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* net: emaclite: Cleanup license to be GPL compatibleMichal Simek2009-09-14-19/+20
| | | | | Signed-off-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com> Signed-off-by: Michal Simek <monstr@monstr.eu>
* net: Remove old Xilinx Emac driverMichal Simek2009-09-14-465/+0
| | | | Signed-off-by: Michal Simek <monstr@monstr.eu>
* fsl: add register read-back to set_law()Timur Tabi2009-09-08-1/+2
| | | | | | | | | After programming a new LAW, we should read-back the LAWAR register so that we sync the writes. Otherwise, code that attempts to use the new LAW-mapped memory might fail right away. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_i2c: increase I2C timeout values and make them configurableTimur Tabi2009-09-06-4/+20
| | | | | | | | | | | | | | | | The value of I2C_TIMEOUT in fsl_i2c.c has several problems. First, it is defined as CONFIG_HZ/4, but it is used as a count of microseconds, so it makes no sense to derive it from a clock rate. Second, the current value (250) is too low for some boards, so it needs to be increased. Third, the timeout necessary for multiple-master arbitration is larger than the timeout for basic read/write operations, so we shouldn't have a single constant for both timeouts. Finally, it would be nice if we could override these values on a per-board basis. Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de> Tested-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Peter Tyser <ptyser@xes-inc.com>
* mxc_nand: Remove Freescale's "All Rights Reserved."Scott Wood2009-09-04-1/+1
| | | | Signed-off-by: Scott Wood <scottwood@freescale.com>
* License cleanup: remove unintended "All Rights Reserved" notices.Wolfgang Denk2009-09-04-4/+0
| | | | | | | | Some files included my old standerd file header which had a "All Rights Reserved" part. As this has never been my intention, I remove these lines to make the files compatible with GPL v.2 and later. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Use different PBA value for E1000 PCI and PCIe cardsRoy Zang2009-09-04-2/+10
| | | | | Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: André Schwarz <andre.schwarz@matrix-vision.de>
* Misc ds1722 fixupsGraeme Russ2009-09-04-1/+2
| | | | | | | | This patch is based on a patch submitted by Jean-Christophe PLAGNIOL-VILLARD on 18th May 2008 as part of a general i386 / sc520 fixup which was never applied Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* Misc ti_pci1410a fixupsGraeme Russ2009-09-04-44/+18
| | | | | | | | | | | | | | | | | | Removed do_pinit() - now declared in cmd_pcmcia.c Added #define CONFIG_CMD_PCMCIA around pcmcia_off() in line with other PCMCIA drivers signed/unsigned type fixups Added semi-colon after default: label as required by newer gcc The only board that appears to use this driver is the sc520_spunk which is very old and very likely very broken anyway. I do not have one to test whether this patch breaks anything functionaly, I have can only check that it compiles without warning or error Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* Misc SATA fixupsGraeme Russ2009-09-04-19/+6
| | | | | | | | | | | | | | | | | Cast first parameter to sata_cpy() In /drivers/block/ata_piix.h, ata_id_has_lba48(), ata_id_has_lba(), ata_id_has_dma(), ata_id_u32(), ata_id_u64() are all defined in include/libata.h which is included in ata.h which is included by all files which include ata_piix.h (only ata_piix.c) so these definitions are supurflous to (and conlict with) this in libata.h. Interestingly, my compiler complains about ata_id_u64 already being defined, but not ata_id_u32 ata_dump_id() is defined in include/libata.h and should not be static (maybe should even use ata_dump_id() in libata.c Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* driver/fsl_pci: Add fsl_pci_init_port function to initialize a PCI controllerPoonam Aggrwal2009-08-28-0/+44
| | | | | | | | | fsl_pci_init_port can be called from board specific PCI initialization routines to setup the PCI (or PCIe) controller. This will reduce code redundancy in most of the 85xx/86xx FSL board ports that setup PCI. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Added single core members of FSL P1xx/P2xx processors seriesPoonam Aggrwal2009-08-28-1/+2
| | | | | | | | P1011 - Single core variant of P1020 P2010 - Single core variant of P2020 Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Added P1020 Processor Support.Poonam Aggrwal2009-08-28-1/+1
| | | | | | | | | | | | | | P1020 is another member of QorIQ series of processors which falls in ULE category. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities. Also the SOC is pin compatible with P2020 Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memoryKumar Gala2009-08-28-63/+162
| | | | | | | | | | | | | | | | | | | | | | | | | | | The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* pci/fsl_pci_init: Use PCIe capability to determine if controller is PCIeKumar Gala2009-08-28-19/+13
| | | | | | | | Change the code to use the PCIe capabilities register to determine if we are a PCIe controller or not. Additionally cleaned up some white space and formatting in the file. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* pci/fsl_pci_init: Fold fsl_pci_setup_inbound_windows into fsl_pci_initKumar Gala2009-08-28-1/+7
| | | | | | | | Every platform that calls fsl_pci_init calls fsl_pci_setup_inbound_windows before it calls fsl_pci_init. There isn't any reason to just call it from fsl_pci_init and simplify things a bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* pci/fsl_pci_init: Fold pci_setup_indirect into fsl_pci_initKumar Gala2009-08-28-2/+4
| | | | | | | | Every platform that calls fsl_pci_init calls pci_setup_indirect before it calls fsl_pci_init. There isn't any reason to just call it from fsl_pci_init and simplify things a bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* NAND: DaVinci: V2 Adding 4 BIT ECC supportSandeep Paulraj2009-08-26-2/+282
| | | | | | | | This patch adds 4 BIT ECC support in the DaVinci NAND driver. Tested on both the DM355 and DM365. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* MTD:NAND: ADD new ECC mode NAND_ECC_HW_OOB_FIRSTSandeep Paulraj2009-08-26-0/+59
| | | | | | | | | | | | | | | | | This patch adds the new mode NAND_ECC_HW_OOB_FIRST in the nand code to support 4-bit ECC on TI DaVinci devices with large page (up to 2K) NAND chips. This ECC mode is similar to NAND_ECC_HW, with the exception of read_page API that first reads the OOB area, reads the data in chunks, feeds the ECC from OOB area to the ECC hw engine and perform any correction on the data as per the ECC status reported by the engine. This patch has been accepted by Andrew Morton and can be found at http://userweb.kernel.org/~akpm/mmotm/broken-out/mtd-nand-add-new-ecc-mode-ecc_hw_oob_first.patch Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Sneha Narnakaje <nsnehaprabha@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* mxc_nand: add nand driver for MX2/MX3Ilya Yanok2009-08-26-0/+881
| | | | | | | | | Driver for NFC NAND controller found on Freescale's MX2 and MX3 processors. Ported from Linux. Tested only with i.MX27 but should works with other MX2 and MX3 processors too. Signed-off-by: Ilya Yanok <yanok@emcraft.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* NAND: ADD page Parameter to all read_page/read_page_raw API'sSandeep Paulraj2009-08-26-8/+10
| | | | | | | | | | | | | | | | This patch adds a new "page" parameter to all NAND read_page/read_page_raw APIs. The read_page API for the new mode ECC_HW_OOB_FIRST requires the page information to send the READOOB command and read the OOB area before the data area. This patch has been accepted by Andrew Morton and can be found at http://userweb.kernel.org/~akpm/mmotm/broken-out/mtd-nand-add-page-parameter-to-all-read_page-read_page_raw-apis.patch WE would like this to become part of the u-boot GIT as well Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Sneha Narnakaje <nsnehaprabha@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* 83xx, kmeter1: added NAND supportHeiko Schocher2009-08-26-0/+136
| | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
* OneNAND: Remove unused read_spareramKyungmin Park2009-08-26-3/+1
| | | | | | | Remove unused read_spareram and add unlock_all as kernel does Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* KB9202: Add NAND supportMatthias Kaehlcke2009-08-26-0/+151
| | | | | | | Add KB9202 NAND driver Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net> Signed-off-by: Scott Wood <scottwood@freescale.com>
* Merge branch 'next' of git://www.denx.de/git/u-boot-coldfire into nextWolfgang Denk2009-08-26-6/+10
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| * ColdFire: Fix compile warning messagesTsiChung Liew2009-08-26-6/+10
| | | | | | | | | | | | | | | | | | Change %08lX to %08X in board.c. Remove unused variable 'oscillator' in mcf5227x/cpu_init.c and 'scm2' in mcf532x/cpu_init.c. Provide argument type cast in drivers/dma/MCD_dmaApi.c. Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
* | Support up to 7 banks for ids as specified in JEDEC JEP106ZNiklaus Giger2009-08-26-2/+80
|/ | | | | | | | see http://www.jedec.org/download/search/jep106Z.pdf Add some second source legacy flash chips 256x8. Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'next' of git://git.denx.de/u-boot-net into nextWolfgang Denk2009-08-25-132/+197
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| * net: tsec - handle user interrupt while waiting for PHY auto negotiation to ↵Kim Phillips2009-08-25-0/+7
| | | | | | | | | | | | | | | | | | | | | | complete if you don't have firmware installed for the PHY to come to life, this wait can be painful - let's give the option to avoid it if we want. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * Add debug message for Blackfin Ethernet Rx function.Robin Getz2009-08-25-0/+3
| | | | | | | | | | | | | | | | Add a simple print for the Blackfin's Ethernet Rx function, so we can debug incomming Ethernet functions easier. Signed-off-by: Robin Getz <rgetz@blackfin.uclinux.org> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * Convert CS8900 Ethernet driver to CONFIG_NET_MULTI APIBen Warren2009-08-25-132/+187
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All in-tree boards that use this controller have CONFIG_NET_MULTI added Also: - changed CONFIG_DRIVER_CS8900 to CONFIG_CS8900 - changed CS8900_BASE to CONFIG_CS8900_BASE - changed CS8900_BUS?? to CONFIG_CS8900_BUS?? - cleaned up line lengths - modified VCMA9 command function that accesses the device - removed MAC address initialization from lib_arm/board.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Tested-by: Wolfgang Denk <wd@denx.de> Acked-by: Wolfgang Denk <wd@denx.de>
* | Merge branch 'master' into nextWolfgang Denk2009-08-25-2/+2
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| * ppc4xx: Fix ECC Correction bug with SMC ordering for NDFC driverFeng Kan2009-08-25-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix ECC Correction bug where the byte offset location were double flipped causing correction routine to toggle the wrong byte location in the ECC segment. The ndfc_calculate_ecc routine change the order of getting the ECC code. /* The NDFC uses Smart Media (SMC) bytes order */ ecc_code[0] = p[2]; ecc_code[1] = p[1]; ecc_code[2] = p[3]; But in the Correction algorithm when calculating the byte offset location, the s1 is used as the upper part of the address. Which again reverse the order making the final byte offset address location incorrect. byteoffs = (s1 << 0) & 0x80; . . byteoffs |= (s0 >> 4) & 0x08; The order is change to read it in straight and let the correction function to revert it to SMC order. Signed-off-by: Feng Kan <fkan@amcc.com> Acked-by: Victor Gallardo <vgallardo@amcc.com> Acked-by: Prodyut Hazarika <phazarika@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | Add driver for the ST M41T94 SPI RTCAlbin Tonnerre2009-08-25-0/+125
| | | | | | | | | | | | | | This RTC is used in some Calao boards. The driver code is taken from the linux rtc-m41t94 driver Signed-off-by: Albin Tonnerre <albin.tonnerre@free-electrons.com>
* | Switch from per-driver to common definition of bin2bcd and bcd2binAlbin Tonnerre2009-08-25-233/+0
| | | | | | | | | | Signed-off-by: Albin Tonnerre <albin.tonnerre@free-electrons.com> Acked-by: Stefan Roese <sr@denx.de>
* | Replace BCD2BIN and BIN2BCD macros with inline functionsAlbin Tonnerre2009-08-25-61/+61
|/ | | | | | | | | | In the process, also remove backward-compatiblity macros BIN_TO_BCD and BCD_TO_BIN and update the sole board using them to use the new bin2bcd and bcd2bin instead Signed-off-by: Albin Tonnerre <albin.tonnerre@free-electrons.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Detlev Zundel <dzu@denx.de>
* eeprom_m95xxx: remove unused variable iJean-Christophe PLAGNIOL-VILLARD2009-08-21-1/+0
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Merge branch 'master' of git://git.denx.de/u-boot-netWolfgang Denk2009-08-21-30/+58
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| * tsec: Wait for auto-negotiation to complete without linkPeter Tyser2009-08-21-10/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, waiting for auto-negotiation would only occur if a valid link had been detected. Problems arose when attempting to use a tsec immediately after bootup but before link was achieved, eg: => dhcp Auto-neg error, defaulting to 10BT/HD eTSEC1: No link. Auto-neg error, defaulting to 10BT/HD eTSEC2: No link. => With this patch applied the same operation as above resulted in: => dhcp Waiting for PHY auto negotiation to complete. done Enet starting in 1000BT/FD Speed: 1000, full duplex Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * arm: kirkwood: See to it that sent data is 8-byte alignedSimon Kagstrom2009-08-21-4/+18
| | | | | | | | | | | | | | | | | | | | U-boot might use non-8-byte-aligned addresses for sending data, which the kwgbe_send doesn't accept (bootp does this for me). This patch copies the data to be sent to a malloced temporary buffer if it is non-aligned. Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * Wait for the link to come up on kirkwood network initSimon Kagstrom2009-08-21-6/+14
| | | | | | | | | | | | | | | | | | | | This patch makes the device wait for up to 5 seconds for the link to come up, similar to what many of the other network drivers do. This avoids confusing situations where, e.g., a tftp fails when initiated early after U-boot has started (before the link has come up). Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * arm:kirkwood Define kirkwood phy address magic numberSimon Kagstrom2009-08-21-4/+10
| | | | | | | | | | Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * e1000: fix PCI memory addressingTimur Tabi2009-08-21-8/+9
| | | | | | | | | | | | | | | | | | | | | | The Intel E1000 driver was making assumptions about the relationship between some virtual, physical, and PCI addresses. Also fix some bad usage of the DEBUGOUT macro Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | add WATCHDOG_RESET() on nand write and readGiulio Benetti2009-08-21-0/+4
|/ | | | | | Signed-off-by: giulio.benetti@micronovasrl.com Acked-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
* flash: Fix CFI buffer size bugJohn Schmoller2009-08-13-1/+1
| | | | | | | | | | | | Fix bug introduced by 9c048b523413ae5f3ff34e00cf57569c3368ab51. The cfi_flash.c driver cast the flash buffer size to a uchar in flash_write_cfibuffer(). On some flash parts, (tested on Numonyx part PC32F512M29EWH), the buffer size is 1KB. Remove the cast to uchar to enable buffer sizes to be larger. Signed-off-by: John Schmoller <jschmoller@xes-inc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* dtt, lm81: move unneccessary printf into a debug printfHeiko Schocher2009-08-11-1/+1
| | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* UEC FIXED PHY: Determine fixed-phy port using UEC interface name.Richard Retanubun2009-08-10-17/+19
| | | | | | | | | | | Fixed a misunderstanding in the original implementation, 'devnum' that was used in the cpu/ppc4xx/4xx_enet.c implementation was NOT the PHY's SMI address, rather it was the number of the MAC interface on the CPU. The equivalent of this for uec_phy will be the UEC number stored in mii_info->dev->name. Usage example is updated for uec. Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* Assigned a static SMI address to all UECs TBIPA address.Richard Retanubun2009-08-10-8/+9
| | | | | | | | | | It is set to 0x1F by default and can be overwritten on the board header file by defining CONFIG_UTBIPAR_INIT_TBIPA. This allows the CPU to simply "reserve" one SMI address instead of using a different one for each UEC. Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* net: kirkwood: updates: used eth_setenv_enetaddr apiPrafulla Wadaskar2009-08-10-6/+9
| | | | | | | | | | | eth_setenv_enetaddr is avaible by upper layer using this saves 204 bytes on total image size used Local OUI instead of Marvell OUI for random MAC address generation logic Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* Fix E1000 build warning on AP1000 boardRoy Zang2009-08-10-44/+44
| | | | | | | | | | Fix E1000 build warning on AP1000 board Fix the build warning on AP1000 board: e1000.c:131: warning: 'e1000_read_eeprom' used but never defined e1000.c:2012: warning: 'e1000_set_phy_mode' defined but not used Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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