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* | Merge branch 'master' of git://git.denx.de/u-boot-nand-flashWolfgang Denk2009-09-30-2/+1
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| * | NAND: davinci: Fix warnings when 4-bit ECC not usedScott Wood2009-09-28-2/+1
| |/ | | | | | | | | | | | | | | | | I accidentally left v2 of "NAND: DaVinci:Adding 4 BIT ECC support" applied when I pushed the tree last merge window, and missed these fixes which were in v3 of that patch. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cWolfgang Denk2009-09-30-36/+69
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| * | fsl_i2c: Do not generate STOP after read.Joakim Tjernlund2009-09-28-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | __i2c_read always ends with a STOP condition thereby releasing the bus. It is cleaner to do the STOP magic in i2c_read(), like i2c_write() does. This may also help future multimaster systems which wants to hold on to the bus until all transactions are finished. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
| * | fsl_i2c: Impl. AN2919, rev 5 to calculate FDR/DFSRJoakim Tjernlund2009-09-28-35/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | The latest AN2919 has changed the way FDR/DFSR should be calculated. Update the driver according to spec. However, Condition 2 is not accounted for as it is not clear how to do so. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Acked-by: Wolfgang Grandegger <wg@grandegger.com>
| * | fsl_i2c: Add CONFIG_FSL_I2C_CUSTOM_{DFSR/FDR}Joakim Tjernlund2009-09-28-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some boards need a higher DFSR value than the spec currently recommends so give these boards the means to define there own. For completeness, add CONFIG_FSL_I2C_CUSTOM_FDR too. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
| * | fsl_i2c: Wait for STOP condition to propagateJoakim Tjernlund2009-09-28-4/+8
| |/ | | | | | | | | | | | | | | | | | | | | | | | | After issuing a STOP one must wait until the STOP has completed on the bus before doing something new to the controller. Also add an extra read of SR as the manual mentions doing that is a good idea. Remove surplus write of CR just before a write, isn't required and could potentially disturb the I2C bus. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
* | net: uec: Fix uccf.h and uec.h headers to include headers they depend onAnton Vorontsov2009-09-25-0/+4
| | | | | | | | | | | | | | | | Headers should include headers containing prototypes and defines they depend on, don't assume that they're included by somebody else. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | net: uec_phy: Implement TXID and RXID RGMII modes for Marvell PHYsAnton Vorontsov2009-09-25-2/+14
|/ | | | | | | This will be needed for MPC8360E-MDS boards with rev. 2.1 CPUs. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2009-09-24-12/+118
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| * ppc/p4080: Add various p4080 related defines (and p4040)Kumar Gala2009-09-24-0/+2
| | | | | | | | | | | | | | | | | | | | | | There are various locations that we have chip specific info: * Makefile for which ddr code to build * Added p4080 & p4040 to cpu_type_list and SVR list * Added number of LAWs for p4080 * Set CONFIG_MAX_CPUS to 8 for p4080 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * ppc/p4080: Add support for CoreNet style platform LAWsKumar Gala2009-09-24-11/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On CoreNet based platforms the LAW address is split between an high & low register and we no longer shift the address. Also, the target IDs on CoreNet platforms have been completely re-assigned. Additionally, added a new find_law() API to which LAW an address hits in. This is need for the CoreNet style boot release code since it will need to determine what the target ID should be set to for boot window translation. Finally, enamed LAWAR_EN to LAW_EN and moved to header so we can use it elsewhere. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * ppc/85xx: Clean up p1_p2_rdb PCI setupKumar Gala2009-09-24-1/+1
| | | | | | | | | | | | | | | | General code cleanup to use in/out IO accessors as well as making the code that prints out info sane between board and generic fsl pci code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | rtc/ds1337.c: Allow to set TCR registerWerner Pfister2009-09-24-0/+4
|/ | | | | | | | This is needed to correctly start the charging of an attached capacitor or battery. Signed-off-by: Werner Pfister <werner.pfister@intercontrol.de> Signed-off-by: Detlev Zundel <dzu@denx.de>
* mpc512x. Micron nand flash needs a reset before a read command is issued.Paul Gibson2009-09-22-0/+1
| | | | | Micron nand flash needs a reset before a read command is issued. The current mpc5121_nfc driver ignores the reset command.
* ppc/85xx: add boot from NAND/eSDHC/eSPI supportMingkai Hu2009-09-15-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch implements these three bootup methods in a unified way - all of these use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM which lets us use the SPD to initialize the SDRAM. For all three bootup methods, the bootup process can be divided into two stages: the first stage will initialize the corresponding controller, configure the L2SRAM, then copy the second stage image to L2SRAM and jump to it. The second stage image is just like the general U-Boot image to configure all the hardware and boot up to U-Boot command line. When boot from NAND, the eLBC controller will first load the first stage image to internal 4K RAM buffer because it's also stored on the NAND flash. The first stage image, also call 4K NAND loader, will initialize the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K NAND loader's code comes from the corresponding nand_spl directory, along with the code twisted by CONFIG_NAND_SPL. When boot from eSDHC/eSPI, there's no such a first stage image because the CPU ROM code does the same work. It will initialize the L2SRAM according to the config addr/word pairs on the fixed address and initialize the eSDHC/eSPI controller, then load the second stage image to L2SRAM and jump to it. The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the second stage image for all different bootup methods. It's set in the board config file when one of the bootup methods above is selected. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of git://git.denx.de/u-boot-microblazeWolfgang Denk2009-09-15-484/+20
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| * net: emaclite: Cleanup license to be GPL compatibleMichal Simek2009-09-14-19/+20
| | | | | | | | | | Signed-off-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com> Signed-off-by: Michal Simek <monstr@monstr.eu>
| * net: Remove old Xilinx Emac driverMichal Simek2009-09-14-465/+0
| | | | | | | | Signed-off-by: Michal Simek <monstr@monstr.eu>
* | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2009-09-15-70/+70
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| * | ppc4xx: Big cleanup of PPC4xx definesStefan Roese2009-09-11-70/+70
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch cleans up multiple issues of the 4xx register (mostly DCR, SDR, CPR, etc) definitions: - Change lower case defines to upper case (plb4_acr -> PLB4_ACR) - Change the defines to better match the names from the user's manuals (e.g. cprpllc -> CPR0_PLLC) - Removal of some unused defines Please test this patch intensive on your PPC4xx platform. Even though I tried not to break anything and tested successfully on multiple 4xx AMCC platforms, testing on custom platforms is recommended. Signed-off-by: Stefan Roese <sr@denx.de>
* | sk98lin: fix compile warningsWolfgang Denk2009-09-15-13/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix warnings: skge.c: In function 'BoardInitMem': skge.c:1389: warning: dereferencing type-punned pointer will break strict-aliasing rules skge.c:1390: warning: dereferencing type-punned pointer will break strict-aliasing rules skge.c:1391: warning: dereferencing type-punned pointer will break strict-aliasing rules skgesirq.c: In function 'SkGePortCheckUpXmac': skgesirq.c:1301: warning: dereferencing type-punned pointer will break strict-aliasing rules skgesirq.c:1301: warning: dereferencing type-punned pointer will break strict-aliasing rules skgesirq.c:1398: warning: dereferencing type-punned pointer will break strict-aliasing rules skgesirq.c:1398: warning: dereferencing type-punned pointer will break strict-aliasing rules skrlmt.c: In function 'SkRlmtInit': skrlmt.c:661: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c: In function 'SkMacPromiscMode': skxmac2.c:753: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c:753: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c: In function 'SkMacHashing': skxmac2.c:803: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c:803: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c: In function 'SkMacFlushTxFifo': skxmac2.c:1115: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c:1115: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c: In function 'SkMacFlushRxFifo': skxmac2.c:1145: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c:1145: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c: In function 'SkXmInitPauseMd': skxmac2.c:1987: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c:1987: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c: In function 'SkXmOverflowStatus': skxmac2.c:4236: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c:4236: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c:4242: warning: dereferencing type-punned pointer will break strict-aliasing rules skxmac2.c:4242: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Ben Warren <biggerbadderben@gmail.com>
* | drivers/net/natsemi.c: fix compile warningWolfgang Denk2009-09-15-1/+2
|/ | | | | | | | Fix warning: natsemi.c:757: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Ben Warren <biggerbadderben@gmail.com>
* fsl: add register read-back to set_law()Timur Tabi2009-09-08-1/+2
| | | | | | | | | After programming a new LAW, we should read-back the LAWAR register so that we sync the writes. Otherwise, code that attempts to use the new LAW-mapped memory might fail right away. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_i2c: increase I2C timeout values and make them configurableTimur Tabi2009-09-06-4/+20
| | | | | | | | | | | | | | | | The value of I2C_TIMEOUT in fsl_i2c.c has several problems. First, it is defined as CONFIG_HZ/4, but it is used as a count of microseconds, so it makes no sense to derive it from a clock rate. Second, the current value (250) is too low for some boards, so it needs to be increased. Third, the timeout necessary for multiple-master arbitration is larger than the timeout for basic read/write operations, so we shouldn't have a single constant for both timeouts. Finally, it would be nice if we could override these values on a per-board basis. Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de> Tested-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Peter Tyser <ptyser@xes-inc.com>
* mxc_nand: Remove Freescale's "All Rights Reserved."Scott Wood2009-09-04-1/+1
| | | | Signed-off-by: Scott Wood <scottwood@freescale.com>
* License cleanup: remove unintended "All Rights Reserved" notices.Wolfgang Denk2009-09-04-4/+0
| | | | | | | | Some files included my old standerd file header which had a "All Rights Reserved" part. As this has never been my intention, I remove these lines to make the files compatible with GPL v.2 and later. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Use different PBA value for E1000 PCI and PCIe cardsRoy Zang2009-09-04-2/+10
| | | | | Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: André Schwarz <andre.schwarz@matrix-vision.de>
* Misc ds1722 fixupsGraeme Russ2009-09-04-1/+2
| | | | | | | | This patch is based on a patch submitted by Jean-Christophe PLAGNIOL-VILLARD on 18th May 2008 as part of a general i386 / sc520 fixup which was never applied Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* Misc ti_pci1410a fixupsGraeme Russ2009-09-04-44/+18
| | | | | | | | | | | | | | | | | | Removed do_pinit() - now declared in cmd_pcmcia.c Added #define CONFIG_CMD_PCMCIA around pcmcia_off() in line with other PCMCIA drivers signed/unsigned type fixups Added semi-colon after default: label as required by newer gcc The only board that appears to use this driver is the sc520_spunk which is very old and very likely very broken anyway. I do not have one to test whether this patch breaks anything functionaly, I have can only check that it compiles without warning or error Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* Misc SATA fixupsGraeme Russ2009-09-04-19/+6
| | | | | | | | | | | | | | | | | Cast first parameter to sata_cpy() In /drivers/block/ata_piix.h, ata_id_has_lba48(), ata_id_has_lba(), ata_id_has_dma(), ata_id_u32(), ata_id_u64() are all defined in include/libata.h which is included in ata.h which is included by all files which include ata_piix.h (only ata_piix.c) so these definitions are supurflous to (and conlict with) this in libata.h. Interestingly, my compiler complains about ata_id_u64 already being defined, but not ata_id_u32 ata_dump_id() is defined in include/libata.h and should not be static (maybe should even use ata_dump_id() in libata.c Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* driver/fsl_pci: Add fsl_pci_init_port function to initialize a PCI controllerPoonam Aggrwal2009-08-28-0/+44
| | | | | | | | | fsl_pci_init_port can be called from board specific PCI initialization routines to setup the PCI (or PCIe) controller. This will reduce code redundancy in most of the 85xx/86xx FSL board ports that setup PCI. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Added single core members of FSL P1xx/P2xx processors seriesPoonam Aggrwal2009-08-28-1/+2
| | | | | | | | P1011 - Single core variant of P1020 P2010 - Single core variant of P2020 Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Added P1020 Processor Support.Poonam Aggrwal2009-08-28-1/+1
| | | | | | | | | | | | | | P1020 is another member of QorIQ series of processors which falls in ULE category. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities. Also the SOC is pin compatible with P2020 Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memoryKumar Gala2009-08-28-63/+162
| | | | | | | | | | | | | | | | | | | | | | | | | | | The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* pci/fsl_pci_init: Use PCIe capability to determine if controller is PCIeKumar Gala2009-08-28-19/+13
| | | | | | | | Change the code to use the PCIe capabilities register to determine if we are a PCIe controller or not. Additionally cleaned up some white space and formatting in the file. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* pci/fsl_pci_init: Fold fsl_pci_setup_inbound_windows into fsl_pci_initKumar Gala2009-08-28-1/+7
| | | | | | | | Every platform that calls fsl_pci_init calls fsl_pci_setup_inbound_windows before it calls fsl_pci_init. There isn't any reason to just call it from fsl_pci_init and simplify things a bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* pci/fsl_pci_init: Fold pci_setup_indirect into fsl_pci_initKumar Gala2009-08-28-2/+4
| | | | | | | | Every platform that calls fsl_pci_init calls pci_setup_indirect before it calls fsl_pci_init. There isn't any reason to just call it from fsl_pci_init and simplify things a bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* NAND: DaVinci: V2 Adding 4 BIT ECC supportSandeep Paulraj2009-08-26-2/+282
| | | | | | | | This patch adds 4 BIT ECC support in the DaVinci NAND driver. Tested on both the DM355 and DM365. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* MTD:NAND: ADD new ECC mode NAND_ECC_HW_OOB_FIRSTSandeep Paulraj2009-08-26-0/+59
| | | | | | | | | | | | | | | | | This patch adds the new mode NAND_ECC_HW_OOB_FIRST in the nand code to support 4-bit ECC on TI DaVinci devices with large page (up to 2K) NAND chips. This ECC mode is similar to NAND_ECC_HW, with the exception of read_page API that first reads the OOB area, reads the data in chunks, feeds the ECC from OOB area to the ECC hw engine and perform any correction on the data as per the ECC status reported by the engine. This patch has been accepted by Andrew Morton and can be found at http://userweb.kernel.org/~akpm/mmotm/broken-out/mtd-nand-add-new-ecc-mode-ecc_hw_oob_first.patch Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Sneha Narnakaje <nsnehaprabha@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* mxc_nand: add nand driver for MX2/MX3Ilya Yanok2009-08-26-0/+881
| | | | | | | | | Driver for NFC NAND controller found on Freescale's MX2 and MX3 processors. Ported from Linux. Tested only with i.MX27 but should works with other MX2 and MX3 processors too. Signed-off-by: Ilya Yanok <yanok@emcraft.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* NAND: ADD page Parameter to all read_page/read_page_raw API'sSandeep Paulraj2009-08-26-8/+10
| | | | | | | | | | | | | | | | This patch adds a new "page" parameter to all NAND read_page/read_page_raw APIs. The read_page API for the new mode ECC_HW_OOB_FIRST requires the page information to send the READOOB command and read the OOB area before the data area. This patch has been accepted by Andrew Morton and can be found at http://userweb.kernel.org/~akpm/mmotm/broken-out/mtd-nand-add-page-parameter-to-all-read_page-read_page_raw-apis.patch WE would like this to become part of the u-boot GIT as well Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Sneha Narnakaje <nsnehaprabha@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* 83xx, kmeter1: added NAND supportHeiko Schocher2009-08-26-0/+136
| | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
* OneNAND: Remove unused read_spareramKyungmin Park2009-08-26-3/+1
| | | | | | | Remove unused read_spareram and add unlock_all as kernel does Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* KB9202: Add NAND supportMatthias Kaehlcke2009-08-26-0/+151
| | | | | | | Add KB9202 NAND driver Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net> Signed-off-by: Scott Wood <scottwood@freescale.com>
* Merge branch 'next' of git://www.denx.de/git/u-boot-coldfire into nextWolfgang Denk2009-08-26-6/+10
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| * ColdFire: Fix compile warning messagesTsiChung Liew2009-08-26-6/+10
| | | | | | | | | | | | | | | | | | Change %08lX to %08X in board.c. Remove unused variable 'oscillator' in mcf5227x/cpu_init.c and 'scm2' in mcf532x/cpu_init.c. Provide argument type cast in drivers/dma/MCD_dmaApi.c. Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
* | Support up to 7 banks for ids as specified in JEDEC JEP106ZNiklaus Giger2009-08-26-2/+80
|/ | | | | | | | see http://www.jedec.org/download/search/jep106Z.pdf Add some second source legacy flash chips 256x8. Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'next' of git://git.denx.de/u-boot-net into nextWolfgang Denk2009-08-25-132/+197
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| * net: tsec - handle user interrupt while waiting for PHY auto negotiation to ↵Kim Phillips2009-08-25-0/+7
| | | | | | | | | | | | | | | | | | | | | | complete if you don't have firmware installed for the PHY to come to life, this wait can be painful - let's give the option to avoid it if we want. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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