| Commit message (Collapse) | Author | Age | Lines |
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Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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This change is in preparation for condtitionial compile support in the
build system. By spliting them all into seperate lines now, subsequent
patches that change 'COBJS-y += ' into 'COBJS-$(CONFIG_<blah>) += ' will
be less invasive and easier to review
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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Signed-off-by: Vlad Lungu <vlad@comsys.ro>
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This was causing problems for some people.
Signed-off-by: Alain Gravel <agravel@fulcrummicro.com>
Signed-off-by: Dan Wilson <dwilson@fulcrummicro.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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Patch 16e23c3f removed PCSRBAR allocation. But passing zero windows
to pciauto_setup_device has the side effect of not getting
COMMAND_MEMORY set.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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Fixed typo in ne2000.h, thinko re n2k_inb() usage, don't try
to do anything in eth_stop() if eth_init() was not called.
Simplified RX path in order to avoid timeouts on really really
fast NE2000 cards (read: qemu with internal tftp), NetLoop() is
clever enough to cope with 1 packet per eth_rx().
Signed-off-by: Vlad Lungu <vlad@comsys.ro>
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Original isp116x-hcd code prepared multiple PTDs for longer than 16
byte transfers for one endpoint. That is unnecessary because the
ISP116x is able to split long data from one PTD into multiple
transactions based on the buffer size of the endpoint. It also caused
serious problems if the endpoint NAKed some of the transactions. In
that case ISP116x wouldn't notice that the other PTDs were for the same
endpoint and would try the other PTDs possibly out of order. That would
break the whole transfer.
This patch makes isp116x_submit_job to use one PTD for one transfer.
Signed-off-by: Timo Ketola <timo.ketola@exertus.fi>
Signed-off-by: Markus Klotzbuecher <mk@denx.de>
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because PowerPC 405 can use UartLite as console
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microblaze toolchain don't support PRAGMA PACK.
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Because PPC405 can use UARTLITE serial interface and
Microblaze can use Uart16550 serial interface not only Uartlite.
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Signed-off-by: Stefan Roese <sr@denx.de>
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[PATCH 2/3] OneNAND support (take #2)
OneNAND support at U-Boot
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
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[PATCH 1/3] OneNAND support (take #2)
OneNAND support at U-Boot
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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Signed-off-by: David Saada <david.saada@ecitele.com>
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Improve indentation in drivers/at45.c
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Fixup for the break statement in wrong place.
[Patch by urwithsughosh@gmail.com]
Acked-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
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Fix usage of do_div() in nand erase|read|write process output.
The last patch to nand_util.c introduced do_div() instead of libgcc's
implementation. But do_div() returns the quotient in its first
macro parameter and not as result.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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This patch add support for the Trizeps IV module (520Mhz).
Signed-off-by: Stefano Babic <sbabic@denx.de>
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Signed-off-by: Jason Jin <Jason.jin@freescale.com>
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o add drivers/sil680.c to support the Sil680 IDE-controller.
o drivers/Makefile: add sil680.o.
Signed-off-by: Gary Jennejohn <garyj@denx.de>
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The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is
set to non-zero, because it doesn't support MRM (memory-read-
multiple) correctly. We now added the possibility to configure
this register in the board config file, so that the default value
of 8 can be overridden.
Here the details of this patch:
o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow
board-specific settings. As an example the sequoia board requires 0.
Idea from Stefan Roese <sr@denx.de>.
o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the
PCI IO-space. Obtained from Stefan Roese <sr@denx.de>.
o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set
CFG_PCI_CACHE_LINE_SIZE to 0.
Signed-off-by: Gary Jennejohn <garyj@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
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