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* dm: mmc: msmsdhic: Drop old MMC codeSimon Glass2016-07-11-16/+1
| | | | | | Now that we have fully moved to driver model, drop the old code. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: mmc: msm_sdhci: Support CONFIG_BLK and CONFIG_DM_MMC_OPSSimon Glass2016-07-11-2/+44
| | | | | | | Add support for using driver model for block devices and MMC operations in this driver. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: mmc: sdhci: Support CONFIG_BLK and CONFIG_DM_MMC_OPSSimon Glass2016-07-11-1/+39
| | | | | | | Add support for using driver model for block devices and MMC operations in this driver. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: mmc: sdhci: Refactor configuration setup to support DMSimon Glass2016-07-11-48/+59
| | | | | | | Move the configuration setting into a separate function which can be used by the driver-model code. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: sandbox: Convert to use CONFIG_CMD_MMC_OPSSimon Glass2016-07-11-11/+6
| | | | | | Update the sandbox MMC emulation to use driver model for MMC operations. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: mmc: rockchip: Enable CONFIG_DM_MMC_OPS for all boardsSimon Glass2016-07-11-1/+2
| | | | | | | Enable this option to move rockchip over to use driver model for MMC operations. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: mmc: dwmmc: Support CONFIG_DM_MMC_OPSSimon Glass2016-07-11-0/+33
| | | | | | Add support to dwmmc for using driver model for MMC operations. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: mmc: Add a way to use driver model for MMC operationsSimon Glass2016-07-11-3/+93
| | | | | | | | | | | | The driver model conversion for MMC has moved in small steps. The first step was to have an MMC device (CONFIG_DM_MMC). The second was to use a child block device (CONFIG_BLK). The final one is to use driver model for MMC operations (CONFIG_DM_MMC_OP). Add support for this. The immediate priority is to make all boards that use DM_MMC also use those other two options. This will allow them to be removed. Signed-off-by: Simon Glass <sjg@chromium.org>
* mmc: Move tracing code into separate functionsSimon Glass2016-07-11-15/+45
| | | | | | | Move this code into separate functions so that it can be used from the uclass also. Add static inline versions for when the option is disabled. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: mmc: rockchip: Support only CONFIG_BLKSimon Glass2016-07-11-11/+0
| | | | | | Since all Rockchip boards use CONFIG_BLK, we can remove this old code. Signed-off-by: Simon Glass <sjg@chromium.org>
* mmc: Move MMC boot code into its own fileSimon Glass2016-07-11-125/+146
| | | | | | | Rather than having an #ifdef in the main mmc.c file, control this feature from the Makefile by moving the code into its own file. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: mmc: Move non-CONFIG_BLK code into mmc_legacy.cSimon Glass2016-07-11-95/+91
| | | | | | Rather than having #ifdef in mmc.c, move this code into the legacy file. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: mmc: Move CONFIG_BLK code into the mmc uclassSimon Glass2016-07-11-82/+83
| | | | | | Rather than having #ifdef in mmc.c, move this code into the uclass file. Signed-off-by: Simon Glass <sjg@chromium.org>
* mmc: Add function declarations for mmc_bread() and mmc_switch_part()Simon Glass2016-07-11-5/+21
| | | | | | | These private functions are used both in the driver-model implementation and in the legacy code. Add them to the header. Signed-off-by: Simon Glass <sjg@chromium.org>
* mmc: msm_sdhci: Set mmc->dev pointer in msm_sdc_probe()Mateusz Kulikowski2016-07-08-1/+6
| | | | | | | | | | | MMC core expects (now) valid mmc->dev pointer. During conversion in commit cffe5d86 not every driver was updated. This patch fixes crash while accessing MMC on boards using Qualcomm SDHCI controller. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2016-07-06-301/+69
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| * tegra: video: Always use write-through cache on LCDSimon Glass2016-07-05-18/+3
| | | | | | | | | | | | | | | | This seems to give the best performance, so let's use it always. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * video: tegra: Move to using simple-panel and pwm-backlightSimon Glass2016-07-05-263/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have standard drivers for panels and backlights which can do most of the work for us. Move the tegra20 LCD driver over to use those instead of custom code. This patch includes device tree changes for the nvidia boards. I have only been able to test seaboard. If this patch is applied, these boards will also need to be synced with the kernel, and updated to use display-timings: - colibri - medcom-wide - paz00 - tec Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * pci: tegra: actually program REFCLK_CFG* on recent SoCsStephen Warren2016-07-05-9/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On recent SoCs, tegra_pcie_phy_enable() isn't called; but instead tegra_pcie_enable_controller() calls tegra_xusb_phy_enable(). However, part of tegra_pcie_phy_enable() needs to happen in all cases. Move that code to tegra_pcie_port_enable() instead. For reference, NVIDIA's downstream Linux kernel performs this operation in tegra_pcie_enable_rp_features(), which is called immediately after tegra_pcie_port_enable(). Since that function doesn't exist in the U-Boot driver, we'll just add it to the tail of tegra_pcie_port_enable() instead. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * pci: tegra: correctly program PADS_REFCLK registersStephen Warren2016-07-05-13/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The value that should be programmed into the PADS_REFCLK register varies per SoC. Fix the Tegra PCIe driver to program the correct values. Future SoCs will require different values in cfg0/1, so the two values are stored separately in the per-SoC data structures. For reference, the values are all documented in NV bug 1771116 comment 20. The Tegra210 value doesn't match the current TRM, but I've filed a bug to get the TRM fixed. Earlier TRMs don't document the value this register should contain, but the ASIC team has validated all these values, except for the Tegra20 value which is simply left unchanged in this patch. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2016-07-06-5/+44
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| * | net: rtl8169: Fix return value for rtl_send_commonOleksandr Tymoshenko2016-07-06-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Return value of rtl_send_common propogates unmodified all the way up to eth_send and further to API consumer if CONFIG_API is enabled. Previously rtl_send_common returned number of bytes sent on success which was erroneouly detected as error condition by API consumers that checked for operation success by comparing return value with 0. Switch rtl_send_common to use common convention: return 0 on success and negative value for failure. Cc: Stephen Warren <swarren@nvidia.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Oleksandr Tymoshenko <gonzo@bluezbox.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | driver: net: phylib: add support for aquantia AQR106/107 PHYMingkai Hu2016-07-06-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for aquantia AQR106/107 PHY. Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: designware: Make driver independent from DM_GPIO againAlexey Brodkin2016-07-06-3/+14
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 90b7fc924adf "net: designware: support phy reset device-tree bindings" made DW GMAC driver dependent on DM_GPIO by unconditional usage of purely DM_GPIO stuff like: * dm_gpio_XXX() * gpio_request_by_name() But since that driver as of today might be easily used without DM_GPIO (that's the case for Synopsys AXS10x boards) we're shielding all DM_GPIO things by ifdefs. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Simon Glass <sjg@chromium.org> Cc: Beniamino Galvani <b.galvani@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Cc: Sonic Zhang <sonic.zhang@analog.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | rockchip: video: Lower hpd wait timeSjoerd Simons2016-07-05-1/+1
|/ | | | | | | | | | | | | Waiting 30 seconds for the hpd to go high seems a bit much, especially on headless boots. Lowering the timeout to 300ms. Sending as RFC because frankly i don't know what a sensible timeout is here, but 30 seconds is clearly not it :) Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Simon Glass <sjg@chromium.org> Dropped RFC tag: Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-07-01-4/+9
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| * ehci: mx7: fix otg id detectionPeng Fan2016-06-25-2/+5
| | | | | | | | | | | | | | | | | | | | The USBNC_PHYCFG2_ACAENB bit should be cleared to enable the OTG ID detection, not set it. When the bit is set, the ACA Resistance Detection is enabled, which disables the OTG ID detection, because the internal pull up is off. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * ehci: mx7: fix usbnc_regsPeng Fan2016-06-25-1/+2
| | | | | | | | | | | | | | | | There is a 4 bytes hole between phy_cfg2 and phy_status, fix the usbnc_regs structure to include the hole. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * usb: fsl: Fix NULL terminating issue for usb controller name stringRajesh Bhagat2016-06-25-1/+2
| | | | | | | | | | | | | | Fixes NULL terminating issue for usb controller name string by using sizeof operator. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2016-07-01-315/+530
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| * | pinctrl: uniphier: add Ethernet pin-mux settingsMasahiro Yamada2016-07-02-0/+94
| | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: avoid building unneeded pin-mux tables for SPLMasahiro Yamada2016-07-02-171/+192
| | | | | | | | | | | | | | | | | | | | | SPL does not use all of the devices, so we can save some memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: support pin configuration for dedicated pinsMasahiro Yamada2016-07-02-154/+149
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PH1-LD4 and PH1-sLD8 SoCs have pins that support pin configuration (pin biasing, drive strength control), but not pin-muxing. Allow to fill the mux value table with -1 for those pins; pins with mux value -1 will be skipped in the pin-mux set function. The mux value type should be changed from "unsigned" to "int" in order to accommodate -1 as a special case. [ Linux commit: 363c90e743b50a432a91a211dd8b078d9df446e9 ] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: split pinctrl driver for PH1-LD11 and PH1-LD20Masahiro Yamada2016-07-02-8/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PH1-LD11 and PH1-LD20 have much pin controlling in common, so I added a single driver shared between them in the initial commit. However, the Ethernet pin-mux settings I am going to add are different with each other, and they may diverge more as the progress of development. Split it into two dedicated drivers. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: allow to have pinctrl node under syscon nodeMasahiro Yamada2016-07-02-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the UniPhier pinctrl driver itself is a syscon, but it turned out much more reasonable to make it a child node of a syscon because our syscon node consists of a bunch of system configuration registers, not only pinctrl, but also phy, and misc registers. It is difficult to split the node. This commit allows to migrate to the new DT structure. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: remove unneeded pin group nand_cs1Masahiro Yamada2016-06-30-3/+0
| | | | | | | | | | | | | | | | | | | | | This SoC does not support NAND CS1. This place-holder is no longer necessary. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: fix NAND pin-mux setting for PH1-LD11/LD20Masahiro Yamada2016-06-30-2/+2
| | | | | | | | | | | | | | | | | | My mistake in the initial support patch. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: remove wrong pin-mux functions for ProXstream2Masahiro Yamada2016-06-30-2/+0
| | | | | | | | | | | | | | | | | | These are pin group names, not function names. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | mmc: increase MMC SDHCI read status timeoutSteve Rae2016-07-01-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Otherwise, ocassionally see errors like this: Flashing sparse image at offset 2078720 Flashing Sparse Image sdhci_send_command: Timeout for status update! mmc fail to send stop cmd write_sparse_image: Write failed, block #2181088 [0] This does not affect the actual writing speed, which is controlled by the default value: CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT It only increases the retries when reading: SDHCI_INT_STATUS to avoid the timeout error. Signed-off-by: Steve Rae <steve.rae@raedomain.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
* | | driver: qspi: correct QSPI disable CS reset valuePraneeth Bajjuri2016-07-01-1/+1
|/ / | | | | | | | | | | | | | | | | | | | | Correcting QSPI disable/unselect CS reset value. CTRL_CORE_CONTROL_IO_2: QSPI_MEMMAPPED_CS[10:8] This is not causing any issue, but its better to untouch the reserved bits. Praneeth Bajjuri <praneeth@ti.com> Signed-off-by: Ravi Babu <ravibabu@ti.com>
* | Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-06-28-16/+56
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| * | armv8: fsl-layerscape: Append "A" in SoC name for ARM based SoCsPrabhakar Kushwaha2016-06-28-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale ARMv8 SoC name ends with "A" to represent ARM SoCs. like LS2080A, LS1043A, LS1012A. So append "A" to SoC names. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | mmc: fsl: introduce wp_enablePeng Fan2016-06-28-3/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introudce wp_enable. To check WPSPL, wp_enable needs to be set to 1 in board code. Take i.MX6UL for example, for some boards, they do not use WP singal, so they does not configure USDHC1_WP_SELECT_INPUT, and its default value is 0(GPIO1_IO02). However GPIO1_IO02 is muxed for i2c usage and SION bit set. So USDHC controller can always get wp signal and WPSPL shows write protect and blocks driver continuing. This is not what we want to see, so add wp_enable, and if set to 0, just omit the WPSPL checking and this does not effect normal working of usdhc controller. If wp-gpios is provided in dts, wp_enable is set to 1, otherwise 0. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: York Sun <york.sun@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | fsl_esdhc: Update clock enable bits for USDHCYe Li2016-06-28-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The USDHC moves the 4 clock bits CARD_CLK_SOFT_EN, IPG_PERCLK_SOFT_EN, HCLK_SOFT_EN, and IPG_CLK_SOFT_EN from sysctl register to vendorspec register. The driver uses RSTA to replace the clock gate off operation. But this is not a good solution because: 1. when using RSTA, we should wait this bit to clear by itself. This is not implemeneted in the code. 2. After RSTA is set, it is recommended that the Host Driver reset the external card and reinitialize it. So in this patch, we change to use the vendorspec registers for these bits operation. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: York Sun <york.sun@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | mmc: fsl: reset to normal boot mode when eMMC fast bootPeng Fan2016-06-28-9/+29
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When booting in eMMC fast boot, MMC host does not exit from boot mode after bootrom loading image. So the first command 'CMD0' sent in uboot will pull down the CMD line to low and cause errors. This patch cleans the MMC boot register in "mmc_init" to put the MMC host back to normal mode. Also clear DLL_CTRL delay line settings at USDHC initialization to eliminate the pre-settings from boot rom. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: York Sun <york.sun@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | fastboot: sparse: resync common/image-sparse.c (part 2)Steve Rae2016-06-27-12/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - update fastboot_okay() and fastboot_fail() This file originally came from upstream code. While retaining the storage abstraction feature, this is the second set of the changes required to resync with the cmd_flash_mmc_sparse_img() in the file aboot.c from https://us.codeaurora.org/cgit/quic/la/kernel/lk/plain/app/aboot/aboot.c?h=LE.BR.1.2.1 Signed-off-by: Steve Rae <srae@broadcom.com>
* | fastboot: sparse: remove session-id logicSteve Rae2016-06-27-14/+2
| | | | | | | | | | | | | | This "session-id" alogrithm is not required, and currently corrupts the stored image whenever more the one "session" is required. Signed-off-by: Steve Rae <srae@broadcom.com>
* | mmc: dw_mmc: fix the wrong AND operationJaehoon Chung2016-06-27-2/+2
| | | | | | | | | | | | | | | | | | | | These condition checking are wrong. Original Author's intention might be "&" instead of "&&". It can know whether receive or transmit data request with BIT[4]/BIT[5] of RINTSTS register. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | clk: sandbox: don't check clk ID against 0Stephen Warren2016-06-24-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | clk->id is unsigned, so it can't be < 0. Remove the check for that. FWIW, this issue was introduced when the clock API converted e.g. clk_get_rate()'s clock ID parameter from an int to an unsigned long (with a struct clk), without removing this check. Fixes: 135aa9500264 ("clk: convert API to match reset/mailbox style") Reported-by: Coverity Scan Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* | mtd: nand: Drop a blank line in nand_wait()Andre Renaud2016-06-24-1/+0
|/ | | | | | | This empty line should not be there. Remove it. Signed-off-by: Andre Renaud <andre@designa-electronics.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org> Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-12-28 19:31:17 +0000