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* mmc: fsl_esdhc fix register offsetPeng Fan2015-03-17-1/+1
| | | | | | | | | | Commit f022d36e8a4517b2a9d25ff2d75bd2459d0c68b1 introduces error register offset. Change the "char reserved3[59]" to "char reserved3[56]". Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
* ARM: UniPhier: adjust device trees for business transferMasahiro Yamada2015-03-15-13/+18
| | | | | | | Panasonic's System LSI products, UniPhier SoC family, have been transferred to Socionext Inc. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* sunxi: musb: Support checking VBUS using AXP221 PMICChen-Yu Tsai2015-03-10-14/+38
| | | | | | | | | | | | | | | | This enables the musb glue layer to use the AXP221's VBUS detection function to check for VBUS. This fixes otg support on the A23 q8h tablets. Note that u-boot never calls musb_shutdown(), so once VBUS is enabled, it is never disabled until the system is powered off, or the OS does so. This can be used to our advantage to keep VBUS powered into the OS, where support for AXP221 is not available yet. Fixes: 52defe8f6570 ("sunxi: musb: Check Vbus-det before enabling otg port power") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: axp221: Add VBUS detection supportChen-Yu Tsai2015-03-10-0/+16
| | | | | | | | | | | Some of the AXP PMICs support VBUS detection, i.e. checking whether VBUS power input is available and usable (supplied by an external source). A few boards use this instead of a separate GPIO to detect VBUS on USB OTG. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* dfu: mmc: file buffer: remove static allocationPrzemyslaw Marczak2015-03-09-3/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For writing files, DFU implementation requires the file buffer with the len at least of file size. For big files it requires the same big buffer. Previously the file buffer was allocated as a static variable, so it was a part of U-Boot .bss section. For 32MiB len of buffer we have 32MiB of additional space, required for this section. The .bss needs to be cleared after the relocation. This introduces an additional boot delay at every start, but usually the dfu feature is not required at the standard boot, so the buffer should be allocated only if required. This patch removes the static allocation of this buffer, and alloc it with memalign after first call of function: - dfu_fill_entity_mmc() and the buffer is freed on dfu_free_entity() call. This was tested on Trats2. A quick test with trace. Boot time from start to main_loop() entry: - ~888ms - before this change (arch memset enabled for .bss clear) - ~464ms - after this change Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Tom Rini <trini@konsulko.com> Cc: Marek Vasut <marek.vasut@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-dmTom Rini2015-03-08-0/+2
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| * dm: i2c: Add a missing memory allocaton checkSimon Glass2015-03-05-0/+2
| | | | | | | | | | | | | | This strdup() is missing a check. Add it. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2015-03-05-1/+157
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| * | fsl_sec_mon: Add driver for Security Monitor block of Freescalegaurav rana2015-03-05-0/+155
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Security Monitor is the SOC’s central reporting point for security-relevant events such as the success or failure of boot software validation and the detection of potential security compromises. The API's for transition of Security states have been added which will be used in case of SECURE BOOT. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | rsa : Compile Modular Exponentiation files based on CONFIG_RSA_SOFTWARE_EXPgaurav rana2015-03-05-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove dependency of rsa_mod_exp from CONFIG_FIT_SIGNATURE. As rsa modular exponentiation is an independent module and can be invoked independently. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Acked-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <yorksun@freescale.com>
* | | omap: gpmc: 'nandecc sw' can use HAM1 or BCH8Ash Charles2015-03-05-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'nandecc sw' command selects a software-based error correction algorithm. By default, this is OMAP_ECC_HAM1_CODE_SW but some platforms use OMAP_ECC_BCH8_CODE_HW_DETECTION_SW as their software-based correction algorithm. Allow a user to be specific e.g. # nandecc sw <hamming|bch8> where 'hamming' is still the default. Note: we don't just use CONFIG_NAND_OMAP_ECCSCHEME as it might be set to a hardware-based ECC scheme---a little strange when the user has requested 'sw' ECC. Signed-off-by: Ash Charles <ashcharles@gmail.com>
* | | mtd: nand: omap_gpmc: Make ready/busy pins configurableMichal Sojka2015-03-05-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit fb384c4720ca7496775d6578f184bf628db73456 introduced the use of WAIT0 pin for determining whether the NAND is ready or not. This only works if all NAND chips are connected to WAIT0. If some chips are connected to the other available pin WAIT1, nand_wait() does not really wait and prints a WARN_ON message. This patch allows the board to provide configuration of which chip is connected to which WAITx signal. For example, one can define in include/configs/foo.h: #define CONFIG_NAND_OMAP_GPMC_WSCFG 0,0,1,1 This would mean that chips using to CS0 and 1 are connected to WAIT0 and chips with CS2 and 3 are connected to WAIT1. Signed-off-by: Michal Sojka <sojka@merica.cz> Acked-by: Stefan Roese <sr@denx.de> Tested-by: Michal Vokáč <michal.vokac@comap.cz> Cc: Tom Rini <trini@ti.com>
* | | drivers/video/am335x-fb: Add possibility to wait for stable power/pictureHannes Petermaier2015-03-05-7/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Often on boards exists a circuit which switches power on/off to LCD display. Due to the need of limiting the in-rush current the output voltage from this circuit rises "slowly", so it is necessary to wait a bit (VCC ramp up time) before starting output on LCD-pins. This time is specified in <n> ms within the panel-settings, called "pup_delay" Further some LCDs need a couple of frames to stabilize the image on it. We have now the possibility to wait some time after starting output on LCD. This time is also specified in <n> ms within panel-settings, called "pon_delay" Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
* | | net: Support DMA threshold mode in DWMAC driverSonic Zhang2015-03-05-0/+5
| | | | | | | | | | | | | | | | | | - DMA threshold mode can be selected in board config head file. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
* | | net: configure DWMAC DMA by default AXI burst lengthSonic Zhang2015-03-05-1/+7
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | Board can define its own AXI burst length to improve DWMAC DMA performance. v2-changes: - Avoid write burst len register when the Macro is not defined. v3-changes: - Add axi_bus register member to struct eth_dma_regs. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-03-05-14/+282
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| * | imx6: Added DEK blob generator commandRaul Cardenas2015-03-02-7/+256
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's SEC block has built-in Data Encryption Key(DEK) Blob Protocol which provides a method for protecting a DEK for non-secure memory storage. SEC block protects data in a data structure called a Secret Key Blob, which provides both confidentiality and integrity protection. Every time the blob encapsulation is executed, a AES-256 key is randomly generated to encrypt the DEK. This key is encrypted with the OTP Secret key from SoC. The resulting blob consists of the encrypted AES-256 key, the encrypted DEK, and a 16-bit MAC. During decapsulation, the reverse process is performed to get back the original DEK. A caveat to the blob decapsulation process, is that the DEK is decrypted in secure-memory and can only be read by FSL SEC HW. The DEK is used to decrypt data during encrypted boot. Commands added -------------- dek_blob - encapsulating DEK as a cryptgraphic blob Commands Syntax --------------- dek_blob src dst len Encapsulate and create blob of a len-bits DEK at address src and store the result at address dst. Signed-off-by: Raul Cardenas <Ulises.Cardenas@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Ulises Cardenas <ulises.cardenas@freescale.com> Signed-off-by: Ulises Cardenas-B45798 <Ulises.Cardenas@freescale.com>
| * | Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2015-03-02-1138/+2207
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| * | | mmc: fsl_esdhc: Add support to force VSELECT setOtavio Salvador2015-02-23-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some boards cannot do voltage negotiation but need to set the VSELECT bit forcely to ensure it to work at 1.8V. This commit adds CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT flag for this use. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
| * | | mmc: fsl_esdhc: Add CMD11 support to switch to 1.8VOtavio Salvador2015-02-23-7/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support to switch to 1.8V in case CMD11 succeeds. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Marek Vasut <marex@denx.de>
* | | | dm: tegra: Enable driver model in SPL and adjust the GPIO driverSimon Glass2015-03-04-16/+15
| |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the full driver model GPIO and serial drivers in SPL now that these are supported. Since device tree is not available they will use platform data. Remove the special SPL GPIO function as it is no longer needed. This is all in one commit to maintain bisectability. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | serial: ns16550: Fix build error due to a typoAxel Lin2015-03-02-1/+1
| | | | | | | | | | | | | | | | | | | | | Fix trivial typo. Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Axel Lin <axel.lin@ingics.com>
* | | Merge git://git.denx.de/u-boot-usbTom Rini2015-03-02-6/+98
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| * | | usb: gadget: fastboot: Set the Serial Number for Fastboot GadgetDileep Katta2015-02-25-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Configure the serial number using the serial# environment variable during the fastboot bind. This enables "fastboot devices" to return the serial number for the attached devices. Signed-off-by: Dileep Katta <dileep.katta@linaro.org> Acked-by: Steve Rae <srae@broadcom.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
| * | | fastboot: OUT transaction length must be aligned to wMaxPacketSizeDileep Katta2015-02-25-5/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OUT transactions must be aligned to wMaxPacketSize for each transfer, or else transfer will not complete successfully. This patch modifies rx_bytes_expected to return a transfer length that is aligned to wMaxPacketSize. Note that the value of wMaxPacketSize and ep->maxpacket may not be the same value, and it is the value of wMaxPacketSize that should be used for alignment. wMaxPacketSize is passed depending on the speed of connection. Signed-off-by: Dileep Katta <dileep.katta@linaro.org> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
| * | | usb: gadget: fastboot: Add fastboot eraseDileep Katta2015-02-25-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds the fastboot erase functionality, to erase a partition specified by name. The erase is performed based on erase group size, to avoid erasing other partitions. The start address and the size is aligned to the erase group size for this. Currently only supports erasing from eMMC. Signed-off-by: Dileep Katta <dileep.katta@linaro.org> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
| * | | dfu: samsung: move call to set_dfu_alt_info() to dfu common codePrzemyslaw Marczak2015-02-25-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This common call can be used for setting proper entities based on dfu command arguments. The config: CONFIG_SET_DFU_ALT_INFO, was used only for few configs, and now it is common. The board file should implement: - set_dfu_alt_info() function Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [Test HW: Odroid U3 (Exynos 4412)]
| * | | fastboot: add support for "oem format" commandRob Herring2015-02-25-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add "oem format" command to write partition table. This relies on the env variable partitions to contain the list of partitions as required by the gpt command. Note that this does not erase any data other than the partition table. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Steve Rae <srae@broadcom.com>
| * | | fastboot: add "fastboot oem" command supportMichael Scott2015-02-25-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add code stub to handle "fastboot oem __" command. As unlock is a common fastboot command, distinguish that it is not implemented. Signed-off-by: Michael Scott <michael.scott@linaro.org> Signed-off-by: Rob Herring <robh@kernel.org> Tested-by: Steve Rae <srae@broadcom.com>
| * | | usb: musb-new: omap2430: Reset the MUSB controller earlyPaul Kocialkowski2015-02-24-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When booting from USB peripheral boot, the bootrom will not properly deinit the MUSB controller, which doesn't clearly indicate an USB disconnection to the host and leaves U-Boot to deal with the state of the previous USB session. On some host controller drivers (e.g. xhci_hcd), this ends up in a failure during set address, caused by the lack of proper disconnection notification. Resetting the controller early in U-Boot notifies the host of the disconnection and doesn't hurt other use cases. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@ti.com>
| * | | exynos: usb: make dwc3_set_mode to staticJoonyoung Shim2015-02-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The dwc3_set_mode function is used only in drivers/usb/host/xhci-exynos5.c so make it to static. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2015-03-01-45/+140
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| * | | | usb: UniPhier: add UniPhier on-chip xHCI host driver supportMasahiro Yamada2015-03-01-0/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support xHCI host driver used on Panasonic UniPhier platform. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Marek Vasut <marex@denx.de>
| * | | | ARM: UniPhier: move uniphier_ehci_reset() functionMasahiro Yamada2015-03-01-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because uniphier_ehci_reset() is only called from ehci-uniphier.c, it can be a static function there. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Marek Vasut <marex@denx.de>
| * | | | ARM: UniPhier: remove EHCI platform devicesMasahiro Yamada2015-03-01-14/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now UniPhier platform highly depends on Device Tree configuration (CONFIG_OF_CONTROL is select'ed by Kconfig). Since the EHCI is only used on main U-Boot, we can drop platform devices of the EHCI controllers. We still keep UART platform devices because they might be useful for SPL. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Marek Vasut <marex@denx.de>
| * | | | serial: UniPhier: move LCR register setting to probe functionMasahiro Yamada2015-03-01-9/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We do not have to set the LCR register every time we change the baud-rate. We just need to set it up once in the probe function. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | | serial: UniPhier: use 32 bit register accessMasahiro Yamada2015-03-01-28/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For PH1-Pro4, the 8 bit write access to LCR register (offset = 0x11) is not working correctly. As a side effect, it also modifies MCR register (offset = 0x10) and results in unexpected behavior. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | | ARM: UniPhier: include <mach/*.h> instead of <asm/arch/*.h>Masahiro Yamada2015-03-01-1/+1
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 0e7368c6c426 (kbuild: prepare for moving headers into mach-*/include/mach), we can replace #include <asm/arch/*.h> with <mach/*.h> so we do not need to create the symbolic link during the build. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2015-03-01-3/+4
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| * | | serial: sh: fix internal clock source on SCIFVladimir Barinov2015-02-25-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The formula to calculate SCIF BRR for R-Car H2/M2/E2 SoCs is as follows: BRR = pclk / (64 * 2^(2n-1) * baudrate) - 1, the prescaler is 0 due to SCSMR settings, hence n=0 Also SCSCR must be set to use internal or external clock source. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | serial: sh: Remove invalid UTF-8 characterNobuhiro Iwamatsu2015-02-25-1/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | serial_sh.c contains invalid UTF-8 character. This deletes the character. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-02-25-210/+1219
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| * | | crypto/fsl - Add progressive hashing support using hardware acceleration.gaurav rana2015-02-25-1/+171
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently only normal hashing is supported using hardware acceleration. Added support for progressive hashing using hardware. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> CC: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | crypto/fsl: Make function names consistent for blob encapsulation/decapsulation.gaurav rana2015-02-25-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch does the following: 1. The function names for encapsulation and decapsulation were inconsitent in freescale's implementation and cmd_blob file. This patch corrects the issues. 2. The function protopye is also modified to change the length parameter from u8 to u32 to allow encapsulation and decapsulation of larger images. 3. Modified the description of km paramter in the command usage for better readability. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | mmc: fsl_esdhc: Add support for DDR modeVolodymyr Riazantsev2015-02-24-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support of the DDR mode for eSDHC driver. Enable it for i.MX6 SoC family only. Signed-off-by: Volodymyr Riazantsev <volodymyr.riazantsev@globallogic.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | driver/pci: add Layerscape PCIe driverMinghuan Lian2015-02-24-5/+466
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch adds Freescale Layerscape PCIe driver and provides up to 4 controllers support. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | drivers/mc: Migrated MC Flibs to 0.5.2J. German Rivera2015-02-24-46/+295
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Upgrade Manage Complex (MC) flib API to 0.5.2. Rename directory fsl_mc to fsl-mc. Change the fsl-mc node in Linux device tree from "fsl,dprcr" to "fsl-mc". Print MC version info when appropriate. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | driver/ddr/fsl: Add sync of refreshYork Sun2015-02-24-0/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add sync of refresh for multiple DDR controllers. DDRC initialization needs to complete first. Code is re-ordered to keep refresh close. Signed-off-by: York Sun <yorksun@freescale.com>
| * | | driver/ddr/fsl: Fix a typo in timing_cfg_8 calculationYork Sun2015-02-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | wwt_bg should match rrt_bg. It was a typo in driver. Signed-off-by: York Sun <yorksun@freescale.com>
| * | | driver/ddr/fsl: Add support for multiple DDR clocksYork Sun2015-02-24-152/+180
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Controller number is passed for function calls to support individual DDR clock, depending on SoC implementation. It is backward compatible with exising platforms. Multiple clocks have been verifyed on LS2085A emulator. Signed-off-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-11-28 17:18:21 +0000