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* pmic: tps65218: add useful functions and definesNikita Kiryanov2016-02-24-0/+56
| | | | | | | | | | | | | | | | Add the following functions: tps65218_reg_read() for accessing redisters tps65218_toggle_fseal() for toggling the fseal bit tps65218_lock_fsea() for locking the fseal bit to 1 Add the following defines: All status register bits Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Reviewed-by: Tom Rini <trini@konsulko.com>
* pci_rom: fix may be used uninitialized warningAndreas Bießmann2016-02-24-1/+1
| | | | | | | | | | | | | | | | Building pci_rom.c with my toolchain complains about may be used uninitialized rom varaible: ---8<--- +drivers/pci/pci_rom.c:269:25: note: 'rom' was declared here w+drivers/pci/pci_rom.c: In function 'dm_pci_run_vga_bios': w+drivers/pci/pci_rom.c:154:14: warning: 'rom' may be used uninitialized in this function [-Wmaybe-uninitialized] --->8--- Fix this as done in 55616b86c745fcac5a791268ab8e7cba36965c0f the ram variable. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Anatolij Gustschin <agust@denx.de>
* stm32: add support for stm32f7 & stm32f746 discovery boardVikas Manocha2016-02-24-3/+3
| | | | | | This patch adds support for stm32f7 family & stm32f746 board. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* stm32x7: add support for stm32x7 serial driverVikas Manocha2016-02-24-0/+121
| | | | | | | This patch adds support for stm32f7 family usart peripheral. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* gpio: stm32_gpio: move base addresses to the soc fileVikas Manocha2016-02-24-18/+0
| | | | | | | Base addresses for GPIOs could be different for different socs, this patch moves the base addresses from driver to the soc specific location. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* gpio: stm32_gpio: move clock config from driver to boardVikas Manocha2016-02-24-5/+0
| | | | | | | This patch removes the gpio clock enable from gpio driver & move it in the board code, making it possible to use the gpio driver with other socs. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-02-23-16/+62
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| * sunxi: H3: Add support for the host usb-physJelle van der Waa2016-02-23-16/+16
| | | | | | | | | | | | | | | | Add support for phy 1-3. Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl> [hdegoede@redhat.com: use setclrbits_le32 instead of read-modify-write] Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: power: add support for sy8106a driverJelle van der Waa2016-02-23-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SY8106A is a PMIC which is used on the Allwinner H3 Orange Pi Pc and Plus board. The VOUT1_SEL register is implemented to set the default V-CPU voltage to 1200 mV. This driver is required to ensure the SY8106A V-CPU voltage is set to 1200 mV after a software reset. On cold boot the default SY8106A output voltage is selected to be 1200 mV by a pair of resistors on the Orange Pi PC and Plus. Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl> Tested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2016-02-23-5/+187
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| * | spi: spi-uclass: Set slave wordlen with SPI_DEFAULT_WORDLENChristophe Ricard2016-02-23-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | In some case wordlen may not be set. Use SPI_DEFAULT_WORDLEN as default. Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | spi: omap3: Remove unused variable irqstatus in omap3_spi_txrxChristophe Ricard2016-02-23-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | Remove unused variable irqstatus in omap3_spi_txrx Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | drivers: dma: ti-edma3: convert driver to adopt driver modelMugunthan V N2016-02-23-2/+80
| | | | | | | | | | | | | | | | | | | | | | | | adopt ti-edma3 driver to device driver model Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | spi: ti_qspi: compile out spi_flash_copy_mmap when CONFIG_DMA is definedMugunthan V N2016-02-23-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_DMA is defined the default spi_flash_copy_mmap() can handle dma memory copy, so compile out spi_flash_copy_mmap() from ti_qspi driver when CONFIG_DMA config is defined. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | sf: spi_flash: use dma to copy data from mmap region if platform supportsMugunthan V N2016-02-23-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add dma memcpy api to the default spi_flash_copy_mmap(), so that dma will be used to copy data when CONFIG_DMA is defined for the platform. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | dma: Kconfig: Add TI_EDMA3 entryMugunthan V N2016-02-23-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Add TI_EDMA3 entry on Kconfig with help description. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | dm: implement a DMA uclassMugunthan V N2016-02-23-0/+89
| |/ | | | | | | | | | | | | | | | | | | Implement a DMA uclass so that the devices like ethernet, spi, mmc etc can offload the data transfers from/to the device and memory. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini2016-02-22-2/+179
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| * | video: Add S3C24xx framebuffer supportMarek Vasut2016-02-22-1/+174
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add basic framebuffer driver for the S3C24xx family of CPUs. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Vladimir Zapolskiy <vz@mleia.com> V2: Keep the Makefile sorted. Acked-by: Anatolij Gustschin <agust@denx.de>
| * | video: freetype: Fix a memory leak with a bad parameterSimon Glass2016-02-22-1/+4
| | | | | | | | | | | | | | | | | | | | | Make sure to free memory used when the scale facture is incorrect. Reported-by: Coverity (CID: 24068) Signed-off-by: Simon Glass <sjg@chromium.org>
| * | video: truetype: Fix a memory leak on errorSimon Glass2016-02-22-0/+1
| |/ | | | | | | | | | | | | | | | | When the resolution is not supported we should free the memory we don't plan to use. Reported-by: Coverity (CID: 135127) Signed-off-by: Simon Glass <sjg@chromium.org>
* | net: phy: realtek: Use generic genphy_parse_link() for RTL8211EMichal Simek2016-02-22-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The problem with current implementation is that SPDDONE bit is 1 but link bit is zero. That's why phydev->link is setup to 0 which ending up in driver failure that link is not up. Log: Zynq> dhcp ethernet@e000b000 Waiting for PHY auto negotiation to complete....... done ethernet@e000b000: No link. There is at least 1ms delay between spddone bit and link up. Use genphy_read_status() instead of realtek implemenation which is working with page 11. Linux driver is also using generic implementation. Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | dm: ns16550: Add support for reg-offset propertyMichal Simek2016-02-22-2/+4
| | | | | | | | | | | | | | | | | | | | reg-offset is the part of standard 8250 binding in the kernel. It is shifting start of address space by reg-offset. On Xilinx platform this offset is typically 0x1000. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | serial: zynq: Change logic in putcMichal Simek2016-02-22-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sync logic with Linux kernel where TX empty flag is checked before char is sent. This logic is fixing problem with console on zynqmp platform. For example: DRAM: 2 GiB Enabling Caches... EL Level: �� sdhci@ff170000: 0 Using default environment Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
* | mmc: Kconfig: Add Arasan SDHCI entryMichal Simek2016-02-22-0/+6
|/ | | | | | Add Arasan SDHCI entry to Kconfig and fix all references. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-02-21-9/+429
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| * pinctrl: imx: Support i.MX7DPeng Fan2016-02-21-0/+56
| | | | | | | | | | | | | | | | | | | | | | Introudce i.MX7 pinctrl driver support. For now only i.MX7D supported. There are two iomux controllers in i.MX7D, iomuxc and iomuxc_lpsr. To iomuxc_lpsr, ZERO_OFFSET_VALID is set, means offset of mux_reg and conf_reg can begin at 0. Signed-off-by: Peng Fan <van.freenix@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * pinctrl: imx: Introduce pinctrl driver for i.MX6Peng Fan2016-02-21-0/+352
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce pinctrl for i.MX6 1. pinctrl-imx.c is for common usage. It's used by i.MX6/7. 2. Add PINCTRL_IMX PINCTRL_IMX6 Kconfig entry. 3. To the pinctrl_ops implementation, only set_state is implemented. To i.MX6/7, the pinctrl dts entry is as following: &iomuxc { pinctrl-names = "default"; pinctrl_csi1: csi1grp { fsl,pins = < MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 >; }; [.....] }; there is no property named function or groups. So pinctrl_generic_set_state can not be used here. 5. This driver is a simple implementation for i.mx iomux controller, only parse the fsl,pins property and write value to registers. 6. With DEBUG enabled, we can see log when "i2c bus 0": " set_state_simple op missing imx_pinctrl_set_state: i2c1grp mux_reg 0x14c, conf_reg 0x3bc, input_reg 0x5d8, mux_mode 0x0, input_val 0x1, config_val 0x4000007f write mux: offset 0x14c val 0x10 select_input: offset 0x5d8 val 0x1 write config: offset 0x3bc val 0x7f mux_reg 0x148, conf_reg 0x3b8, input_reg 0x5d4, mux_mode 0x0, input_val 0x1, config_val 0x4000007f write mux: offset 0x148 val 0x10 select_input: offset 0x5d4 val 0x1 write config: offset 0x3b8 val 0x7f " this means imx6 pinctrl driver works as expected. Signed-off-by: Peng Fan <van.freenix@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * imx: Refactoring CAAM Job Ring structure and Secure Memory for imx7Ulises Cardenas2016-02-21-9/+21
| | | | | | | | | | | | | | | | | | | | | | | | Refactored data structure for CAAM's job ring and Secure Memory to support i.MX7. The new memory map use macros to resolve SM's offset by version. This will solve the versioning issue caused by the new version of secure memory of i.MX7 Signed-off-by: Ulises Cardenas <raul.casas@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
* | superio: Add SMSC SIO1007 driverBin Meng2016-02-21-0/+127
| | | | | | | | | | | | | | | | | | | | | | The SMSC SIO1007 superio chipset integrates two ns16550 compatible serial ports for legacy applications, 16 GPIO pins and some other functionalities like power management. This adds a simple driver to enable serial port and handle GPIO. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2016-02-20-92/+28
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| * | drivers: usb: ohci-at91: clean up the PLLB codeWenyou Yang2016-02-18-15/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Due to introducing the new PLLB clock handle functions, use these functions to clean up the PLLB enable/disable code. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Tested-by: Heiko Schocher <hs@denx.de>
| * | drivers: usb: atmel: clean up the UTMI PLL codeWenyou Yang2016-02-18-47/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Due to introducing the new UTMI PLL clock handle functions, use these function to reduce the duplicated code. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | drivers: at91: clean up peripheral clock codeWenyou Yang2016-02-18-29/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to introducing the new peripheral clock handle functions, use these functions to reduce the duplicated code. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> [fixup for missing clk.h in at91_emac.c] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2016-02-19-412/+908
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| * | | tegra: video: Move LCD driver to use the DM PWM driverSimon Glass2016-02-16-4/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the driver-model PWM driver in preference to the old code. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: Convert CONFIG_PWM_TEGRA to KconfigSimon Glass2016-02-16-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move this option to Kconfig and clean up the header files. Adjust the only user (the LCD driver) to work with the new driver. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: video: Move all fdt-decoding into a single functionSimon Glass2016-02-16-159/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Join the two functions which decode the device tree and put them in the ofdata_to_platdata() method. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: video: Move LCD enums into the driverSimon Glass2016-02-16-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to have these in a separate file as they are not referenced from anywhere else. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: video: Remove the static variablesSimon Glass2016-02-16-16/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can move the static variables into the driver-private data. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: video: Convert tegra20 LCD driver to driver modelSimon Glass2016-02-16-213/+172
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move this driver over to use driver model. This involves rearranging the code somewhat. The effect is that everything is run from the probe() method. Boards which use this are fixed up, but only seaboard is tested. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: video: Merge the two config structures togetherSimon Glass2016-02-16-19/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have a structure for the display panel and another for the controller. There is some overlap between them. Merge them to simplify the driver. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: video: Move the check for CONFIG_OF_CONTROL to KconfigSimon Glass2016-02-16-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can check this in Kconfig now. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: video: Merge the display driver into one fileSimon Glass2016-02-16-0/+396
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present we have code in arch/arm and code in drivers/video. Move it all into drivers/video since it is a display driver and our current approach is to put all driver code in drivers/. Make a few functions static now that they are not used outside the file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: video: Rename CONFIG_VIDEO_TEGRA to CONFIG_VIDEO_TEGRA20Simon Glass2016-02-16-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This option refers only to the tegra20 video driver, so name it as such to avoid confusion with tegra124. Also move this option to Kconfig. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: nyan-big: Move the LCD driver to driver modelSimon Glass2016-02-16-194/+237
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adjust the driver to use driver model. The SOR becomes a bridge device. We use the normal simple_panel driver to handle the display itself. We also need to enable some options such as regulators, PWMs and DM_VIDEO itself. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: lcd: Merge tegra124-lcd.c into display.cSimon Glass2016-02-16-98/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There isn't a lot of benefit of have two separate files. With driver model the code needs to be in the same driver, so it's better to have it in the same file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: pwm: Add a driver for the tegra PWMSimon Glass2016-02-16-0/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This PWM supports four channels. The driver always uses the 32KHz clock, and adjusts the duty cycle accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: gpio: Show the GPIO value for outputsSimon Glass2016-02-16-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The tegra GPIO controller has two ways of reading the value of a GPIO. It can supply the 'input' value (which is the value read from the pin) and the 'output' value (which is the value being driven from the pin. With a GPIO set to output mode, the 'input' value is always low which is not very useful. This has the unfortunate result that setting a GPIO high still leaves it showing as low in the 'gpio status' command. Adjust the driver to check which direction the GPIO is set to, then read the value from the appropriate register: 'input' for input GPIOs, 'output' for output GPIOs. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: mmc: Fix comments in the MMC driver initSimon Glass2016-02-16-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the SoC names in two comments. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
generated by cgit v1.1 at 2024-12-22 22:32:17 +0000