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* usb: dwc2: Simplify wait_for_chhltd(), remove ignore_ackStefan Brüns2016-01-23-23/+17
| | | | | | | | | | | | A transfer is completed if the XFERCOMP flag is set, irrespective of the ACK flag. BULK OUT transfers to some HS devices complete without having the ACK flag set, which signal the devices has responded with an NYET to the transfer (PING protocol). The new behaviour matches the Linux kernel minus any PING protocol. Also see 5966defabdcc (usb: dwc2: fix bulk transfers) Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
* usb: dwc2: Fix out-of-bounds access, fix chunk sizeStefan Brüns2016-01-23-15/+15
| | | | | | | | | | | | | | | | | | | | | | | Fix two errors in transfer len calculation, move loop invariant code out of loop. If xfer_len is equal to CONFIG_DWC2_MAX_TRANSFER_SIZE (or slightly smaller), the xfer_len will be to large, e.g.: xfer_len = MAX_TRANSFER_SIZE = 65535 max packet size = 512 => num_packets = 128 => IN xfer_len = 65536 For OUT transactions larger than (65536 - mps) bytes, the xfer_len determination is quite awkward, it is only correct due to: - max_packet_size for control/bulk/interrupt is required to be power-of-two. - (CONFIG_DWC2_MAX_TRANSFER_SIZE + 1) % max-packet-size is zero for all allowed (2^3 ... 2^9) packet sizes As the max xfer len is loop invariant, it can be moved out of the loop. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
* rockchip: spl: Support full-speed CPU in SPLSimon Glass2016-01-21-0/+56
| | | | | | | | Add a feature which speeds up the CPU to full speed in SPL to minimise boot time. This is only supported for certain boards (at present only jerry). Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3288: pinctrl: Fix HDMI pinctrlSimon Glass2016-01-21-0/+2
| | | | | | | Since the device tree does not specify the EDID pinctrl option for HDMI we must set it manually. Fix the driver to handle this. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3288: clock: Fix various minor errorsSimon Glass2016-01-21-8/+13
| | | | | | Fix a number of small errors which were found in reviewing the clock code. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: video: Add a video-output driverSimon Glass2016-01-21-1/+347
| | | | | | | | Some rockchip SoCs include video output (VOP). Add a driver to support this. It can output via a display driver (UCLASS_DISPLAY) and currently HDMI and eDP are supported. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: video: Add a display driver for rockchip eDPSimon Glass2016-01-21-1/+1086
| | | | | | | Some Rockchip SoCs support embedded DisplayPort output. Add a display driver for this so that these displays can be used on supported boards. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: video: Add a display driver for rockchip HDMISimon Glass2016-01-21-0/+952
| | | | | | | | | | | | Some Rockchip SoCs support HDMI output. Add a display driver for this so that these displays can be used on supported boards. Unfortunately this driver is not fully functional. It cannot reliably read EDID information over HDMI. This seems to be due to the clocks being incorrect - the I2C bus speed appears to be up to 100x slower than the clock settings indicate. The root cause may be in the clock logic. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: clk: Add support for clocks needed by the displaysSimon Glass2016-01-21-4/+170
| | | | | | | The displays need to use NPLL and also select some new peripheral clocks. Add support for these to the clock driver. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Rename the CRU_MODE_CON fieldsSimon Glass2016-01-21-30/+9
| | | | | | These should match the datasheet naming. Adjust them. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: video: Repurpose the 'displayport' uclass to 'display'Simon Glass2016-01-21-57/+71
| | | | | | | | | | | | | | The current DisplayPort uclass is too specific. The operations it provides are shared with other types of output devices, such as HDMI and LVDS LCD displays. Generalise the uclass so that it can be used with these devices as well. Adjust the uclass to handle the EDID reading and conversion to display_timing internally. Also update nyan-big which is affected by this. Signed-off-by: Simon Glass <sjg@chromium.org>
* video: panel: Add a simple panel driverSimon Glass2016-01-21-1/+100
| | | | | | | | Most panels are very simple - they just have a power supply and a backlight. Add a driver which supports this and implements the enable_backlight() method. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: panel: Add a panel uclassSimon Glass2016-01-21-0/+26
| | | | | | | | LCD panels can usefully be modelled as their own uclass. They can be probed (which powers them up ready for use). If they have a backlight, this can be enabled. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: backlight: Add a driver for a PWM backlightSimon Glass2016-01-21-0/+137
| | | | | | | Many backlights need to use a PWM to control the brightness. Add a driver for this. It understands the standard device tree binding. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: backlight: Add a backlight uclassSimon Glass2016-01-21-0/+26
| | | | | | | | LCD panels normally have a backlight which can be controlled to illuminate the LCD contents. Add a uclass to support this. Initially it only has a method to enable the backlight. Signed-off-by: Simon Glass <sjg@chromium.org>
* pwm: rockchip: Add a PWM driver for Rockchip SoCsSimon Glass2016-01-21-0/+113
| | | | | | Add a simple driver which implements the standard PWM uclass interface. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: pwm: Add a PWM uclassSimon Glass2016-01-21-0/+49
| | | | | | | Add a uclass that supports Pulse Width Modulation (PWM) devices. It provides methods to enable/disable and configure the device. Signed-off-by: Simon Glass <sjg@chromium.org>
* video: bridge: Allow GPIOs to be optionalSimon Glass2016-01-21-4/+7
| | | | | | | Some video bridges will not have GPIOs to control reset, etc. Allow these to be optional. Signed-off-by: Simon Glass <sjg@chromium.org>
* video: Add a function to control cache flushingSimon Glass2016-01-21-0/+7
| | | | | | Allow the cache-flushing function of a video device to be controlled. Signed-off-by: Simon Glass <sjg@chromium.org>
* video: Name consoles by their numberSimon Glass2016-01-21-1/+6
| | | | | | | | | | | | We must use the console name in the 'stdout' variable to select the one we want. At present the name is formed from the driver name with a suffix indicating the rotation value. It seems better to name them sequentially since this can be controlled by driver order. So adjust the code to use 'vidconsole' for the first, 'vidconsole1' for the second, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: spi: Remove the explicit pinctrl settingSimon Glass2016-01-21-26/+2
| | | | | | | | The correct pinctrl is handled automatically so we don't need to do it in the driver. The exception is when we want to use a different chip select (other than 0). But this isn't used at present. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: spi: Correct chip-enable codeSimon Glass2016-01-21-1/+6
| | | | | | | | At present there is an incorrect call to rkspi_enable_chip(). It should be disabling the chip, not enabling it. Correct this and ensure that the chip is disabled when releasing the bus. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: spi: Implement the delaysSimon Glass2016-01-21-4/+23
| | | | | | | | Some devices need delays before and after activiation. Implement these features in the SPI driver so that we will be able to enable the Chrome OS EC. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: gpio: Implement the get_function() methodSimon Glass2016-01-21-4/+36
| | | | | | | Provide this method so that 'gpio status' works fully. It now shows whether a pin is used for input, output or some other function. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: gpio: Read the GPIO value correctlySimon Glass2016-01-21-1/+1
| | | | | | This function should return 0 or 1, not a mask. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: pinctrl: Implement the get_gpio_mux() methodSimon Glass2016-01-21-16/+52
| | | | | | | Implement this so that the GPIO command will be able to report whether a GPIO is used for input or output. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: pinctrl: Reduce the size for SPLSimon Glass2016-01-21-3/+17
| | | | | | | This file has many features that are not needed by SPL. Use #ifdef to remove the unused features and reduce the code size. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: clk: Make rkclk_get_clk() SoC-specificSimon Glass2016-01-21-0/+30
| | | | | | | | | | | | The current method assumes that clocks are numbered from 0 and we can determine a clock by its number. It is safer to use an ID in the clock's platform data to avoid the situation where another clock is bound before the one we expect. Move the existing code into rk3036 since it still works there. Add a new implementation for rk3288. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: spi: Correct the bus init codeSimon Glass2016-01-21-2/+2
| | | | | | | Two of the init values are created locally so cannot be out of range. The masking is unnecessary and in one case is incorrect. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: spi: Remember the last speed to avoid re-setting itSimon Glass2016-01-21-1/+4
| | | | | | | Rather than changing the clock to the same value on every transaction, remember the last value and don't adjust the clock unless it is necessary. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: clk: Add a simple version of clk_get_by_index()Simon Glass2016-01-21-1/+17
| | | | | | | This function adds quite a bit of code to SPL and we probably don't need all the features in SPL. Add a simple version (for SPL only) to save space. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: power: Allow regulators to not implement all operationsSimon Glass2016-01-21-0/+2
| | | | | | | | Some regulators will not implement any operations (e.g. fixed regulators). This is not an error, so allow the autoset process to continue when one of these regulators is found. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: power: Tidy up debugging output and return valuesSimon Glass2016-01-21-8/+19
| | | | | | | | The currect PMIC debugging is a little confusing. Adjust it so that it is clear whether the operation succeeded or failed. Also, avoid creating a new error return value when a perfectly good one is already available. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: core: Export uclass_find_device_by_of_offset()Simon Glass2016-01-21-2/+2
| | | | | | | | It is sometimes useful to be able to find a device before probing it, perhaps to set up some platform data for it. Allow finding by of_offset also. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: pinctrl: Add a way for a GPIO driver to obtain a pin functionSimon Glass2016-01-21-0/+10
| | | | | | | | | | | | | GPIO drivers want to be able to show if a pin is enabled for input, output, or is being used by another function. Some drivers can easily find this and the code is included in the driver. For some SoCs this is more complex. Conceptually this should be handled by pinctrl rather than GPIO. Most pinctrl drivers will have this feature anyway. Add a method by which a GPIO driver can obtain the pin mux value given a GPIO reference. This avoids repeating the code in two places. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: power: Allow regulators to be omitted from SPLSimon Glass2016-01-21-2/+34
| | | | | | | | For some boards the pmic interface is useful but the regulator interface (which comes with it) is too large. Allow them to be separated such that SPL can decide which it needs. Signed-off-by: Simon Glass <sjg@chromium.org>
* spi: Correct device tree usage in spi_flash_decode_fdt()Simon Glass2016-01-21-6/+3
| | | | | | | | | | | This function currently searches the entire device tree for a node that it thinks is relevant. But the node is known and is passed in. Correct the code and enable it only with driver model, since only driver-model boards will use it. This avoids bringing in a large number of strings from fdtdec. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: i2c: Allow muxes to be enabled for SPL separatelySimon Glass2016-01-21-3/+12
| | | | | | | Since I2C muxes are seldom needed in SPL, and the code for this increases the size somewhat, add a separate option to enable I2C muxes for SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
* cros_ec: Disable the Chrome OS EC in SPLSimon Glass2016-01-21-0/+2
| | | | | | | This is not used in SPL so don't allow it to be built there, even if I2C is enabled in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: pinctrl: Add a full pinctrl driverSimon Glass2016-01-21-1/+229
| | | | | | | We can make use of the device tree to configure pinctrl settings. Add this support for the driver so we can use it in U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: mmc: Update the driver to use the new clock IDSimon Glass2016-01-21-1/+1
| | | | | | We can use the new clk_get_by_index() function to get the correct clock. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: spi: Avoid setting the pinctrl twiceSimon Glass2016-01-21-3/+6
| | | | | | | | If full pinctrl is enabled we don't need to manually set the pinctrl in the driver. It will happen automatically. Adjust the code to suit - we will still use manual mode in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: spi: Update the driver to use the new clock IDSimon Glass2016-01-21-15/+17
| | | | | | We can use the new clk_get_by_index() function to get the correct clock. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: i2c: Update the driver to use the new clock IDSimon Glass2016-01-21-16/+22
| | | | | | We can use the new clk_get_by_index() function to get the correct clock. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: clock: Add a function to find a clock by IDSimon Glass2016-01-21-2/+22
| | | | | | | | The current approach of using uclass_get_device() is error-prone. Another clock (for example a fixed-clock) may cause it to break. Add a function that does a proper search. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: clk: Add a function to get a peripheral clock rateSimon Glass2016-01-21-0/+37
| | | | | | | It is useful to be able to read the rate of a peripheral clock. Add a handler for that. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: clock: Rename the general clock variable to gclk_rateSimon Glass2016-01-21-12/+12
| | | | | | The current name is confusing and a bit verbose. Rename it. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Use a separate clock ID for clocksSimon Glass2016-01-21-44/+48
| | | | | | | | | | At present we use the same peripheral ID for clocks and pinctrl. While this works it is probably better to use the device tree clock binding ID for clocks. We can use the clk_get_by_index() function to find this. Update the clock drivers and the code that uses them. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: mmc: Use a pwrseq device if availableSimon Glass2016-01-21-0/+47
| | | | | | | Use the pwrseq uclass to find a suitable power sequence for the MMC device. If this is enabled in the device tree, we will pick it up automatically. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Convert the PMU IOMUX registers into an arraySimon Glass2016-01-21-2/+2
| | | | | | | | | This is easier to deal with when using generic code since it allows us to use a register index instead of naming each register. Adjust it, adding an enum to improve readability. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-12-21 12:32:54 +0000