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* Merge branch 'u-boot-sunxi/master' into 'u-boot-arm/master'Albert ARIBAUD2014-08-09-0/+218
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| * sunxi: add USB EHCI driverRoman Byshko2014-07-31-0/+202
| | | | | | | | | | | | | | | | | | The Allwinner aka sunxi SoCs have one or more USB host controllers. This adds a driver for their EHCI. Signed-off-by: Roman Byshko <rbyshko@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * ahci: provide sunxi SATA driver using AHCI platform frameworkIan Campbell2014-07-31-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This enables the necessary clocks, in AHB0 and in PLL6_CFG. This is done for sun7i only since I don't have access to any other sunxi platforms with sata included. The PHY setup is derived from the Alwinner releases and Linux, but is mostly undocumented. The Allwinner AHCI controller also requires some magic (and, again, undocumented) DMA initialisation when starting a port. This is added under a suitable ifdef. This option is enabled for Cubieboard, Cubieboard2 and Cubietruck based on contents of Linux DTS files, including SATA power pin config taken from the DTS. All build tested, but runtime tested on Cubieboard2 and Cubietruck only. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Change Andy Fleming's email addressAndy Fleming2014-08-06-2/+2
| | | | | | | | | | | | | | Messages to afleming@freescale.com now bounce, and should be directed to my personal address at afleming@gmail.com Signed-off-by: Andy Fleming <afleming@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2014-08-06-8/+25
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| * | spi, spi_mxc: do not hang in spi_xchg_singleHeiko Schocher2014-08-06-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | if status register do never set MXC_CSPICTRL_TC, spi_xchg_single endless loops. Add a timeout here to prevent endless hang. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Dirk Behme <dirk.behme@gmail.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | spi: Support half-duplex mode in FDT decodeSimon Glass2014-08-06-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | This parameter should also be supported. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | exynos: spi: Fix calculation of SPI transaction start timeSimon Glass2014-08-06-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPI transaction delay is supposed to be measured from the end of one transaction to the start of the next. The code does not work that way, so fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | cros_ec: Fix two bugs in the SPI implementationSimon Glass2014-08-06-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | An incorrect message version is passed to the EC in some cases and the parameters of one function are switched. Fix these problems. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | sf: sf_ops: Stop leaking memoryMarek Vasut2014-08-06-0/+1
| |/ | | | | | | | | | | | | | | | | It's usually a common pattern to free() the memory that we allocated. Implement this here to stop leaking memory. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* | MMC: atmel_mci: enable high speed mode supportBo Shen2014-08-01-1/+6
| | | | | | | | | | | | | | | | If the MCI IP version >= 0x300, it supports hight speed mode option, this patch enable it. Signed-off-by: Bo Shen <voice.shen@atmel.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* | MMC: atmel_mci: refactor setting the mode registerBo Shen2014-08-01-14/+42
| | | | | | | | | | | | | | | | The mode register is different between MCI IP version. So, according to MCI IP version to set the mode register. Signed-off-by: Bo Shen <voice.shen@atmel.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* | mmc/dw_mmc: Fix clock divider calculation error for bypass modeChin Liang See2014-08-01-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | To fix the clock divider calculation error when the controller clock same as the operating frequency. This is known as bypass mode. In this mode, the divider should be 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Mischa Jonker <mjonker@synopsys.com>
* | mmc: s3c: Add SD driverMarek Vasut2014-08-01-0/+322
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement SD driver for the S3C24xx family. This implementation is currently only capable of using the PIO transfers, DMA is not supported. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* | bcm2835_sdhci: Add SDHCI_QUIRK_NO_HISPD_BIT flagLubomir Rintel2014-08-01-1/+1
| | | | | | | | | | | | | | | | Seems like the controller doesn't support the flag. None of the hi-speed cards I've tried could be read, while they successfully worked with the quirk enabled. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Tested-by: Stephen Warren <swarren@wwwdotorg.org>
* | ARM: kirkwood: add mvsdio driverDrEagle2014-08-01-0/+362
|/ | | | | | | | | This patch add Marvell kirkwood MVSDIO/MMC driver and enable it for Sheevaplugs and OpenRD boards. Signed-off-by: Gerald Kerma <drEagle@doukki.net> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-07-29-256/+730
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| * Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2014-07-28-5/+225
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| | * keystone2: use CONFIG_SOC_KEYSTONE in common placesKhoronzhuk, Ivan2014-07-25-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Use CONFIG_SOC_KEYSTONE in common places instead of defining a lot of "if def .. || if def " for different Keystone2 SoC types. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * mtd: nand: davinci: add opportunity to write keystone U-boot imageKhoronzhuk, Ivan2014-07-25-0/+196
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Keystone SoCs use the same NAND driver as Davinci. This patch adds opportunity to write Keystone U-boot image to NAND device using appropriate RBL ECC layout. This is needed only if RBL boots U-boot from NAND device and that's supposed that raw u-boot partition is used only for writing image. The main problem is that default Davinci ECC layout is different from Keystone RBL layout. To read U-boot image the RBL needs that image was written using RBL ECC layout. The BBT table is written using default Davinci layout and has to be updated using one. The BBT can be updated only while erasing chip or by forced bad block assigning, so erase function has to use native ecc layout in order to be able to write BBT correctly. So if we're writing to NAND U-boot address we use RBL layout for others we use default ECC layout. Also remove definition for CONFIG_CMD_NAND_ECCLAYOUT as there is no reasons to use ECC layout commands. It was added by mistake. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * tps65218/am43xx_evm: Add power framework support to TPS65218Tom Rini2014-07-25-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | Add in an init function for the drivers/power framework so we can dump and read the registers via i2c. Cc: Łukasz Majewski <l.majewski@samsung.com> Signed-off-by: Tom Rini <trini@ti.com>
| | * drivers: net: cpsw: add support for using second port as ethernetMugunthan V N2014-07-25-3/+5
| | | | | | | | | | | | | | | | | | | | | Add support for using the second slave port of cpsw to be used as primary ethernet. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
| * | Merge branch 'u-boot-sh/rmobile' into 'u-boot-arm/master'Albert ARIBAUD2014-07-28-5/+9
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| | * | serial: sh: Add support R8A7794Nobuhiro Iwamatsu2014-07-24-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | This adds the preset value to register for R8A7794. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| | * | net: sh-eth: Add support R8A7794Nobuhiro Iwamatsu2014-07-24-4/+7
| | |/ | | | | | | | | | | | | | | | | | | R8A7794 has the same sh-ether IP core as other SH/rmobile. This patch adds support of R8A7794. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * | Merge branch 'u-boot-sunxi/master' into 'u-boot-arm/master'Albert ARIBAUD2014-07-28-246/+496
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| | * | sunxi: add gpio driverIan Campbell2014-07-18-0/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables CONFIG_CMD_GPIO for the Allwinner (sunxi) platform as well as providing the common gpio API (gpio_request/free, direction in/out, get/set etc). Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ma Haijun <mahaijuns@gmail.com> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Cc: Henrik Nordström <henrik@henriknordstrom.net> Cc: Tom Cubie <Mr.hipboi@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
| | * | sunxi: Add axp152 pmic supportHans de Goede2014-07-18-0/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the x-powers axp152 pmic which is found on most A10s boards and enable it for the r7-tv-dongle board. Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| | * | sunxi: Add axp209 pmic supportHenrik Nordstrom2014-07-18-0/+168
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the x-powers axp209 pmic which is found on most A10, A13 and A20 boards. And enable AXP209 support for the Cubietruck and Cubieboard boards. Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| | * | sunxi: Add i2c supportHans de Goede2014-07-18-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the i2c controller found on all Allwinner sunxi SoCs, this is the same controller as found on the Marvell orion5x and kirkwood SoC families, with a slightly different register layout, so this patch uses the existing mvtwsi code. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-By: Prafulla Wadaskar <prafulla@marvell.com> Acked-by: Heiko Schocher <hs@denx.de> [ ijc -- updated u-boot-spl-fel.lds ]
| | * | mvtwsi: convert to CONFIG_SYS_I2C frameworkHans de Goede2014-07-16-39/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Note this has only been tested on Allwinner sunxi devices (support for which gets introduced by a later patch). The kirkwood changes have been compile tested using the wireless_space board config, the orion5x changes have been compile tested using the edminiv2 board config. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Heiko Schocher <hs@denx.de>
| | * | net: Rename and cleanup sunxi (Allwinner) emac driverStefan Roese2014-07-06-73/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There have been 3 versions of the sunxi_emac support patch during its development. Somehow version 2 ended up in upstream u-boot where as the u-boot-sunxi git repo got version 3. This bumps the version in upstream u-boot to version 3 of the patch: - Initialize MII clock earlier so mii access to allow independent use - Name change from WEMAC to EMAC to match mainline kernel & chip manual - Cosmetic code cleanup Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| | * | sunxi: Remove mmc DMA supportHans de Goede2014-07-06-134/+7
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DMA code in sunxi_mmc.c is broken. mmc_trans_data_by_dma() allocates the dma descriptors on the stack, and then exits while the dma transfer is in progress, so the dma engine is reading stack memory which at that point may be re-used. So far we've gotten away with this by luck, but recent u-boot changes have shifted the stack start address by 16 bytes, which combined with dma alignment now exposes this problem. Since we end up just busy waiting for the dma engine anyway, this commit fixes things by simply removing the dma code, resulting in smaller bug-free code. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-07-28-18/+74
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| * | driver/ddr: Fix DDR register timing_cfg_8York Sun2014-07-22-0/+3
| | | | | | | | | | | | | | | | | | | | | The field wrtord_bg should add 2 clocks if on the fly chop is enabled, according to DDR controller manual for DDR4. Signed-off-by: York Sun <yorksun@freescale.com>
| * | driver/ddr: Fix DDR4 driver for ARMYork Sun2014-07-22-2/+5
| | | | | | | | | | | | | | | | | | | | | Previously the driver was only tested on Power SoCs. Different barrier instructions are needed for ARM SoCs. Signed-off-by: York Sun <yorksun@freescale.com>
| * | driver/nand: Add support of 16K SRAM for IFC 2.0Prabhakar Kushwaha2014-07-22-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Internal SRAM has been incresed from 8KB to 16KB for IFC cotroller ver 2.0. Update the page offset calculation logic to support the same. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | fsl/pcie: Change 'no link' to 'undetermined' for pcie endpointZang Roy-R619112014-07-22-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Even u-boot boots up, the pcie link may not setup correctly when Freescale SOC acts as endpoint. So change the link status from 'no link' to 'undetermined' to reduce the confusion. The link status can check from host side eventually. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | driver/nand: Update SRAM initialize logic for IFC.Prabhakar Kushwaha2014-07-22-4/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IFC controller v1.1.0 requires internal SRAM initialize by reading NAND flash. Higher controller versions have provided "SRAM init" bit in NCFGR register space. update SRAM initialize logic to reflect the same. Also print error message in case of Page read error. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | driver/nand:Define MAX_BANKS same as SoC defined for IFCPrabhakar Kushwaha2014-07-22-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The number of chip select used by IFC controller vary from one SoC to other. For eg. P1010 has 4, T4240 has 8. Update MAX_BANKS same as SoC defined Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | qe: move immap_qe.h from arch directory into common directoryZhao Qiang2014-07-22-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | ls1021 is arm-core and supports qe too. Move immap_qe.h into common directory for both arm and powerpc. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | net/fm: call fm_port_to_index() with proper checksRotariu Marian-Cristian2014-07-22-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | Some of the fm_port_to_index() callers did not check for -1 return value and used -1 as an array index. Signed-off-by: Marian Rotariu <marian.rotariu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | dm: Give the demo uclass a nameSimon Glass2014-07-23-0/+1
| | | | | | | | | | | | | | | | | | Uclasses should be named, so add a name for the demo uclass. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | dm: Add dm_scan_other() to locate board-specific devicesSimon Glass2014-07-23-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Some boards will have devices which are not in the device tree and do not have platform data. They may be programnatically created, for example. Add a hook which boards can use to bind those devices early in boot. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | dm: Improve errors and warnings in lists_bind_fdt()Simon Glass2014-07-23-3/+13
| | | | | | | | | | | | | | | | | | | | | Add a debug message for when a device tree node has no driver. Also reword the warning when a device fails to bind, which was misleading. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | dm: Add child_pre_probe() and child_post_remove() methodsSimon Glass2014-07-23-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some devices (particularly bus devices) must track their children, knowing when a new child is added so that it can be set up for communication on the bus. Add a child_pre_probe() method to provide this feature, and a corresponding child_post_remove() method. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | dm: Introduce per-child data for devicesSimon Glass2014-07-23-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some device types can have child devices and want to store information about them. For example a USB flash stick attached to a USB host controller would likely use this space. The controller can hold information about the USB state of each of its children. The data is stored attached to the child device in the 'parent_priv' member. It can be auto-allocated by dm when the child is probed. To do this, add a per_child_auto_alloc_size value to the parent driver. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | dm: Add functions to access a device's childrenSimon Glass2014-07-23-0/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Devices can have childen that can be addressed by a simple index, the sequence number or a device tree offset. Add functions to access a child in each of these ways. The index is typically used as a fallback when the sequence number is not available. For example we may use a serial UART with sequence number 0 as the console, but if no UART has sequence number 0, then we can fall back to just using the first UART (index 0). The device tree offset function is useful for buses, where they want to locate one of their children. The device tree can be scanned to find the offset of each child, and that offset can then find the device. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | dm: Provide a function to scan child FDT nodesSimon Glass2014-07-23-15/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present only root nodes in the device tree are scanned for devices. But some devices can have children. For example a SPI bus may have several children for each of its chip selects. Add a function which scans subnodes and binds devices for each one. This can be used for the root node scan also, so change it. A device can call this function in its bind() or probe() methods to bind its children. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | dm: Avoid accessing uclasses before they are readySimon Glass2014-07-23-0/+2
| | | | | | | | | | | | | | | | | | Don't allow access to uclasses before they have been initialised. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-12-20 14:29:21 +0000