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* kbuild: force to define __UBOOT__ in all the C sourcesMasahiro Yamada2014-09-16-28/+0
| | | | | | | | | | | | | | | | | | | | | | | U-Boot has imported various source files from other projects, mostly Linux. Something like #ifdef __UBOOT__ [ modification for U-Boot ] #else [ original code ] #endif is an often used strategy for clarification of adjusted parts, that is, easier re-sync in future. Instead of defining __UBOOT__ in each source file, passing it from the top Makefile would be easier. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
* rtl8169: Defer network packet processingThierry Reding2014-09-16-1/+2
| | | | | | | | | | | | | | | | | | When network protocol errors occur (such as a file not being found on a TFTP server), the processing done by the NetReceive() function will end up calling the driver's .halt() implementation. However, after that the device no longer has access to the memory buffers and will cause errors such as this in the rtl_recv() function when trying to hand descriptors back to the device: pci_hose_bus_to_phys: invalid physical address This can be fixed by deferring processing of network packets until the descriptors have been handed back. That way rtl_halt() tearing down network buffers is not going to prevent access to the buffers. Reported-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* openrisc: Fix a few type cast related warningsVasili Galka2014-09-15-4/+4
| | | | | | | | | | | Use size_t type for positive offsets instead of the loff_t type. The later is defined as long long, which is larger than the pointer type on OpenRISC architecture and therefore the following warning was generated: "warning: cast to pointer from integer of different size" Signed-off-by: Vasili Galka <vvv444@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-dmTom Rini2014-09-13-117/+838
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| * dm: tegra: Enable driver model for serialSimon Glass2014-09-10-0/+39
| | | | | | | | | | | | | | | | | | Use driver model for serial ports. Since Tegra now uses driver model for serial, adjust the definition of V_NS16550_CLK so that it is clear that this is only used for SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: serial: Add driver model support for ns16550Simon Glass2014-09-10-3/+155
| | | | | | | | | | | | | | | | | | | | Add driver model support so that ns16550 can support operation both with and without driver model. The driver needs a clock frequency so cannot stand alone unfortunately. The clock frequency must be provided by a separate driver. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: serial: Collect common baud rate code in ns16550Simon Glass2014-09-10-20/+13
| | | | | | | | | | | | | | The same sequence is used in several places, so move it into a function. Note that UART_LCR_BKSE is an alias for UART_LCR_DLAB. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: serial: Move baud rate calculation to ns16550.cSimon Glass2014-09-10-11/+21
| | | | | | | | | | | | | | Move the function that calculates the baud rate divisor into ns16550.c so it can be used by that file. Signed-off-by: Simon Glass <sjg@chromium.org>
| * sandbox: serial: Support a coloured consoleSimon Glass2014-09-10-0/+83
| | | | | | | | | | | | | | | | | | | | The current sandbox serial driver is a pretty trivial example and does not have the featues that might be needed for other board serial drivers. To help provide a better example, add a text colour property to the device tree for sandbox. This uses platform data, a device tree node, driver private data and a remove() method. Signed-off-by: Simon Glass <sjg@chromium.org>
| * sandbox: Convert serial driver to use driver modelSimon Glass2014-09-10-31/+36
| | | | | | | | | | | | | | Adjust the sandbox serial driver to use the new driver model uclass. The driver works much as before, but within the new framework. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: Add a uclass for serial devicesSimon Glass2014-09-10-0/+217
| | | | | | | | | | | | | | | | Serial devices support simple byte input/output and a few operations to find out whether data is available. Add a basic uclass for serial devices to be used by drivers that are converted to driver model. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: Adjust lists_bind_fdt() to return the bound deviceSimon Glass2014-09-10-4/+8
| | | | | | | | | | | | | | Allow the caller to find out the device that was bound in response to this call. Signed-off-by: Simon Glass <sjg@chromium.org>
| * serial: Set up the 'priv' pointer when creating a serial deviceSimon Glass2014-09-10-0/+1
| | | | | | | | | | | | | | | | The stdio_dev structure has a private pointer for its creator, but it is not set up by the serial system. Set it to point to the serial device so that it can be found by code called by stdio. Signed-off-by: Simon Glass <sjg@chromium.org>
| * tegra: Convert tegra GPIO driver to use driver modelSimon Glass2014-09-10-55/+272
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is an implementation of GPIOs for Tegra that uses driver model. It has been tested on trimslice and also using the new iotrace feature. The implementation uses a top-level GPIO device (which has no actual GPIOS). Under this all the banks are created as separate GPIO devices. The GPIOs are named as per the Tegra datasheet/header files: A0..A7, B0..B7, ..., Z0..Z7, AA0..AA7, etc. Since driver model is not yet available before relocation, or in SPL, a special function is provided for seaboard's SPL code. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-09-12-57/+308
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| * Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2014-09-09-12/+270
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| | * video: Add driver for Parade PS8625 dP to LVDS bridgeVadim Bendebury2014-09-05-0/+221
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The initialization table comes from the "Illustration of I2C command for initialing PS8625" document supplied by Parade. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * video: exynos_fimd: Add framework to disable FIMD sysmmuAjay Kumar2014-09-05-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Exynos5420 and newer versions, the FIMD sysmmus are in "on state" by default. We have to disable them in order to make FIMD DMA work. This patch adds the required framework to exynos_fimd driver, and disables FIMD sysmmu on Exynos5420. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * exynos_fb: Remove usage of static definesAjay Kumar2014-09-05-12/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, we used to statically assign values for vl_col, vl_row and vl_bpix using #defines like LCD_XRES, LCD_YRES and LCD_COLOR16. Introducing the function exynos_lcd_early_init() would take care of this assignment on the fly by parsing FIMD DT properties, thereby allowing us to remove LCD_XRES and LCD_YRES from the main config file. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | mtd: nand: omap_gpmc: Fix 'bit-flip' errorsRostislav Lisovy2014-09-04-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OMAP GPMC driver used with some NAND Flash devices (e.g. Spansion S34ML08G1) causes that U-boot shows hundreds of 'nand: bit-flip corrected' error messages. Possible cause was discussed in the mailinglist thread: http://lists.denx.de/pipermail/u-boot/2014-April/177508.html Quote (Author: Pekon Gupta <pekon@ti.com>): "The issue is mainly due to a NAND protocol violation in the omap driver since the Random Data Output command (05h-E0h) expects to see only the column address that should be addressed within the already loaded read page into the read buffer. Only 2 address cycles with ALE active should be provided between the 05h and E0h commands. The Page read command expects the full address footprint (2bytes for column address + 3bytes for row address), but once the page is loaded into the read buffer, Random Data Output should be used with only 2bytes for column address." This patch combines the solution proposed in the mailinglist and the patch provided by the Spansion company (GPLv2 code, source: http://www.spansion.com/Support/Software/u-boot-psp-04.04.00.01-NAND.zip) Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
| * | mtd: nand: omap_gpmc: Enable multiple NAND flash devicesRostislav Lisovy2014-09-04-22/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the CS of a device connected to the GPMC was stored in the global variable, it was not possible to use multiple devices. In this patch the CS is stored per device in its 'struct omap_nand_info'. This makes it possible to use up to 'GPMC_MAX_CS' NAND Flash devices connected to U-boot. Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
| * | mtd: nand: davinci_nand: correct keystone RBL layout definitionKhoronzhuk, Ivan2014-09-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | In case when 4K page keystone RBL layout is used the compilation error is appeared. That's because the #ifdef has to be placed under struct name. This patch correct it. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | keystone2: use readl/writel functions instead of redefinitionKhoronzhuk, Ivan2014-09-04-20/+15
| |/ | | | | | | | | | | | | | | There is no reason to redefine pure readl/writel functions. So remove this redundancy. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Acked-by: Vitaly Andrianov <vitalya@ti.com>
* | video: dcu: Add DCU driver supportWang Huan2014-09-08-0/+366
| | | | | | | | | | | | | | | | | | This patch is to add DCU driver support. DCU also named 2D-ACE(Two Dimensional Animation and Compositing Engine) is a system master that fetches graphics stored in internal or external memory and displays them on a TFT LCD panel. Signed-off-by: Alison Wang <alison.wang@freescale.com>
* | serial: lpuart: add 32-bit registers lpuart supportJingchang Lu2014-09-08-0/+118
| | | | | | | | | | | | | | | | | | On vybrid, lpuart's registers are 8-bit. On LS102xA, lpuart's registers are 32-bit. This patch adds the support for 32-bit registers on LS102xA. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
* | driver/ddr/fsl: Add support of overriding chip select write levelingYork Sun2014-09-08-0/+5
| | | | | | | | | | | | | | | | | | | | JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This is not an issue unless some DQ pins are not connected. If a platform uses regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on those floating pins for the second rank. The workaround is to use a known good chip select for this purpose. Signed-off-by: York Sun <yorksun@freescale.com>
* | driver/ddr/freescale: Fix DDR3 driver for ARMYork Sun2014-09-08-1/+1
| | | | | | | | | | | | | | Reading DDR register should use ddr_in32() for proper endianess. This patch fixes incorrect waiting time for ARM platforms. Signed-off-by: York Sun <yorksun@freescale.com>
* | driver/ddr/freescale: Add support of accumulate ECCYork Sun2014-09-08-0/+5
| | | | | | | | | | | | | | | | | | If less than 8 ECC pins are used for DDR data bus width smaller than 64 bits, the 8-bit ECC code will be transmitted/received across several beats, and it will be used to check 64-bits of data once 8-bits of ECC are accumulated. Signed-off-by: York Sun <yorksun@freescale.com>
* | ls102xa: esdhc: Add esdhc support for LS102xAWang Huan2014-09-08-2/+2
| | | | | | | | | | | | | | | | | | | | | | For LS1, esdhc is big-endian IP. Accessing the registers should be in big-endian mode. So we use esdhc_read32() to read Host controller capabilities register for LS1. For LS1, when using CMD12, cmdtype need to be set to ABORT, otherwise, next read command will hang. Signed-off-by: Alison Wang <alison.wang@freescale.com>
* | ls102xa: etsec: Add etsec support for LS102xAAlison Wang2014-09-08-0/+7
| | | | | | | | | | | | | | | | | | This patch is to add etsec support for LS102xA. First, Little-endian descriptor mode should be enabled. So RxBDs and TxBDs are interpreted with little-endian byte ordering. Second, TSEC_SIZE and TSEC_MDIO_OFFSET are different from PowerPC, redefine them for LS1021xA. Signed-off-by: Alison Wang <alison.wang@freescale.com>
* | net: mdio: Use mb() to be compatible for both ARM and PowerPCAlison Wang2014-09-08-3/+6
| | | | | | | | | | | | | | Use mb() instead of sync assembly instruction to be compatible for both ARM and PowerPC. Signed-off-by: Alison Wang <alison.wang@freescale.com>
* | net: Merge asm/fsl_enet.h into fsl_mdio.hClaudiu Manoil2014-09-08-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fsl_enet.h defines the mapping of the usual MII management registers, which are included in the MDIO register block common to Freescale ethernet controllers. So it shouldn't depend on the CPU architecture but it should be actually part of the arch independent fsl_mdio.h. To remove the arch dependency, merge the content of asm/fsl_enet.h into fsl_mdio.h. Some files (like fm_eth.h) were simply including fsl_enet.h only for phy.h. These were updated to include phy.h instead. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
* | ls102xa: i2c: Add i2c support for LS102xAWang Huan2014-09-08-2/+2
| | | | | | | | | | | | | | | | | | | | | | The existing i.MX's I2C driver mxc_i2c.c is compatible with the controller of LS102xA. As I2C's registers are 8-bit on LS102xA, I2C_QUIRK_REG is enabled to use 8-bit driver. This patch is to add I2C 1,2,3 support for LS102xA. Signed-off-by: Alison Wang <alison.wang@freescale.com>
* | arm: ls102xa: Add Freescale LS102xA SoC supportWang Huan2014-09-08-1/+1
|/ | | | | | | | | | | | | | | | | | The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale. Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors with Layerscape architecture and with a comprehensive enablement model focused on ease of programmability. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* USB: gadget: s3c: get rid of debug compile warningBo Shen2014-09-02-8/+8
| | | | | | | | | | When enable debug option to compile, it will give the following warning, this patch is used to get rid of it. --->8--- warning: 'flags' is used uninitialized in this function [-Wuninitialized] ---8<--- Signed-off-by: Bo Shen <voice.shen@atmel.com>
* USB: gadget: atmel: get rid of debug compile warningBo Shen2014-09-02-6/+6
| | | | | | | | | | When enable debug option to compile, it will give the following warning, this patch is used to get rid of it. --->8--- warning: 'flags' is used uninitialized in this function [-Wuninitialized] ---8<--- Signed-off-by: Bo Shen <voice.shen@atmel.com>
* usb: ci_udc: implement dfu_usb_get_resetStephen Warren2014-09-02-0/+7
| | | | | | | | This allows the USB code to determine whether a USB bus reset was issued, which in turn allows the code to differentiate between a detach (return to shell prompt) and a board reset/reboot request. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* udc: dfu: s3c_udc: Provide function to check if USB reset was assertedLukasz Majewski2014-09-02-0/+5
| | | | | | | | | | | New dfu_usb_get_reset() method is necessary to distinct two different use cases of dfu-util program. This method checks if the USB bus reset has been really performed after DFU DETACH. Without this function the previous DFU behavior is preserved. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
* dfu: Provide means to find difference between dfu-util -e and -RLukasz Majewski2014-09-02-6/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit provides distinction between DFU device detach and reset. The -R behavior is preserved with proper handling of the dfu-util's -e switch, which detach the DFU device. By running dfu-util -e; one can force device to finish the execution of dfu command on target and execute some other scripted commands. Moreover, some naming has been changed - the dfu_reset() method now is known as dfu_detach(). New name better reflects the purpose of the code. It was also necessary to increase the number of usb_gadget_handle_interrupts() calls since we also must wait for detection of the USB reset event. Example usage: 1. -e (detach) switch dfu-util -a0 -D file1.bin;dfu-util -a3 -D uImage;dfu-util -e access to u-boot prompt. 2. -R (reset) switch dfu-util -a0 -D file1.bin;dfu-util -R -a3 -D uImage target board reset Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com>
* Merge branch 'master' of git://git.denx.de/u-boot-niosTom Rini2014-08-31-3/+143
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| * serial: move nios2-yanu.h into opencores_yanu driverThomas Chou2014-08-30-1/+86
| | | | | | | | | | | | | | | | | | The nios2-yanu.h contains hardware registers and bits of opencores yanu. As there is no other user of this header , it should be moved into the driver. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> CC: Renato Andreola <renato.andreola@imagos.it>
| * nios2: divide nios2-io.h into each specific drivers and remove itThomas Chou2014-08-30-2/+57
| | | | | | | | | | | | | | | | | | | | The nios2-io.h defines hardware registers and bits of several FPGA IP cores. It could be divided in to the specific drivers, including altera timer, altera sysid, altera uart and altera jtag uart. The altera pio and altera spi drivers use their own hardware definitions. The removal of nios2-io.h will help modularity and maintenance. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
* | arm/kirkwood/nand: allow forced disabling for subpage writesHolger Brunck2014-08-30-0/+3
| | | | | | | | | | | | | | | | | | | | Make it configurable to disable subpage writes like the DaVinci NAND driver already does. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> cc: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> cc: Scott Wood <scottwood@freescale.com>
* | arm: bcm281xx: net: Add Ethernet DriverJiandong Zheng2014-08-30-0/+1535
| | | | | | | | | | | | | | | | | | | | | | The Broadcom StarFighter2 Ethernet driver is used in multiple Broadcom SoC(s) and: - supports multiple MAC blocks, - provides support for the Broadcom GMAC. This driver requires MII and PHYLIB. Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com>
* | socfpga: cleanup socfpga_dw_mmcPavel Machek2014-08-30-4/+4
| | | | | | | | | | | | | | Cleanups as suggested by wd on mailing list. Signed-off-by: Pavel Machek <pavel@denx.de> Acked-by: Chin Liang See <clsee@altera.com>
* | socfpga: fix clock manager register definitionPavel Machek2014-08-29-2/+2
|/ | | | | | | | | Structure defining clock manager hardware was wrong, leading to wrong registers being accessed and hang in MMC init. This fixes structure to match hardware. Signed-off-by: Pavel Machek <pavel@denx.de>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-08-29-5/+201
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| * pci: mx6: fix occasional link failuresTim Harvey2014-08-20-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable for SS function) must remain deasserted until the reference clock is running at the appropriate frequency. Without this patch we find a high link failure rate (>5%) on certain IMX6 boards at various temperatures. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
| * Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic2014-08-11-45/+1056
| |\ | | | | | | | | | | | | | | | | | | Conflicts: boards.cfg Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | pmic: pmic_pfuze100: Use a shorter name for PMIC nameFabio Estevam2014-08-08-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is redundant to use 'PFUZE100_PMIC' as the PMIC name because we already know it is a PMIC. Call it simply 'PFUZE100' instead. Cc: Tim Harvey <tharvey@gateworks.com> Cc: Markus Niebel <Markus.Niebel@tq-group.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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