summaryrefslogtreecommitdiff
path: root/drivers
Commit message (Collapse)AuthorAgeLines
* Merge remote-tracking branch 'u-boot-imx/master'Albert ARIBAUD2014-10-08-2/+743
|\ | | | | | | | | | | | | The single file conflict below is actually trivial. Conflicts: board/boundary/nitrogen6x/nitrogen6x.c
| * usb: ehci-mx6: Rename the USB register base addressYe.Li2014-09-29-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | The mx6sl/mx6sx has 2 OTG and 1 host. So they have name "USBO2H_USB_BASE_ADDR" in imx-regs.h. The driver hard codes the USB base address name to "USBOH3", which causes the driver failed to build for mx6sl/mx6sx. This patch uniform the address name to "USB_BASE_ADDR" for all mx6 series. Signed-off-by: Ye.Li <B37916@freescale.com>
| * usb: ehci: mxs: Add board-specific callbacksMarek Vasut2014-09-29-0/+16
| | | | | | | | | | | | | | | | | | Add board-specific callbacks for enabling/disabling port power into the MXS EHCI controller driver. This is in-line with the names of callbacks on other systems. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic2014-09-22-181/+1390
| |\
| * | mtd: nand: add Freescale vf610_nfc driverStefan Agner2014-09-16-0/+725
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds initial support for Freescale NFC (NAND Flash Controller) found in ARM Vybrid SoC's, Power Architecture MPC5125 and others. The driver is called vf610_nfc since this is the first supported and tested hardware platform supported by the driver. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Bill Pringlemeir <bpringlemeir@nbsps.com>
* | | serial: add UniPhier serial driverMasahiro Yamada2014-10-05-0/+207
| | | | | | | | | | | | | | | | | | The driver for on-chip UART used on Panasonic UniPhier platform. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | mtd: denali: add Denali NAND driver for SPLMasahiro Yamada2014-10-05-0/+242
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPL-mode driver for Denali(Cadence) NAND Flash Memory Controller IP. This driver requires two CONFIG macros: - CONFIG_SPL_NAND_DENALI Define to enable this driver. - CONFIG_SYS_NAND_BAD_BLOCK_POS Specify bad block mark position in the oob space. Typically 0. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Chin Liang See <clsee@altera.com> Cc: Scott Wood <scottwood@freescale.com>
* | | mtd: denali: add Denali controller configs to KconfigMasahiro Yamada2014-10-05-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 3eb3e72a3f66 (nand/denali: Adding Denali NAND driver support) introduced some new options, and some of them were documented by commit f9860cf081ef (nand/denali: Document CONFIG symbols). This commit allows users to enable/disable them via Kconfig with more detailed help docs. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Chin Liang See <clsee@altera.com> Cc: Scott Wood <scottwood@freescale.com>
* | | Merge branch 'for-tom' of git://git.denx.de/u-boot-dmTom Rini2014-09-26-76/+38
|\ \ \
| * | | sandbox: Convert SPI flash emulation to use sf_paramsSimon Glass2014-09-26-76/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present sandbox has its own table of supported SPI flash chips. Now that the SPI flash system is fully consolidated and has its own list, sandbox should use that. This enables us to expand the number of chips that sandbox supports. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2014-09-26-131/+249
|\ \ \ \
| * | | | driver/ddr/fsl: Fix DDR4 driverYork Sun2014-09-25-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When accumulated ECC is enabled, the DQ_MAP for ECC[4:7] needs to be set to 0, i.e. 0->0, 1->1, etc., required by controller logic, even these pins are not actually connected. Also fix a bug when reading from DDR register to use proper accessor for correct endianess. Signed-off-by: York Sun <yorksun@freescale.com>
| * | | | driver/ddr/fsl: Fix tXP and tCKEYork Sun2014-09-25-12/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver was written using old DDR3 spec which only covers low speeds. The value would be suboptimal for higher speeds. Fix both timing according to latest DDR3 spec, remove tCKE as an config option. Signed-off-by: York Sun <yorksun@freescale.com>
| * | | | driver/ddr: Restruct driver to allow standalone memory spaceYork Sun2014-09-25-100/+205
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-boot has been initializing DDR for the main memory. The presumption is the memory stays as a big continuous block, either linear or interleaved. This change is to support putting some DDR controllers to separated space without counting into main memory. The standalone memory controller could use different number of DIMM slots. Signed-off-by: York Sun <yorksun@freescale.com>
| * | | | driver/mtd: Use generic timer API for FSL IFC, eLBCPrabhakar Kushwaha2014-09-25-15/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's flash control driver is using architecture specific timer API i.e. usec2ticks Replace usec2ticks with get_timer() (generic timer API) Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-09-26-2/+0
|\ \ \ \ \ | |_|/ / / |/| | | |
| * | | | board/t1040qds: Add sgmii ports support in 0xA7 protocolPriyanka Jain2014-09-24-2/+0
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1042QDS (T1042 is T1040 Personality without L2 switch) supports following sgmii interfaces with serdes protocol 0xA7 -SGMII-MAC3 on Lane B - slot 7 -SGMII-MAC5 on Lane H - slot 7 -SGMII2.5G-MAC1 on Lane C - slot 6 -SGMII2.5G-MAC2 on Lane D - slot 5 Add support of above sgmii interfaces Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
* | | | nand/denali: Adding Denali NAND driver supportChin Liang See2014-09-25-0/+1673
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To add the Denali NAND driver support into U-Boot. This driver is leveraged from Linux with commit ID fdbad98dff8007f2b8bee6698b5d25ebba0471c9. For Denali controller 64 variance, you need to declare macro CONFIG_SYS_NAND_DENALI_64BIT. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Tested-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | | mtd: nand: Fix length bug in ioread16_rep() and iowrite16_rep()Stefan Roese2014-09-25-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ioread16_rep() and iowrite16_rep() implementations are U-Boot specific and have been introduced with the Linux MTD v3.14 sync. While introducing these functions, the length for the loop has been miscalculated. The ">> 1" is already present in the caller. So lets remove it in the function. Tested on omap3_ha. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Scott Wood <scottwood@freescale.com> Acked-by: Heiko Schocher <hs@denx.de>
* | | | mtd: nand: am335x: Fix 'bit-flip' errors in SPLRostislav Lisovy2014-09-25-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OMAP GPMC driver used with some NAND Flash devices (e.g. Spansion S34ML08G1) causes that U-boot shows hundreds of 'nand: bit-flip corrected' error messages. Possible cause was discussed in the mailinglist thread: http://lists.denx.de/pipermail/u-boot/2014-April/177508.html The issue was partially fixed with the cc81a5291910d7a.git however this has to be done to fix the SPL. The original author of the code is Belisko Marek <marek.belisko@gmail.com> Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
* | | | kbuild: refactor some makefilesMasahiro Yamada2014-09-24-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [1] Move driver/core/, driver/input/ and drivers/input/ entries from the top Makefile to drivers/Makefile [2] Remove the conditional by CONFIG_DM in drivers/core/Makefile because the whole drivers/core directory is already selected by CONFIG_DM in the upper level [3] Likewise for CONFIG_DM_DEMO in drivers/demo/Makefile [4] Simplify common/Makefile - both CONFIG_DDR_SPD and CONFIG_SPD_EEPROM are boolean macros so they can directly select objects Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Marek Vasut <marex@denx.de>
* | | | cosmetic: replace MIN, MAX with min, maxMasahiro Yamada2014-09-24-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The macro MIN, MAX is defined as the aliase of min, max, respectively. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | | kconfig: add blank Kconfig filesMasahiro Yamada2014-09-24-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This would be useful to start moving various config options. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | | | e1000: fix no nvm buildMarcel Ziswiler2014-09-24-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following build error in case CONFIG_E1000_NO_NVM is enabled: CC drivers/net/e1000.o drivers/net/e1000.c: In function ‘e1000_initialize’: drivers/net/e1000.c:5365:5: error: ‘struct e1000_hw’ has no member named ‘eeprom_semaphore_present’ make[1]: *** [drivers/net/e1000.o] Error 1 make: *** [drivers/net] Error 2 Acked-by: Marek Vasut <marex@denx.de>
* | | | usb/gadget: fastboot: minor cleanupSteve Rae2014-09-24-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - update static function - additional debugging statements - update "fastboot command" information - add missing include file - update spelling Signed-off-by: Steve Rae <srae@broadcom.com>
* | | | usb/gadget: fastboot: add support for flash commandSteve Rae2014-09-24-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - implement 'fastboot flash' for eMMC devices Signed-off-by: Steve Rae <srae@broadcom.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Reviewed-by: Marek Vasut <marex@denx.de>
* | | | spi: kirkwood_spi.c: cosmetic: Fix minor coding style issuesStefan Roese2014-09-24-8/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Cc: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Tested-by: Luka Perkov <luka@openwrt.org> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* | | | spi: kirkwood_spi.c: Make global variable staticStefan Roese2014-09-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Tested-by: Luka Perkov <luka@openwrt.org> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* | | | spi: kirkwood_spi.c: Some fixes and cleanupStefan Roese2014-09-24-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces the clrsetbits_le32() accessor functions in the kirkwood SPI driver. Note that it also includes a fix: - writel(~KWSPI_CSN_ACT | KWSPI_SMEMRDY, &spireg->ctrl); + writel(KWSPI_SMEMRDY, &spireg->ctrl); Here the bit KWSPI_CSN_ACT (0x1) should have been cleared. Instead 0xfffffffe is written into this control register. This is the main reason to use the clrsetbits() functions now. As they make clearing bits much less error prone. Additionally KWSPI_IRQUNMASK is not used in spi_cs_activate() and spi_cs_deactivate() any more. Its the wrong macro but has the same value as the correct one (KWSPI_CSN_ACT). This is in preparation for use of this driver on the Marvell Armada XP platform as well. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Tested-by: Luka Perkov <luka@openwrt.org> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* | | | sf: Add M25PX64 SPI NOR flash IDStefan Roese2014-09-24-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add ID for this Numonix / STMicro chip. Tested on Marvell DB-78460-BP board. Signed-off-by: Stefan Roese <sr@denx.de> Tested-by: Luka Perkov <luka@openwrt.org> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* | | | spl: replace CONFIG_SPL_SPI_* with CONFIG_SF_DEFAULT_*Nikita Kiryanov2014-09-24-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, CONFIG_SPL_SPI_* #defines are used for controlling SPI boot in SPL. These #defines do not allow the user to select SPI mode for the SPI flash (there's no CONFIG_SPL_SPI_MODE, so the SPI mode is hardcoded in spi_spl_load.c), and duplicate information already provided by CONFIG_SF_DEFAULT_* #defines. Kill CONFIG_SPL_SPI_*, and use CONFIG_SF_DEFAULT_* instead. Cc: Tom Rini <trini@ti.com> Cc: Marek Vasut <marex@denx.de> Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Cc: Vitaly Andrianov <vitalya@ti.com> Cc: Lars Poeschel <poeschel@lemonage.de> Cc: Bo Shen <voice.shen@atmel.com> Cc: Hannes Petermaier <hannes.petermaier@br-automation.com> Cc: Michal Simek <monstr@monstr.eu> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* | | | spi: mxc: fix sf probe when using mxc_spiNikita Kiryanov2014-09-24-23/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MXC SPI driver has a feature whereas a GPIO line can be used to force CS high across multiple transactions. This is set up by embedding the GPIO information in the CS value: cs = (cs | gpio << 8) This merge of cs and gpio data into one value breaks the sf probe command: if the use of gpio is required, invoking "sf probe <cs>" will not work, because the CS argument doesn't have the GPIO information in it. Instead, the user must use "sf probe <cs | gpio << 8>". For example, if bank 2 gpio 30 is used to force cs high on cs 0, bus 0, then instead of typing "sf probe 0" the user now must type "sf probe 15872". This is inconsistent with the description of the sf probe command, and forces the user to be aware of implementaiton details. Fix this by introducing a new board function: board_spi_cs_gpio(), which will accept a naked CS value, and provide the driver with the relevant GPIO, if one is necessary. Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Eric Benard <eric@eukrea.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* | | | mtd: spi: add support for M25PE16 and M25PX16Nikita Kiryanov2014-09-24-0/+2
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | Add support for M25PE16 and M25PX16 Cc: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* | | dm: avoid dev->req_seq overflowRobert Baldyga2014-09-23-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since dev->req_seq value is initialized from "reg" property of fdt node, there is posibility, that address value contained in fdt is greater than INT_MAX, and then value in dev->req_seq is negative which led to probe() fail. This patch fix this problem by ensuring that req_seq is positive, unless it's one of errno codes. Signed-off-by: Robert Baldyga <r.baldyga@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | dm: serial: Don't require device tree to configure a consoleSimon Glass2014-09-23-1/+2
| | | | | | | | | | | | | | | | | | Allow serial_find_console_or_panic() to work without a device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | dm: core: Allow device_bind() to used without CONFIG_OF_CONTROLSimon Glass2014-09-23-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | The sequence number support in driver model requires device tree control. It should be skipped if CONFIG_OF_CONTROL is not defined, and should not require functions from fdtdec. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | sf: Add an empty entry to the parameter listSimon Glass2014-09-23-0/+1
| |/ |/| | | | | | | | | | | | | The list is supposed to be terminated with a NULL name, but is not. If a board probes a chip which does not appear in the table, U-Boot will crash (at least on sandbox). Signed-off-by: Simon Glass <sjg@chromium.org>
* | mtd: atmel_nand: Disable subpage NAND write when using Atmel PMECCBoris BREZILLON2014-09-19-0/+1
| | | | | | | | | | | | | | | | | | | | | | Disable subpage write when using PMECC to prevent buggy partial page write. This fix has been taken from linux sources (see commit 90445ff6241e2a13445310803e2efa606c61f276) Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | USB: ehci-atmel: use pcr to enable or disable clockBo Shen2014-09-19-0/+8
| | | | | | | | | | | | | | | | If the SoC has pcr, we use pcr (peripheral control register) to enable or disable clock. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | USB: ohci-at91: use pcr to enable or disable clockBo Shen2014-09-19-4/+4
| | | | | | | | | | | | | | | | If the SoC has pcr, we use pcr (peripheral control register) to enable or disable clock. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | mtd: atmel-nand: use pmecc_readl(b)/pmecc_writel to access the pmecc registerWu, Josh2014-09-19-10/+14
| | | | | | | | | | | | | | | | | | | | We defined the macro pmecc_readl(b)/pmecc_writel for pmecc register access. But in the driver we also use the readl(b)/writel. To keep consistent, this patch make all use pmecc_readl(b)/pmecc_writel. Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-09-17-15/+107
|\ \ | |/
| * pcie_imx: Add mx6solox supportFabio Estevam2014-09-09-4/+36
| | | | | | | | | | | | | | Let PCI on mx6solox also be supported. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
| * arm: vf610: lpuart: disable FIFO on initializatonStefan Agner2014-09-09-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | UART does not use the UART FIFO, but we should also not rely that the UART FIFO is diabled by default. For instance, when loading U-Boot using the boot ROMs serial downloader protocol over UART, FIFO is enabled at U-Boot start time. This patch disables the RX and TX FIFO, sets back their thresholds and flushes them. Signed-off-by: Stefan Agner <stefan@agner.ch>
| * arm: vf610: lpuart: fix status register handlingStefan Agner2014-09-09-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The status register 1 (S1) is not writeable, hence we should not write it. In order to clear the RDRF flag we only need to read the data register. Also, when stressing U-Boot a lot with serial input, an overflow can occur which asserts the S1_OR flag (while not asserting the S1_RDRF flag). To clear this flag we again just need to read the data register, hence add this flag to the abort conditions for the while loop. Insert a compiler barrier to make sure reading the data register gets executed after reading the status register. Signed-off-by: Stefan Agner <stefan@agner.ch>
| * pci: add support for board_pci_fixup_dev functionTim Harvey2014-09-09-0/+4
| | | | | | | | | | | | | | Some board-level drivers may wish to have per-device fixup functions for PCI devices. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * sata: dwc_ahsata: implement sata_port_statusNikita Kiryanov2014-09-09-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | Define the new common function sata_port_status() which can be used to query the sata driver for the state of ports, and implement it for dwc_ahsata. Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| * net: fec_mxc: Poll FEC_TBD_READY after polling TDARFabio Estevam2014-09-09-3/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets always cleared prior then the READY bit is cleared in the last BD, which causes FEC packets reception to always fail. As explained by Ye Li: "The TDAR bit is cleared when the descriptors are all out from TX ring, but on mx6solox we noticed that the READY bit is still not cleared right after TDAR. These are two distinct signals, and in IC simulation, we found that TDAR always gets cleared prior than the READY bit of last BD becomes cleared. In mx6solox, we use a later version of FEC IP. It looks like that this intrinsic behaviour of TDAR bit has changed in this newer FEC version." Fix this by polling the READY bit of BD after the TDAR polling, which covers the mx6solox case and does not harm the other SoCs. No performance drop has been noticed with this patch applied when testing TFTP transfers on several boards of different i.mx SoCs. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
| * net: fec_mxc: Adjust RX DMA alignment for mx6soloxFabio Estevam2014-09-09-2/+10
| | | | | | | | | | | | | | | | | | | | | | mx6solox has a requirement for 64 bytes alignment for RX DMA transfer. Other SoCs work with the standard 32 bytes alignment. Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers, which addresses the needs from mx6solox and also works for the other SoCs. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
* | net: usb: Add SMSC copyright to smsc95xx driverSimon Glass2014-09-16-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver was upstreamed without an SMSC copyright, even thought it seems that SMSC was the original author. See the kernel version for a code comparison: http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=2f7ca802bdae2ca41022618391c70c2876d92190 It's not clear who actually moved this code, or whether the kernel was the original source, or somewhere else, but it probably should still have the SMSC copyright. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-12-19 12:01:57 +0000