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* mx31/mx35/mx51/mx53/mx6: add watchdogTroy Kisky2013-01-13-0/+69
| | | | | | | Use a common watchdog driver for all these cpus. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
* Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-01-08-1/+1
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| * fsl_esdhc: add MMC_MODE_HC host_capsShawn Guo2013-01-05-1/+1
| | | | | | | | | | | | | | | | All esdhc variants we know should support high capacity MMC cards, so let's add MMC_MODE_HC host_caps unconditionally to support those MMC cards (capacity > 2 GB). Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2013-01-08-55/+720
|\ \ | | | | | | | | | | | | This required manual merging drivers/mtd/nand/Makefile and adding am335x_evm support for CONFIG_SPL_NAND_DRIVERS
| * | power: twl6035: complain on LDO9 errorVincent Stehlé2012-12-10-4/+13
| | | | | | | | | | | | | | | | | | | | | We handle i2c_write return code and complain in case of error. We propagate the error, too, to allow better handling at the upper level in the future. Signed-off-by: Vincent Stehlé <v-stehle@ti.com>
| * | omap24xx_i2c: Handle wait_for_bb errorVincent Stehlé2012-12-10-6/+14
| | | | | | | | | | | | | | | | | | | | | | | | We add a return code to wait_for_bb() to be able to report errors to the callers properly. We in turn handle this new error code in i2c_read, i2c_write and i2c_probe. Signed-off-by: Vincent Stehlé <v-stehle@ti.com>
| * | gpio: add gpio_is_valid() to omap_gpio APINikita Kiryanov2012-12-10-7/+3
| | | | | | | | | | | | | | | | | | | | | Add gpio_is_valid() to omap_gpio API Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
| * | am335x: cpsw: make phy address configurableYegor Yefremov2012-12-10-1/+4
| | | | | | | | | | | | Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
| * | OMAP3 SPI : Fixed bugs related to SPI transferajoy2012-12-10-32/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added posted writes (read after writes) to effect the change immediately for channel confiuration and channel enable register Disable the channel to purge receieve data in TX_ONLY mode transfer otherwise rx data will get affected by the next immediate RX_ONLY mode transfer Wait for the EOT bit to be set after last byte has been loaded to TX shift register in the the TX_ONLY mode.This ensures TX data has been completely shifted out Disable the channel in RX_ONLY mode before reading the last data from RXX register to prevent the SPI slave to transmit next word Signed-off-by: Ajoy Kumar Das <akdas75@yahoo.in> Cc: Tom Rini <trini@ti.com> Cc: jacopo mondi <j.mondi@voltaelectronics.com>
| * | am33xx_spl_bch: simple SPL nand loader for AM33XXIlya Yanok2012-12-10-0/+239
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AM33XX with BCH8 can't work with nand_spl_simple correctly because custom read_page implementation is required for proper syndrome generation. This simple driver mostly duplicates nand_spl_simple but has nand_read_page changed to suit our needs. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
| * | omap_gpmc: BCH8 support (ELM based)Mansoor Ahamed2012-12-10-1/+402
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for BCH8 error correction code to omap_gpmc driver. We use GPMC to generate codes/syndromes but we need ELM to find error locations from given syndrome. Signed-off-by: Mansoor Ahamed <mansoor.ahamed@ti.com> [ilya: merge it with omap_gpmc driver, some fixes and cleanup] Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
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*---. \ \ Merge samsung, imx, tegra into u-boot-arm/masterAlbert ARIBAUD2012-12-22-787/+15489
|\ \ \ \ \ | |_|_|/ / |/| | | / | | | |/ | | |/| | | | | This commit merges branches from samsung, imx and tegra meant to fix merge issues between u-boot/master and u-boot-arm/master, as well as a few manual merge fixes.
| | | * Merge remote-tracking branch 'u-boot/master' into u-boot-arm-mergedAllen Martin2012-12-19-773/+15476
| | | |\ | |_|/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: README arch/arm/cpu/armv7/exynos/clock.c board/samsung/universal_c210/universal.c drivers/misc/Makefile drivers/power/power_fsl.c include/configs/mx35pdk.h include/configs/mx53loco.h include/configs/seaboard.h
| | | * Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2012-12-17-4/+26
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| | | | * net: sh_eth: add support for SH7752Yoshihiro Shimoda2012-12-15-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SH7752 has two fast ethernet controllers and two gigabit ethernet controllers. It is similar to SH7757. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | | | * phy: Add support for Marvell 88E1118RMichal Simek2012-12-15-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Marvell 88E1118R has different uid then 88E1118. Signed-off-by: Michal Simek <monstr@monstr.eu> CC: Andy Fleming <afleming@freescale.com> CC: Zang Roy-R61911 <tie-fei.zang@freescale.com> CC: Kumar Gala <galak@kernel.crashing.org>
| | | | * e1000e : Correct Rx Threshold granularityRuchika Gupta2012-12-15-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In e1000e driver, Rx descriptor queue is used such that hardware can add only one descriptor at a time. So the WTHRESH granularity in RXDCTL should be set to single descriptor. This would ensure that every time controller fills a Rx descriptor, it is flushed to host memory. Earlier this granularity was in cache line units i.e 2 descriptors. This leads to controller always waiting for 2 descriptors before flushing them out. But since not more than one Rx BD is actually available , the accumulation condition never gets hit. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Vakul Garg <vakul@freescale.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
| | | * | Merge remote-tracking branch 'origin/master'Scott Wood2012-12-14-61/+262
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| | | | * env: Add a baudrate env handlerJoe Hershberger2012-12-13-0/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the hard-coded baudrate handler and use a callback instead Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
| | | | * designware_i2c.h: Define IC_CLK only if not already defined in config fileArmando Visconti2012-12-11-0/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Armando Visconti <armando.visconti@st.com>
| | | | * designware_i2c.h: Fixed the correct values for SCL low/high timeArmando Visconti2012-12-11-3/+3
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Armando Visconti <armando.visconti@st.com>
| | | | * designware_i2c: Fixed the setting of the i2c bus speedArmando Visconti2012-12-11-15/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are three couple (hcnt/lcnt) of registers for each speed (SS/FS/HS). The driver needs to set the proper couple of regs according to what speed we are setting. Signed-off-by: Armando Visconti <armando.visconti@st.com>
| | | | * designware_i2c: Added s/w generation of stop bitArmando Visconti2012-12-11-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the newer versions of designware i2c IP there is the possibility of configuring it with IC_EMPTYFIFO_HOLD_MASTER_EN=1, which basically requires the s/w to generate the stop bit condition directly, as the h/w will not automatically generate it when TX_FIFO is empty. To avoid generation of an extra 0x0 byte sent as data, the IC_STOP command must be sent along with the last IC_CMD. This patch always writes bit[9] of ic_data_cmd even in the older versions, assuming that it is a noop there. Signed-off-by: Armando Visconti <armando.visconti@st.com>
| | | | * designware_i2c.c: Added the support for MULTI_BUSArmando Visconti2012-12-11-1/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the capability to switch between 10 different I2C busses (from 0 to 9). Signed-off-by: Armando Visconti <armando.visconti@st.com>
| | | | * drivers:i2c: Modify I2C driver for Exynos4Piotr Wilczek2012-12-11-7/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch modifies the S3C i2c driver to support both Exynos4 and Exynos5 Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> CC: Minkyu Kang <mk7.kang@samsung.com>
| | | | * omap24xx_i2c: Handle OMAP5 like OMAP2,3,4Vincent Stehlé2012-12-11-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OMAP5 has 8b i2c data register field, like OMAP2, 3 and 4. Handle in the same way. This fixes the following error on OMAP5: OMAP5430 EVM # mmc rescan timed out in wait_for_bb: I2C_STAT=1410 twl6035: could not turn on LDO9. Signed-off-by: Vincent Stehlé <v-stehle@ti.com>
| | | | * mxs: i2c: Implement algorithm to set up arbitrary i2c speedMarek Vasut2012-12-11-53/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This algorithm computes the values of TIMING{0,1,2} registers for the MX28 I2C block. This algorithm was derived by using a scope, but the result seems correct. The resulting values programmed into the registers do not correlate with the contents in datasheet. When using the values from the datasheet, the I2C clock were completely wrong. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Wolfgang Denk <wd@denx.de>
| | | | * mxs: i2c: Restore speed setting after block resetMarek Vasut2012-12-11-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The I2C block reset configures the I2C bus speed to strange value. Read the I2C speed from the block before reseting the block and restore it afterwards, so the I2C operates correctly. This issue can be replicated by doing unsuccessful I2C transfer, after such transfer finishes, the I2C block clock speed is misconfigured. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
| | | | * i2c: mxs: Fix TIMING2 register valueMarek Vasut2012-12-11-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to FSL, the value in the TIMING2 register shall be 0x00300030 instead of what's written in the datasheet. This new value correlates with older STMP36xx datasheet. Issues were detected in Linux when this register was misconfigured, so write this correct value. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
| | | | * i2c: mxs: Use i2c_set_bus_speed() in i2c_init()Marek Vasut2012-12-11-15/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use i2c_set_bus_speed() in i2c_init() within the mxs i2c driver to avoid duplication of code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
| | | | * i2c: mxs: Implement i2c_get/set_bus_speed()Marek Vasut2012-12-11-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements the setup and retrieval functions for the I2C bus speed on the MXS I2C IP. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
| | | | * i2c: mxs: Abstract out the MXS I2C speed setupMarek Vasut2012-12-11-20/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch pulls out the I2C speed setup from the i2c_init() call and implements the bus configuration lookup table with register values that needs to be programmed into the I2C IP to run at particular speed. This patch is a first step towards implementing run-time I2C bus speed configuration for the MXS I2C IP. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
| | | | * i2c: Staticize local functions in mxc i2c driverMarek Vasut2012-12-11-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some functions in the MXC i2c driver were not static, fix this by making them so. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| | | | * soft_i2c: add necessary includes for AVR32Andreas Bießmann2012-12-11-0/+3
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Andreas Bießmann <biessmann@corscience.de>
| | | * | mtd: nand: mxs: reset BCH earlier, too, to avoid NAND startup problemsWolfram Sang2012-12-11-0/+3
| | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It could happen (1 out of 100 times) that NAND did not start up correctly after warm rebooting, so we end up with various failures or DMA timed out due to a stalled BCH. When resetting BCH together with GPMI, the issue could not be observed anymore (after 10000+ reboots). We probably need the consistent state already before sending commands to NAND. This behaviour was observed in barebox and kernel, so I assume it affects U-Boot as well. I chose to keep the extra reset for BCH when changing the flash layout to be on the safe side. Signed-off-by: Wolfram Sang <w.sang@pengutronix.de> Acked-by: Marek Vasut <marex@denx.de>
| | * | Merge branch 'master' of git://git.denx.de/u-boot into masterStefano Babic2012-12-08-716/+15186
| | |\ \ | | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/power/power_fsl.c include/configs/mx35pdk.h include/configs/mx53loco.h include/configs/woodburn_common.h board/woodburn/woodburn.c These boards still use the old old PMIC framework, so they do not merge properly after the power framework was merged into mainline. Fix all conflicts and update woodburn to use Power Framework. Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | | POWER: MAX77686: Modified as per the latest ImplementationRajeshwari Shinde2012-12-11-5/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Moved the pmic_max77686.c max77686_pmic.h to drivers/power and made required changes accordingly Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | Merge branch 'master' of git://git.denx.de/u-boot into resolveMinkyu Kang2012-12-10-717/+15186
| |\ \ \ |/ / / / | | | _ | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: README board/samsung/universal_c210/universal.c drivers/misc/Makefile drivers/power/power_fsl.c include/configs/mx35pdk.h include/configs/mx53loco.h include/configs/seaboard.h
| * | Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2012-12-07-0/+293
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| | * | video: Check for valid FB pointer before clearingDuncan Laurie2012-12-06-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This command will start erasing at memory address zero if there is not a valid framebuffer address that was found during video_init(). This is a common case with Chrome OS devices in normal mode when we do not execute the video option rom in coreboot. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: gpio: Add additional GPIO banks to the ICH6 driverBill Richardson2012-12-06-62/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can generally trust the ICH to have GPIO Bank 0 (the first 32 pins) in the same place across all versions. This change adds two more banks, for up to 96 GPIOS. BUT: - Not all chipsets have the same number of GPIOs - Not all chipsets have the same number of GPIO banks - Not all chipsets put the additional banks at the same offset from GPIOBASE - There so many chipset variants that it's pretty much impossible to support them all, or even keep track of the new ones. So, although this adds suppport for the additional banks that seem to work for the particular variants of CougarPoint Mobile chipsets that we've tried, there's no chance it will support everything Intel produces. Good luck. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: gpio: Add GPIO driver for Intel ICH6 and later.Bill Richardson2012-12-06-0/+243
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement <asm-generic/gpio.h> functions for Intel ICH6 and later. Only GPIOs 0-31 are handled by this code. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | serial_pl011: Set RTS during initializationJoshua Housh2012-12-07-2/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the pl011 is connected to another device which has hardware flow-control on, characters are never received by the pl011. Asserting RTS when flow-control is off will have no effect. This is in line with how Linux behaves. Signed-off-by: Joshua Housh <joshua.housh@calxeda.com> Tested-by: Marek Vasut <marex@denx.de>
| * | Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2012-12-03-0/+170
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| | * | x86: video: Add coreboot framebuffer supportStefan Reinauer2012-11-30-0/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a basic driver for the coreboot framebuffer. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: Add console command to display CBMEM console bufferVadim Bendebury2012-11-30-0/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This command is useful to allow to observe messages generated by coreboot and u-boot until present. In particular it is handy when u-boot is instrumented to fall through into console mode on startup errors. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: Add CBMEM console driver for corebootVadim Bendebury2012-11-30-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch builds upon the recently introduced CBMEM console feature of coreboot. CBMEM console uses a memry area allocated by coreboot to store the console output. The memory area has a certain structure, which allows to determine where the buffer is, the buffer size and the location of the pointer in the buffer. This allows different phases of the firmware (rom based coreboot, ram based coreboot, u-boot after relocation with this change) to keep adding text to the same buffer. Note that this patch introduces a new console driver and adds the driver to the list of drivers to be used for console output, i.e. it engages only after u-boot relocates. Usiong CBMEM console for capturing the pre-relocation console output will be done under a separate change. >From Linux, run the cbmem.py utility (which is a part of the coreboot package) to see the output, e.g.: vvvvvvvvvvvvvvvvv SCSI: AHCI 0001.0300 32 slots 6 ports ? Gbps 0xf impl SATA mode flags: 64bit ilck stag led pmp pio ... Magic signature found Kernel command line: "cros_secure quiet loglevel=1 console=tty2... ^^^^^^^^^^^^^^^^^ Note that the entire u-boot output fits into the buffer only if the coreboot log level is reduced from the most verbose. Ether the buffer size will have to be increased, or the coreboot verbosity permanently reduced. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | serial: serial_sh: bugfix: autoboot fails if serial console is not connectedTetsuyuki Kobayashi2012-11-30-7/+13
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On kzm9g board (rmobile SoC), autoboot fails if serial console cable is not connected. When serial cable is not connected, serial error occurs and some garbage comes in data register. sh_serial_tstc() in serial_sh.c does not check error status and misunderstand there is some input data. It is the reason that autoboot fails. This patch adds checking error status in sh_serial_tstc(). This patch is based on v2013.01-rc1 tag of u-boot master git. Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xxTom Rini2012-11-28-0/+136
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| | * | powerpc/p4080ds: fix PCI-e x8 link training down failureYuanquan Chen2012-11-27-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to SerDes configuration error, if we set the PCI-e controller link width as x8 in RCW and add a narrower width(such as x4, x2 or x1) PCI-e device to PCI-e slot, it fails to train down to the PCI-e device's link width. According to p4080ds errata PCIe-A003, we reset the PCI-e controller link width to x4 in u-boot. Then it can train down to x2 or x1 width to make the PCI-e link between RC and EP. Signed-off-by: Yuanquan Chen <B41889@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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