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* Merge remote-tracking branch 'u-boot-imx/master'Albert ARIBAUD2012-09-29-0/+20
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| * i.MX: mxc_ipuv3_fb: add ipuv3_fb_shutdown() routine to stop IPU frame bufferEric Nelson2012-09-24-0/+20
| | | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
* | Merge remote-tracking branch 'u-boot-atmel/master'Albert ARIBAUD2012-09-29-3/+19
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| * | spiflash: at25: using common spi flash operationBo Shen2012-09-17-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | Using common spi flash operation function to replace private operation funtion Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | spi: add atmel at25df321 serial flash supportBo Shen2012-09-17-0/+10
| | | | | | | | | | | | | | | | | | | | | Add atmel at25df321 serial flash support Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | atmel_nand: fix the U-Boot output information about nand flash with PMECC ↵Wu, Josh2012-09-13-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | enable. Before the patch, it looks like: |U-Boot 2012.07-00441-gd578d6f-dirty (Sep 10 2012 - 16:11:06) | |CPU: AT91SAM9G35 |Crystal frequency: 12 MHz |CPU clock : 400 MHz |Master clock : 133.333 MHz |DRAM: 128 MiB |WARNING: Caches not enabled > |NAND: Initialize PMECC params, cap: 2, sector: 512 > |256 MiB |MMC: mci: 0 |In: serial |Out: serial |Err: serial |Net: macb0 |Hit any key to stop autoboot: 0 After the patch: |U-Boot 2012.07-00441-gd578d6f-dirty (Sep 10 2012 - 16:18:11) | |CPU: AT91SAM9G35 |Crystal frequency: 12 MHz |CPU clock : 400 MHz |Master clock : 133.333 MHz |DRAM: 128 MiB |WARNING: Caches not enabled > |NAND: 256 MiB | ... ... |Hit any key to stop autoboot: 0 Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | Merge remote-tracking branch 'u-boot-imx/master'Albert ARIBAUD2012-09-21-25/+37
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| * | MX28: MMC: Avoid DMA DCache race conditionMarek Vasut2012-09-06-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch prevents dcache-related problem. The problem manifested itself on the SPI driver, this is just a port to the MMC driver. The scenario is the same. In case an "mmc read" is issued to a buffer which was written right before it and data cache is enabled, the cache eviction might happen during the DMA transfer into the buffer, therefore corrupting the buffer. Clear any cache lines that might contain the buffer to prevent such issue. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| * | MX28: SPI: Fix the DMA chainingMarek Vasut2012-09-06-18/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It turns out that in order for the SPI DMA to properly support continuous transfers longer than 65280 bytes, there are some very important parts that were left out from the documentation. Firstly, the XFER_SIZE register is not written with the whole length of a transfer, but is written by each and every chained descriptor with the length of the descriptors data buffer. Next, unlike the demo code supplied by FSL, which only writes one PIO word per descriptor, this does not apply if the descriptors are chained, since the XFER_SIZE register must be written. Therefore, it is essential to use four PIO words, CTRL0, CMD0, CMD1, XFER_SIZE. CMD0 and CMD1 are written with zero, since they don't apply. The DMA programs the PIO words in an incrementing order, so four PIO words. Finally, unlike the demo code supplied by FSL, the SSP_CTRL0_IGNORE_CRC must not be set during the whole transfer, but it must be set only on the last descriptor in the chain. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| * | MX28: SPI: Fix the DMA DCache race conditionMarek Vasut2012-09-06-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes dcache-related problem. The problem manifested when dcache was enabled and the following command issued twice: mw 0x42000000 0 0x4000 ; sf probe ; sf read 0x42000000 0x0 0x10000 ; sha1sum 0x42000000 0x10000 The SHA1 checksum was correct during the first call. Yet with every subsequent call of the above command, it differed and was wrong. It turns out this was because of a race condition. On the first time the command was called, no cacheline contained any data from the destination memory location. The DMA transfered data into the location and the cache above the location was invalidated. Then the checksum was computed, but that meant the data were loaded into data cache. On any subsequent call, the DMA again transfered data into the same destination. Yet during the transfer, some of the DCache lines were evicted and written back into the main memory. Once the DMA transfer completed, the data cache was invalidated over the memory location as usual. But the data that were to be loaded back into the data cache by subsequent SHA1 checksuming were corrupted. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
* | | NAND: MXS: include common.h first so cache.h is included in correct orderTom Warren2012-09-10-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With Simon Glass's include/nand.h alignment changes, some mxs builds were generating errors. Fix is to ensure asm/cache.h is included before linux/mtd/nand.h. Moving common.h to top of include list does that. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de>
* | | Tegra: Change Tegra20 to Tegra in common code, prep for T30Tom Warren2012-09-10-162/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert TEGRA20_ defines to either TEGRA_ or NV_PA_ where appropriate. Convert tegra20_ source file and function names to tegra_, also. Upcoming Tegra30 port will use common code/defines/names where possible. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
* | | mmc: detect boot sectors using EXT_CSD_BOOT_MULT tooStephen Warren2012-09-07-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some eMMC devices contain boot partitions, but do not set the PART_SUPPORT bit in EXT_CSD_PARTITIONING_SUPPORT. Allow partition selection on such devices, by enabling partition switching when EXT_CSD_BOOT_MULT is set. Note that the Linux kernel enables access to boot partitions solely based on the value of EXT_CSD_BOOT_MULT; EXT_CSD_PARTITIONING_SUPPORT only influences access to "general" partitions. eMMC devices affected by this issue exist on various NVIDIA Tegra platforms (and presumably many others too), such as Harmony (plug-in eMMC), Seaboard, Springbank, and Whistler (plug-in eMMC). Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | tegra: nand: Add Tegra NAND driverJim Lin2012-09-07-0/+1284
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A device tree is used to configure the NAND, including memory timings and block/pages sizes. If this node is not present or is disabled, then NAND will not be initialized. Signed-off-by: Jim Lin <jilin@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | nand: Try to align the default buffersSimon Glass2012-09-07-1/+2
| |/ |/| | | | | | | | | | | | | | | | | The NAND layer needs to use cache-aligned buffers by default. Towards this goal. align the default buffers and their members according to the minimum DMA alignment defined for the architecture. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Scott Wood <scottwood@freescale.com>
* | video: drop duplicate set of DISPC_CONFIG registerStefano Babic2012-09-04-2/+1
|/ | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
* kw_spi: fix clock prescaler computationValentin Longchamp2012-09-03-2/+3
| | | | | | | | | | | | | | | | | The computation was not correct with low clock values: setting a 1MHz clock would result in an overlap that would then configure a 25Mhz clock. This patch implements a correct computation method according to the kirkwood functionnal spec. table 600 (Serial Memory Interface Configuration Register). Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Holger Brunck <holger.brunck@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> Acked-by: Prafulla Wadaskar <Prafulla@marvell.com> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
* Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-stagingWolfgang Denk2012-09-02-3/+0
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | * 'agust@denx.de' of git://git.denx.de/u-boot-staging: tx25: Use generic gpio_* calls config: Always use GNU ld tools: add kwboot binary to .gitignore file fdt: Include arch specific gpio.h instead of asm-generic/gpio.h serial: CONSOLE macro is not used Conflicts: board/karo/tx25/tx25.c Signed-off-by: Wolfgang Denk <wd@denx.de>
| * serial: CONSOLE macro is not usedMichal Simek2012-08-10-3/+0
| | | | | | | | | | Signed-off-by: Michal Simek <monstr@monstr.eu> Acked-by: Mike Frysinger <vapier@gentoo.org>
* | at91: atmel_nand: Update driver to support Programmable Multibit ECC controllerWu, Josh2012-09-01-1/+792
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Programmable Multibit ECC (PMECC) controller is a programmable binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder. This controller can be used to support both SLC and MLC NAND Flash devices. It supports to generate ECC to correct 2, 4, 8, 12 or 24 bits of error per sector of data. To use PMECC in this driver, the user needs to set the PMECC correction capability, the sector size and ROM lookup table offsets in board config file. This driver is ported from Linux kernel atmel_nand PMECC patch. The main difference is in this version it uses registers structure access hardware instead of using macros. It is tested in 9x5 serial boards. Signed-off-by: Josh Wu <josh.wu@atmel.com> [rebase] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | at91: atmel_nand: remove unused variables.Wu, Josh2012-09-01-2/+1
| | | | | | | | | | | | Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | at91: atmel_nand: extract HWECC initialization code into one function: ↵Wu, Josh2012-09-01-58/+86
| | | | | | | | | | | | | | | | | | | | | | | | atmel_hw_nand_init_param(). This patch 1. extract the hwecc initialization code into one function. It is a preparation for adding atmel PMECC support. 2. enable CONFIG_SYS_NAND_SELF_INIT. Which make us can configurate the ecc parameters between nand_scan_ident() and nand_scan_tail(). Signed-off-by: Josh Wu <josh.wu@atmel.com> [fix empty newline at EOF error and move return value check into ifdef] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | spi: atmel: add WDRBT bit to avoid receive overrunBo Shen2012-09-01-0/+4
| | | | | | | | | | | | | | | | | | | | The atmel at91sam9x5 series spi has feature to avoid receive overren Using the patch to enable it Signed-off-by: Bo Shen <voice.shen@atmel.com> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | AT91: Small fix on AT91 USART initialization codeXu, Hong2012-09-01-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | Before reset dbgu transmitter, we just wait TXEMPTY to drain the transmitter register(Just in case). If not doing this, we may sometimes see several weird characters from DBGU. A short delay is also added to make sure the new serial settings are settled. Signed-off-by: Hong Xu <hong.xu@atmel.com> [cherry-picked from u-boot-atmel/old-next] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | fsl_esdhc: Remove cache snooping for i.MXBenoît Thébaudeau2012-09-01-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The cache snooping feature of Freescale's eSDHC IP is not available on i.MX, so disable it globally for this architecture. This avoids setting no_snoop for all i.MX boards, and it prevents setting a reserved bit of a reserved register if fsl_esdhc_mmc_init() is used on i.MX, like in arch/arm/cpu/armv7/imx-common/cpu.c/cpu_mmc_init(). Since no_snoop was only used on i.MX, get rid of it BTW. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Andy Fleming <afleming@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Kim Phillips <kim.phillips@freescale.com>
* | MX28: SPI: Supercharge the SPI driverMarek Vasut2012-09-01-31/+65
| | | | | | | | | | | | | | | | | | | | This change implements DMA chaining into SPI driver. This allows the transfers to go much faster, while also fixing SF issues. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
* | MX28: DMA: Prolong the DMA timeoutMarek Vasut2012-09-01-1/+1
| | | | | | | | | | | | | | | | | | | | | | Load from SPI flash can create a long DMA chain, which can take long time to transfer. Change the DMA timeout to roughly 10s to prevent such long chains misreporting errors. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
* | gpio: add gpio api support to mx27 (v4)trem2012-09-01-3/+5
| | | | | | | | | | | | | | The gpio api has been tested on an armadeus apf27. Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr> Acked-by: Stefano Babic <sbabic@denx.de>
* | mxc: Make gpio_get_value() use PSRBenoît Thébaudeau2012-09-01-1/+1
| | | | | | | | | | | | | | | | | | | | | | gpio_get_value() should use PSR like Linux, not DR, because DR does not always reflect the pin state, while PSR does. This is especially useful to detect a short circuit on a GPIO pin configured as output, or to read the level of a pin controlled by a non-GPIO IOMUX function. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* | spi: fix mxs_spi_slave structure allocation to clear memoryMatt Sealey2012-09-01-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use calloc() instead of malloc() to allocate the mxs_spi_slave structure. Clearing the memory is necessary since most of the time this gets done super early in boot, but on warm reboots, and when SPI probing is done long after the init stages it could actually pick up previously used memory, and things like the chipselect polarity and other data end up being filled with trash data if not explicitly set by the board files. This solves a semi-random, almost unreproducable error whereby SPI devices act very, very strangly on boot. Signed-off-by: Matt Sealey <matt@genesi-usa.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | spi: fix mxc_spi_slave structure allocation to clear memoryMatt Sealey2012-09-01-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use calloc() instead of malloc() to allocate the mxc_spi_slave structure. Clearing the memory is necessary since most of the time this gets done super early in boot, but on warm reboots, and when SPI probing is done long after the init stages it could actually pick up previously used memory, and things like the chipselect polarity and other data end up being filled with trash data if not explicitly set by the board files. This solves a semi-random, almost unreproducable error whereby SPI devices act very, very strangly on boot. Tested on Efika MX over several years.. Signed-off-by: Matt Sealey <matt@genesi-usa.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | mxc_spi: Round up clock dividerBenoît Thébaudeau2012-09-01-2/+2
| | | | | | | | | | | | | | | | | | | | | | Since the input frequency of the API is a maximum that should not be exceeded in order for the devices to operate properly, the SPI clock divider should be rounded up, not truncated. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* | rtc: add support of mx27 rtctrem2012-09-01-0/+84
| | | | | | | | | | | | | | This driver has been tested on board armadeus apf27. Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr> Acked-by: Stefano Babic <sbabic@denx.de>
* | mxs: Convert sys_proto.h prefixes to 'mxs'Otavio Salvador2012-09-01-13/+13
| | | | | | | | | | | | | | The sys_proto.h functions (except the boot modes) are compatible with i.MX233 and i.MX28 so we use 'mxs' prefix for its methods. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* | mxs: rename regs-clkctrl.h to regs-clkctrl-mx28.hOtavio Salvador2012-09-01-1/+1
| | | | | | | | | | | | | | The CLKCTRL registers are SoC specific so we ought to have it clear on filename. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* | video: support exynos pwm backlight driverDonghwa Lee2012-09-01-0/+58
| | | | | | | | | | | | | | | | | | This patch support exynos pwm backlight driver. It can control backlight power and brightness by using pwm. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | video: exynos fb driver supports display port featureDonghwa Lee2012-09-01-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | If dp_enabled was set, exynos fb driver support display port feature. This patch depends on [PATCH] video: support exynos fimd driver for various exynos series. http://marc.info/?l=u-boot&m=134119605104467&w=2 Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | video: support exynos display port driversDonghwa Lee2012-09-01-0/+2297
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch set supports exynos display port drivers. DisplayPort is an industry standard device to accommodate the increasing board adoption of digital display technology within the PC and consumer electronics. The interface supports internal chip-to-chip and external box-to-box digital display connections. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | video: support exynos fimd driver for various exynos seriesDonghwa Lee2012-09-01-33/+43
| | | | | | | | | | | | | | | | | | This patch supports exynos fimd driver for various exynos series different from existing it supports only exynos4 chip. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | tegra20: rename tegra2 -> tegra20Allen Martin2012-09-01-40/+40
| | | | | | | | | | | | | | | | | | | | This is make naming consistent with the kernel and devicetree and in preparation of pulling out the common tegra20 code. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: add basic support for the Broadcom BCM2835 SoCStephen Warren2012-09-01-0/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This SoC is used in the Raspberry Pi, for example. For more details, see: http://www.broadcom.com/products/BCM2835 http://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf. Initial support is enough to boot to a serial console, execute a minimal set of U-Boot commands, download data over a serial port, and boot a Linux kernel. No storage or network drivers are implemented. GPIO driver originally by Vikram Narayanan <vikram186@gmail.com> with many fixes from myself. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* | u8500: Separating mmc config parameters from driverJohn Rigby2012-09-01-83/+75
| | | | | | | | | | | | | | | | | | | | Configuration in vexpress and u8500.v1 is different from what is needed in u8500.v2. As such, card configuration specifics need to reside in the board file rather than the driver. Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Tom Rini <trini@ti.com>
* | snowball: Add support for ux500 based snowball boardMathieu J. Poirier2012-09-01-0/+224
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org> Acked-by: Tom Rini <trini@ti.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Conflicts: drivers/gpio/Makefile
* | arm: omap: Fix switching back to nandecc sw.Jeroen Hofstee2012-09-01-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Orjan Friberg wrote at [1]: "For the beagleboard, ecc.size is not explicitly set when doing 'nandecc sw'. If it's not set for the NAND_ECC_SOFT case in nand_scan_tail, it's set to 256 bytes. When doing 'nandecc hw', ecc.size is set to 512 bytes. Hence, when changing back to 'nandecc sw' ecc.size remains at 512 bytes and suddenly the format has changed." No patch has been submitted and the issue was still present. This patch adds the mentioned solution. Tested on a tam3517 board. [1] http://lists.denx.de/pipermail/u-boot/2012-February/119002.html cc: Orjan Friberg <of@flatfrog.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Jeroen Hofstee <jhofstee@victronenergy.com>
* | da8xx/hawkboard: Add support for ohci host controllerSughosh Ganu2012-09-01-103/+51
| | | | | | | | | | | | | | | | | | | | Also enable the ohci port on hawkboard. These additions result in an increased u-boot size -- adjust the same accordingly in the board's config. Move the usb header for da8xx platforms under arch-davinci. Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
* | am335x evm: Enable support for spi0Tom Rini2012-09-01-0/+10
| | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
* | am33xx: Add support, update omap3 McSPI driverTom Rini2012-09-01-0/+11
| | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
* | rtc: imxdi: Initial supportBenoît Thébaudeau2012-09-01-0/+245
| | | | | | | | | | | | | | | | | | Add support for Freescale's i.MX DryIce RTC, present on i.MX25. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* | MX28: Fix MXS MMC DMA issuesMarek Vasut2012-09-01-15/+19
| | | | | | | | | | | | | | | | | | | | | | | | The DMA didn't work properly because the DMA descriptor wasn't properly cleaned after it was used once. Also, the DMA_ENABLE bit was enabled/disabled too late. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
* | MX28: Transfer small blocks via PIO in MXS MMCMarek Vasut2012-09-01-26/+20
| | | | | | | | | | | | | | | | | | | | | | Large blocks (> 512b) shall be transfered via DMA to make things a bit faster. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
generated by cgit v1.1 at 2024-12-27 18:11:05 +0000