summaryrefslogtreecommitdiff
path: root/drivers
Commit message (Collapse)AuthorAgeLines
* USB: gadget: atmel_usba_udc: fix transfer hang issueBo Shen2014-12-16-1/+0
| | | | | | | | | | | | | When receive data, the RXRDY in status register set by hardware after a new packet has been stored in the endpoint FIFO. After, we copy from FIFO, we clear it, make the FIFO can be accessed again. In the receive_data() function, this bit RXRDY has been cleared. So, after the receive_data() function return, this bit should not be cleared again, or else it will cause the accessing FIFO corrupt, which will make the data loss. Signed-off-by: Bo Shen <voice.shen@atmel.com>
* Merge git://git.denx.de/u-boot-x86Tom Rini2014-12-15-129/+157
|\
| * x86: ich-spi: Add Intel Tunnel Creek SPI controller supportBin Meng2014-12-13-1/+2
| | | | | | | | | | | | | | | | Add Intel Tunnel Creek SPI controller support which is an ICH7 compatible device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Add a simple superio driver for SMSC LPC47MBin Meng2014-12-13-0/+34
| | | | | | | | | | | | | | | | | | On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8) are provided by a superio chip connected to the LPC bus. We must program the superio chip so that serial ports are available for us. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: ich6-gpio: Move setup_pch_gpios() to board support codesBin Meng2014-12-13-51/+2
| | | | | | | | | | | | | | | | | | Movie setup_pch_gpios() in the ich6-gpio driver to the board support codes, so that the driver does not need to know any platform specific stuff (ie: include the platform specifc chipset header file). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: ich-spi: Set the tx operation mode for ich 7Bin Meng2014-12-13-2/+7
| | | | | | | | | | | | | | | | ICH 7 SPI controller only supports byte program (02h) for SST flash. Word program (ADh) is not supported. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * x86: ich-spi: Set the rx operation mode for ich 7Bin Meng2014-12-13-0/+4
| | | | | | | | | | | | | | | | | | | | ICH 7 SPI controller only supports array read command (03h). Fast array read command (0Bh) is not supported. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * sf: Enable byte program supportJagannadha Sutradharudu Teki2014-12-13-12/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Enabled byte program support for sst flashes in sf. Few controllers will only support BP, so this patch gives a tx transfer flag to set the BP so-that sf will operate on byte program transfer. A new TX operation mode SPI_OPM_TX_BP is introduced for such SPI controller to use byte program op for SST flash. Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * spi: sf: Support byte program for sst spi flashBin Meng2014-12-13-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently if SST flash advertises SST_WP flag in the params table the word program command (ADh) with auto address increment will be used for the flash write op. However some SPI controllers do not support the word program command (like the Intel ICH 7), the byte programm command (02h) has to be used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * spi: Fix flag collision for SST_WPSimon Glass2014-12-13-1/+1
| | | | | | | | | | | | | | | | | | At present SECT_4K is the same as SST_WP so we cannot tell these apart. Fix this so that the table in sf_params.c can be used correctly. Reported-by: Jens Rottmann <Jens.Rottmann@adlinktech.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * sf: Fix look for the fastest read commandJagannadha Sutradharudu Teki2014-12-13-56/+60
| | | | | | | | | | | | | | | | | | | | | | Few of the spi controllers are only supports array slow read which is quite different behaviour compared to others. So this fix on sf will correctly handle the slow read supported controllers. Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * bios_emulator: Correct ordering of includesSimon Glass2014-12-13-2/+2
| | | | | | | | | | | | | | We should include common.h before other includes. This actually causes a build error on chromebook_link. Signed-off-by: Simon Glass <sjg@chromium.org>
| * gpio: intel_ich6: Set correct gpio output value in ich6_gpio_direction_output()Axel Lin2014-12-13-0/+2
| | | | | | | | | | | | | | | | Current code does not set gpio output value in ich6_gpio_direction_output(), fix it. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: ich-spi: Fix a bug of reading from a non-64 bytes aligned addressBin Meng2014-12-13-15/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | The ich spi controller driver spi_xfer() tries to align reading address to 64 bytes when doing spi data in, which causes a bug of either infinite loop or a huge size memcpy(). Actually the ich spi controller does not have such requirement of 64 bytes alignment when reading data from spi slave devices. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-mmcTom Rini2014-12-12-35/+74
|\ \ | |/ |/|
| * mmc: dw_mmc: Use active DDR mode flagAndrew Gabbasov2014-12-12-1/+1
| | | | | | | | | | | | | | The card_caps bit should denote the card capability to use DDR mode, but we need the flag indicating that the DDR mode is active. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
| * mmc: Fix block length for DDR modeAndrew Gabbasov2014-12-12-0/+6
| | | | | | | | | | | | | | | | | | Block length for write and read commands is fixed to 512 bytes when the card is in Dual Data Rate mode. If block length read from CSD is different, make sure the driver will use correct length in all further calculations and settings. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
| * mmc: Fix Dual Data Rate capability recognitionAndrew Gabbasov2014-12-12-1/+1
| | | | | | | | | | | | | | | | | | Since the driver doesn't work in 1.2V or 1.8V signaling level modes, Dual Data Rate mode can be supported by the driver only if it is supported by the card in regular 3.3V mode. So, check for a particular single bit in card type field. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
| * mmc: Fix handling of bus widths and DDR card capabilitiesAndrew Gabbasov2014-12-12-21/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the MMC_MODE_DDR_52MHz flag is set in card capabilities bitmask, it is never cleared, even if switching to DDR mode fails, and if the controller driver uses this flag to check the DDR mode, it can take incorrect actions. Also, DDR related checks in mmc_startup() incorrectly handle the case when the host controller does not support some bus widths (e.g. can't support 8 bits), since the host_caps is checked for DDR bit, but not bus width bits. This fix clearly separates using of card_caps bitmask, having there the flags for the capabilities, that the card can support, and actual operation mode, described outside of card_caps (i.e. bus_width and ddr_mode fields in mmc structure). Separate host controller drivers may need to be updated to use the actual flags. Respectively, the capabilities checks in mmc_startup are made more correct and clear. Also, some clean up is made with errors handling and code syntax layout. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
| * mmc: exynos_dw-mmc: change debug messageJaehoon Chung2014-12-12-10/+12
| | | | | | | | | | | | To debug more exactly, add the index for device. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
| * MMC: add MMC_VERSION_5_0Markus Niebel2014-12-12-0/+3
| | | | | | | | | | Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
| * MMC: fix user capacity for partitioned eMMC cardMarkus Niebel2014-12-12-0/+15
| | | | | | | | | | | | | | | | | | | | if the card claims to be high capacity and the card is partitioned the capacity shall still be read from ext_csd SEC_COUNT even if the resulting capacity is smaller than 2 GiB Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
| * mmc: Cosmetic fix for nicer, aligned device list printoutLubomir Popov2014-12-12-2/+5
| | | | | | | | | | | | | | | | If print_mmc_devices() was called with a '\n' separator (as done for example by the "mmc list" command), it offset the 2-nd and all subsequent lines by one space. Fixing this. Signed-off-by: Lubomir Popov <l-popov@ti.com>
* | Merge git://git.denx.de/u-boot-dmTom Rini2014-12-11-294/+946
|\ \ | |/ |/|
| * dm: i2c: tegra: Convert to driver modelSimon Glass2014-12-11-267/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This converts all Tegra boards over to use driver model for I2C. The driver is adjusted to use driver model and the following obsolete CONFIGs are removed: - CONFIG_SYS_I2C_INIT_BOARD - CONFIG_I2C_MULTI_BUS - CONFIG_SYS_MAX_I2C_BUS - CONFIG_SYS_I2C_SPEED - CONFIG_SYS_I2C This has been tested on: - trimslice (no I2C) - beaver - Jetson-TK1 It has not been tested on Tegra 114 as I don't have that board. Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: device: Add newline to debug() messagesSimon Glass2014-12-11-3/+3
| | | | | | | | | | | | Some of these are missing a newline. Add it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: Add a simple EEPROM driverSimon Glass2014-12-11-0/+52
| | | | | | | | | | | | | | | | | | | | There seem to be a few EEPROM drivers around - perhaps we should have a single standard one? This simple driver is used for sandbox testing, but could be pressed into more active service. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * dm: i2c: Add an I2C EEPROM simulatorSimon Glass2014-12-11-0/+171
| | | | | | | | | | | | | | | | | | To enable testing of I2C, add a simple I2C EEPROM simulator for sandbox. It supports reading and writing from a small data store. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * dm: i2c: Add a sandbox I2C driverSimon Glass2014-12-11-1/+112
| | | | | | | | | | | | | | | | | | This driver includes some test features such as only supporting certain bus speeds. It passes its I2C traffic through to an emulator. Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * dm: i2c: Add I2C emulation driver for sandboxSimon Glass2014-12-11-0/+15
| | | | | | | | | | | | | | | | | | In order to test I2C we need some sort of emulation interface. Add hooks to allow a driver to emulate an I2C device for sandbox. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * dm: i2c: Add a uclass for I2CSimon Glass2014-12-11-0/+467
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The uclass implements the same operations as the current I2C framework but makes some changes to make it fit driver model better: - Remove the chip address from API calls - Remove the address length from API calls - Remove concept of 'current' I2C bus - Drop all existing init functions Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: serial_pl01x: Add missing private data sizeSimon Glass2014-12-11-0/+1
| | | | | | | | | | | | | | | | | | | | | | The private data size is missing from the driver, so we store it at 0, which causes problems when something overwrites memory at 0. Fix this. Change-Id: I6f551ee905b0064ae8343e41e46450c37c8c8c1a Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org>
| * lib: string: move strlcpy() to a common placeMasahiro Yamada2014-12-11-24/+0
| | | | | | | | | | | | | | | | | | Move strlcpy() definition from drivers/usb/gadget/ether.c to lib/string.c because it is a very useful function. Let's add the prototype to include/linux/string.h too. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2014-12-11-5/+52
|\ \ | | | | | | | | | | | | | | | | | | Conflicts: board/freescale/mx6sxsabresd/mx6sxsabresd.c Signed-off-by: Tom Rini <trini@ti.com>
| * | usb: ehci: do not set the LSB of Current qTD pointerMasahiro Yamada2014-11-19-1/+0
| | | | | | | | | | | | | | | | | | | | | According to EHCI specification, the LSB of DWORD 3 of Queue Head (Current qTD Pointer) is not T-bit, but always zero. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | dfu: thor: fix: Modify dfu_get_alt() function to support absolute pathsLukasz Majewski2014-11-14-2/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recently the ext4 file system imposed passing absolute path with its file name parameter. As a result dfu_alt_info env variable has been modified to provide absolute path when ext4 file system is accessed (e.g. /uImage ext4 0 2;). Unfortunately, lthor flashing program provides plain file name (like uImage) and hence those two file names do not match anymore. Presented commit also allows lthor to write files to sub directories (like /boot/bin/uImage). Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Reviewed-by: Marek Vasut <marex@denx.de>
| * | usb:ehci-mx6 add phy mode query functionPeng Fan2014-11-14-2/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | usb_phy_enable should return status bit, but not phy mode bit, thus add a new function usb_phy_mode to query the PHY for it's mode and make usb_phy_enable just return 0 but not 'phy_ctrl & USBPHY_CTRL_OTG_ID'. Include a new board weak function board_usb_phy_mode. If board code does not reimplement this function, it just call usb_phy_mode and return usb_phy_mode's return value. The reason to include such a weak function is: " SOC OTG core <--connect--> board HOST port, but no pin id for the board host port, so board can not use usb_phy_mode to return the phy mode, but define it's own rule." Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye Li <B37916@freescale.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2014-12-11-54/+352
|\ \ \ | |_|/ |/| |
| * | driver/mtd: Fix IFC compilation warningsJaiprakash Singh2014-12-11-1/+1
| | | | | | | | | | | | | | | | | | | | | 'eccstat' array elements might be used uninitialized Signed-off-by: Jaiprakash Singh <b44839@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | fsl/sleep: updated the deep sleep framework for QorIQ platformsTang Yuantian2014-12-11-53/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the introducing of generic board and ARM-based cores, current deep sleep framework doesn't work anymore. This patch will convert the current framework to adapt this change. Basically it does: 1. Converts all the Freescale's DDR driver to support deep sleep. 2. Added basic framework support for ARM-based and PPC-based cores separately. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers: usb: fsl: Check USB Erratum A007792 applicabilityNikhil Badola2014-12-11-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | Check USB Erratum A007792 applicability. If applicable, add corresponding property in the device tree via device tree fixup Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers: usb: fsl: Add USB device-tree errata frameworkNikhil Badola2014-12-11-0/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new framework for fsl usb erratum handling to standardize erratum checking only inside Uboot. Information to kernel is passed via a boolean property corresponding to erratum, hence eliminating need for code duplication inside kernel Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers: usb: Make usb device-tree fixup code architecture independentNikhil Badola2014-12-11-0/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | move usb device tree fixup code from "arch/powerpc/" to "drivers/usb/" so that it works independent of architecture it is running on Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls102xa: Add NAND boot support for LS1021AQDS boardAlison Wang2014-12-11-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds NAND boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from NAND flash to DDR, finally SPL transfer control to u-boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls102xa: Update PCIe dts node statusMinghuan Lian2014-12-11-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | The patch changes PCIe dts node status to 'disabled' if the corresponding controller is disabled according to serdes protocol. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-12-10-14/+18
|\ \ \ | |/ / |/| |
| * | sata: fix reset_sata for dwc_ahsataSoeren Moch2014-12-01-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - fix crash when sata device is not initialized - remove disable_sata_clock() since it is not clear which clock for which device should be disabled here - call disable_sata_clock() for mx6 in preboot_os instead Signed-off-by: Soeren Moch <smoch@web.de> Acked-by: Nikita Kiryanov <nikita@compulab.co.il> Tested-by: Nikita Kiryanov <nikita@compulab.co.il>
| * | mxc_ocotp: Do not disable the OCOTP clock after every accessFabio Estevam2014-12-01-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Leave the OCOTP turned on, so that we subsequent access do not fail. After enabling the thermal driver on a mx6sxsabresd board: U-Boot 2015.01-rc1-18267-g99d4189-dirty (Nov 24 2014 - 12:59:01) CPU: Freescale i.MX6SX rev1.0 at 792 MHz CPU: Temperature 48 C Reset cause: POR Board: MX6SX SABRE SDB I2C: ready DRAM: 1 GiB PMIC: PFUZE100 ID=0x10 MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 00:01.0 - 16c3:abcd - Bridge device 01:00.0 - 8086:08b1 - Network controller In: serial Out: serial Err: serial Net: (hang) As the thermal driver accesses the ocotp registers, its clock will be disabled afterwards. Then when the MAC address is read (also from ocotp registers) it will cause a hang. Do not disable the ocotp clock to prevent this problem. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
| * | thermal: imx_thermal: Do not display calibration dataFabio Estevam2014-12-01-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Printing the calibration data on every boot does not provide really useful information: U-Boot 2015.01-rc1-18266-ge7eb277 (Nov 24 2014 - 11:29:51) CPU: Freescale i.MX6Q rev1.2 at 792 MHz CPU: Thermal calibration data: 0x5d85067d CPU: Temperature 33 C Reset cause: POR Board: MX6-SabreSD Do not display the calibration data in order to have a cleaner boot log. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | mxs_ocotp: clear the error flag before initiating write operationHector Palacios2014-12-01-0/+2
| | | | | | | | | | | | | | | | | | | | | A previous operation may have set the error flag, which must be cleared before a new write operation can be issued. Signed-off-by: Hector Palacios <hector.palacios@digi.com>
generated by cgit v1.1 at 2024-12-19 09:22:28 +0000