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* mtd: nand: omap: optimized chip->ecc.correct() for H/W ECC schemespekon gupta2014-03-03-90/+71
| | | | | | | | | | | | | | | | | | | chip->ecc.correct() is used for detecting and correcting bit-flips during read operations. In omap-nand driver it implemented as: (a) omap_correct_data(): for h/w based ECC_HAM1 scheme (b) omap_correct_data_bch() + CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW_DETECTION_SW for ECC_BCH8 scheme using GPMC and software lib/bch.c (c) omap_correct_data_bch() + CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW for ECC_BCH8 scheme using GPMC and ELM This patch updates (c) - checks for calc_ecc[]==0x00 so that error_correction is not required for known good pages. - adds scalability for other ECC_BCHx scheme by merging following omap_rotate_ecc_bch() + omap_fix_errors_bch() => omap_correct_data_bch() - fixing logic for bit-flip correction based on error_loc[count] Signed-off-by: Pekon Gupta <pekon@ti.com>
* mtd: nand: omap: optimize chip->ecc.calculate() for H/W ECC schemespekon gupta2014-03-03-163/+63
| | | | | | | | | | | | | | | | | chip->ecc.calculate() is used for calculating and fetching of ECC syndrome by processing the data passed during Read/Write accesses. All H/W based ECC schemes use GPMC controller to calculate ECC syndrome. But each BCHx_ECC scheme has its own implemetation of post-processing and fetching ECC syndrome from GPMC controller. This patch updates OMAP_ECC_BCH8_CODE_HW ECC scheme in following way: - merges multiple chip->calculate API for different ECC schemes omap_calculate_ecc() + omap_calculate_ecc_bch() + omap_calculate_ecc_bch_sw() ==> omap_calculate_ecc() - removes omap_ecc_disable() and instead uses it as inline. Signed-off-by: Pekon Gupta <pekon@ti.com>
* mtd: nand: omap: optimize chip->ecc.hwctl() for H/W ECC schemespekon gupta2014-03-03-142/+56
| | | | | | | | | | | | | | | | | | | chip->ecc.hwctl() is used for preparing the H/W controller before read/write NAND accesses (like assigning data-buf, enabling ECC scheme configs, etc.) Though all ECC schemes in OMAP NAND driver use GPMC controller for generating ECC syndrome (for both Read/Write accesses). But but in current code HAM1_ECC and BCHx_ECC schemes implement individual function to achieve this. This patch (1) removes omap_hwecc_init() and omap_hwecc_init_bch() as chip->ecc.hwctl will re-initializeGPMC before every read/write call. omap_hwecc_init_bch() -> omap_enable_ecc_bch() (2) merges the GPMC configuration code for all ECC schemes into single omap_enable_hwecc(), thus adding scalability for future ECC schemes. omap_enable_hwecc() + omap_enable_ecc_bch() -> omap_enable_hwecc() Signed-off-by: Pekon Gupta <pekon@ti.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-02-26-0/+1008
|\ | | | | | | | | | | | | | | | | Conflicts: arch/arm/cpu/armv7/config.mk board/ti/am43xx/mux.c include/configs/am43xx_evm.h Signed-off-by: Tom Rini <trini@ti.com>
| * mmc: kona: Add Kona mmc driverDarwin Rambo2014-02-22-0/+135
| | | | | | | | | | | | | | | | Add support for the Kona SDHCI found on Broadcom mobile SoCs. Signed-off-by: Darwin Rambo <drambo@broadcom.com> Reviewed-by: Steve Rae <srae@broadcom.com> Reviewed-by: Tim Kryger <tkryger@linaro.org>
| * i2c: kona: Add Kona I2C driverDarwin Rambo2014-02-22-0/+731
| | | | | | | | | | | | | | | | Add support for the Kona I2C controller found on Broadcom mobile SoCs. Signed-off-by: Darwin Rambo <drambo@broadcom.com> Reviewed-by: Steve Rae <srae@broadcom.com> Reviewed-by: Tim Kryger <tkryger@linaro.org>
| * gpio: kona: Add Kona gpio driverDarwin Rambo2014-02-22-0/+142
| | | | | | | | | | | | | | | | | | Add support for the Kona GPIO controller found on Broadcom mobile SoCs. Signed-off-by: Darwin Rambo <drambo@broadcom.com> Reviewed-by: Steve Rae <srae@broadcom.com> Reviewed-by: Markus Mayer <markus.mayer@linaro.org> Reviewed-by: Tim Kryger <tkryger@linaro.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-02-25-1/+2
|\ \ | | | | | | | | | | | | | | | | | | With this, fixup a trivial build error of get_effective_memsize needing to be updated in the new board/freescale/p1010rdb/spl.c Signed-off-by: Tom Rini <trini@ti.com>
| * | fsl/usb: Limit phy_type comparison to first four charactersNikhil Badola2014-02-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use first four characters for phy_type comparison. Strcmp() should not be used to check the phy_type string which maybe parsed by hwconfig_subarg(). Hwconfig_subarg() returns part of hwconfig string starting from phy_type value till the end of the string. Since phy_type could be either "utmi" or "ulpi", strncmp() should be used so that a comparison of "utmi;fsl_ddr:bank_intlv=auto" with "utmi" will succeed. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | ar8031/8033/phy:enable autonegotiation for ar8031/8033Zhao Qiang2014-02-24-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before while "if (phydev->supported & SUPPORTED_Autoneg)" now. So assign "phydev->supported" to "phydev->drv->features" for ar8031/8033 to enable autonegotiation. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | power: fix: Do not execute pmic command when not all necessary parameters ↵Łukasz Majewski2014-02-24-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | are passed Lack of this check resulted in a data abort when CPU tried to execute the following command (without further mandatory input): 'pmic MAX77686_PMIC'. Only the 'pmic list' command requires one passed parameter. Other require at least two valid parameters for correct operation. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
* | | SMC91111: Fix compilation warningsBhupesh Sharma2014-02-21-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the following warning messages coming out of 'drivers/net/smc91111.h' when compiled for 'vexpress_aemv8a': warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Currently this issue seems to surface when SMSC is compiled for 64-bit ARMv8 platforms, so the change is protected under CONFIG_ARM64, so that it doesn't break other existing platforms. In addition this patch tries to fix some checkpatch errors and warnings (others related to camel-casing and volatile usage will be addressed by a later patch). This fix has been tested on both ARMv8 foundation model v1 and v2. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
* | | driver/ddr: Add 256 byte interleaving supportYork Sun2014-02-21-2/+20
| | | | | | | | | | | | | | | | | | | | | Freescale LayerScape SoCs support controller interleaving on 256 byte size. This interleaving is mandoratory. Signed-off-by: York Sun <yorksun@freescale.com>
* | | Driver/ddr: Add support of different DDR base addressYork Sun2014-02-21-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | DDR base address has been the same from the view of core and DDR controllers. This has changed for Freescale ARM-based SoCs. Controllers setup DDR memory in a contiguous space and cores view it at separated locations. Signed-off-by: York Sun <yorksun@freescale.com>
* | | driver/ddr: Change Freescale ARM DDR driver to support both big and little ↵York Sun2014-02-21-59/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | endian Initially it was believed the DDR controller on Freescale ARM would have big endian. But some platform will have little endian. Signed-off-by: York Sun <yorksun@freescale.com>
* | | serial: arc: Convert to use default_serial_putsAxel Lin2014-02-21-7/+1
| | | | | | | | | | | | | | | | | | Use default_serial_puts() instead of duplicating the implementation. Signed-off-by: Axel Lin <axel.lin@ingics.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2014-02-21-8/+42
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| * | | spi: ti_qspi: Add delay before xfer for am43xxSourav Poddar2014-02-18-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without this delay, write/read is failing. Looks like, the WIP always remain set and hence a timeout occurs leading to the error. Without this patch, device does not get probed also. Here is the log. U-Boot# U-Boot# U-Boot# U-Boot# sf probe 0 SF: Unsupported flash IDs: manuf ff, jedec ffff, ext_jedec ffff Failed to initialize SPI flash at 0:0 U-Boot# sf probe 0 While with this patch, log is U-Boot# sf probe 0 SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB, mapped at 30000000 U-Boot# sf erase 0 0x80000 SF: 524288 bytes @ 0x0 Erased: OK U-Boot# mw 81000000 0xdededede 0x40000 U-Boot# sf write 81000000 0 0x40000 SF: 262144 bytes @ 0x0 Written: OK U-Boot# sf read 82000000 0 0x40000 SF: 262144 bytes @ 0x0 Read: OK U-Boot# md 0x82000000 Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | spi: ti_qspi: Add AM43xx specifics changesSourav Poddar2014-02-18-3/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add AM43xx specific changes. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | spi: spi-mxc: implement clk control for ECSPI to fix SPI_MODE_3Markus Niebel2014-02-18-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPI_MODE_3 requires clk high when inactive. The SCLK_CTL field of the config reg was not configured in case of CPOL. Fix configuration so that SPI_MODE_3 which uses CPOL configures the clk line to be high in inactive state. Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | spi: xilinx: Move timeout calculation out of the loopMichal Simek2014-02-18-3/+5
| |/ / | | | | | | | | | | | | | | | | | | | | | Timeout calculation should be out of the data loop. This patch increase spi bandwidth for 30%. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* | | serial/serial_arc: switch from {read|write}l to {read|write}b accessorsAlexey Brodkin2014-02-21-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is required for proper functionality on big-endian targets. Memory-mapped registres of ARC UART are not 32-bit words but 8-bit bytes so on little-endian target either acessor (_l or _b) works fine. On big-endian only _b accessors works as expected. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Noam Camus <noamc@ezchip.com> Cc: Tom Rini <trini@ti.com>
* | | serial/serial_arc: add work-around of ISS bugAlexey Brodkin2014-02-21-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Explanation is in in-lined comment. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Noam Camus <noamc@ezchip.com> Cc: Tom Rini <trini@ti.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-02-20-66491/+639
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| * | Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2014-02-20-11/+7
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: Makefile drivers/net/npe/Makefile These two conflicts arise from commit 0b2d3f20 ("ARM: NET: Remove the IXP NPE ethernet driver") and are resolved by deleting the drivers/net/npe/Makefile file and removing the CONFIG_IXP4XX_NPE line from Makefile.
| * \ \ Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-02-19-2/+613
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| | * \ \ Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic2014-02-11-1513/+1233
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| | * | | | NET: fec_mxc: fix MDIO clock prescaler calculationMarkus Niebel2014-02-11-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The prescaler value for MDC is calculated wrong for MX6S. Implement the same logic as linux here which handles ENET_MAC different then original FEC. Tested on a custom board with i.MX6S and 100MBit PHY Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
| | * | | | pci: mx6: Implement reset callbackMarek Vasut2014-02-11-3/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a callback so that a board can implement it's own specific routine to toggle the port's #PERST line or #define a GPIO to do so. Signed-off-by: Marek Vasut <marex@denx.de>
| | * | | | ARM: mx6: Add PCI express driverMarek Vasut2014-01-26-0/+566
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PCIe driver for the Freescale i.MX6 SoC . This driver operates the PCIe block in RC mode only, the EP mode is NOT supported. The driver is tested with the Intel e1000 NIC driver. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| * | | | | serial_zynq: Migrate to Zynq clock frameworkSoren Brinkmann2014-02-19-11/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove hard coded frequencies and use Zynq's clock framework to obtain the UART clock frequency. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | | net: zynq_gem: Calculate clock dividers dynamicallySoren Brinkmann2014-02-19-6/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove hard coded clock divider setting and use the Zynq clock framework to dynamically calculate appropriate dividers at run time. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | | net: zynq_gem: Move RCLK details out of driverSoren Brinkmann2014-02-19-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GEM driver should not need to know about Zynq specific details of RCLK related registers and bitfields in the SLCR. Move those details to the slcr driver. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | | zynq: serial: Simplify serial driver initializationMichal Simek2014-02-19-14/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define both serial uarts in the driver and return default uart based on board configuration. - Move baseaddresses to hardware.h - Define default baudrate and clock values Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | | Merge branch 'u-boot-pxa/master' into 'u-boot-arm/master'Albert ARIBAUD2014-02-19-66464/+0
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| | * | | | | ARM: serial: Remove the IXP UART driverMarek Vasut2014-02-06-133/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver is no longer used, remove it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Michael Schwingen <michael@schwingen.org> Cc: Tom Rini <trini@ti.com>
| | * | | | | ARM: NET: Remove the IXP NPE ethernet driverMarek Vasut2014-02-06-65938/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver is no longer used, remove it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Michael Schwingen <michael@schwingen.org> Cc: Tom Rini <trini@ti.com>
| | * | | | | ARM: PCI: Remove the IXP PCI driverMarek Vasut2014-02-06-352/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver is no longer used, remove it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Michael Schwingen <michael@schwingen.org> Cc: Tom Rini <trini@ti.com>
| | * | | | | ARM: USB: Remove the IXP EHCI driverMarek Vasut2014-02-06-38/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver is no longer used, remove it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Michael Schwingen <michael@schwingen.org> Cc: Tom Rini <trini@ti.com>
| | * | | | | ARM: IXP: Remove the IXP architecture supportMarek Vasut2014-02-06-3/+0
| | | |/ / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The architecture is unmaintained and dead, remove it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Michael Schwingen <michael@schwingen.org> Cc: Tom Rini <trini@ti.com>
* | | | | | blackfin: Add <asm/clock.h> to numerous driversTom Rini2014-02-20-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With d6a320d we moved some clock externs out of blackfin_local.h and into clock.h but now need to include <asm/clock.h> in more drivers to avoid warnings. Cc: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Tom Rini <trini@ti.com>
* | | | | | dfu: mmc: fs: Fix format accepted by ext4write commandLukasz Majewski2014-02-20-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit: "EXT4: Fix number base handling of "ext4write" command" SHA1: f7740f7712b8638f08b83a7e5d00bc1d6bb086a9 Cleaned up the ext4write command format. This commit shall be regarded as a follow up, since the DFU subsystem is using those commands for its normal operation. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
* | | | | | designware_i2c: remove inclusion of <asm/arch/hardware.h>Alexey Brodkin2014-02-20-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As soon as all boards have their CONFIG_SYS_I2C_BASE defined in configuration files instead of "asm/arch/hardware.h" it's safe to remove the inclusion in question and make driver platform-independent. Cc: Tom Rini <trini@ti.com> Cc: Heiko Schocher <hs@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vipin Kumar <vipin.kumar@st.com> Cc: Armando Visconti <armando.visconti@st.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | | | | | OMAP24xx I2C: Add support for set-speedHannes Petermaier2014-02-20-50/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds support for set-speed on the OMAP24xx I2C Adapter. Changes to omap24_i2c_write(...) for polling ARDY Bit from IRQ-Status. Otherwise on a subsequent call the transfer of last byte from the predecessor is aborted and therefore lost. For exmaple when i2c_write(...) is followed by a i2c_setspeed(...) (which has to deactivate and activate master for changing psc,...). Minor cosmetical changes. Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at> Cc: Heiko Schocher <hs@denx.de>
* | | | | | i2c: i2c-mxs: Wait for I2C to empty queueMarek Vasut2014-02-20-7/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make sure the I2C write queue is empty before leaving the mxs_i2c_write(). If we start and I2C write and only wait for ACK, the MXS I2C IP block may enter next operation while still processing the write aftermath internally. This will in turn disrupt one or more subsequent transfer(s). A testcase for this issue is as such. This testcase is also interesting because the first I2C_WRITE which becomes disruptive happens in the 'i2c read' command. The 'i2c read' command first uses I2C_WRITE to send I2C address of the chip and then uses I2C_READ to read data from the chip. After this command completes, the 'i2c probe' will use sequence of I2C_WRITE commands to probe the I2C bus. The problem is that the first I2C_WRITE disrupted the I2C IP block operation and this sideeffect propagates all the way to this next I2C_WRITE used by the 'i2c probe' call. The result is the 'i2c probe' receives an ACK on I2C address 0x00, even if this ACK was owned by the previous I2C_WRITE operation. Note that the 'i2c read' command must read from a valid I2C chip address. Wrong: > i2c probe Valid chip addresses: 50 51 > i2c read 0x50 0x0.2 0x10 0x42000000 > i2c probe Valid chip addresses: 00 50 51 With this patch > i2c probe Valid chip addresses: 50 51 > i2c read 0x50 0x0.2 0x10 0x42000000 > i2c probe Valid chip addresses: 50 51 Signed-off-by: Marek Vasut <marex@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Fabio Estevam <festevam@gmail.com>
* | | | | | designware_i2c: Enhance DesignWare I2C driver address supportChin Liang See2014-02-20-32/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enhance the DesignWare I2C driver to support address length more than 1 byte. This enhancement is required as some I2C slave device such as EEPROM chip might have 16 bit address byte. Signed-off-by: Chin Liang See <clsee@altera.com> Acked-by: Alexey Brodkin <Alexey.Brodkin@synopsys.com> Cc: Tom Rini <trini@ti.com> cc: Armando Visconti <armando.visconti@st.com> Cc: Stefan Roese <sr@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Heiko Schocher <hs@denx.de>
* | | | | | i2c, bootcount: add support for bootcounter on i2c devicesHeiko Schocher2014-02-20-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add support for bootcounter on an i2c device. And add a README for all bootcounter options. Signed-off-by: Heiko Schocher <hs@denx.de>
* | | | | | blackfin: make i2c driver blackfin independantScott Jiang2014-02-20-71/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ADI twi peripheral is not binding to Blackfin processor only. Access i2c registers by standard io functions. Fix coding style. Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
* | | | | | blackfin: rename bfin-twi_i2c driver to adi_i2cSonic Zhang2014-02-20-0/+378
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ADI twi peripheral is not binding to Blackfin processor only. Change to a generic name. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
* | | | | | blackfin: add spi and i2c specific get clock functionsSonic Zhang2014-02-20-7/+10
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
generated by cgit v1.1 at 2024-12-19 01:22:44 +0000