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* x86: Drop the x86_fb driverSimon Glass2015-01-23-48/+0
| | | | | | | | Now that we have a full VESA driver we may as well use that. We need to support the VESA layer being set up by early start-up code or by running a VGA ROM. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add a VESA video driverSimon Glass2015-01-23-0/+75
| | | | | | | | | Add a driver intended to cope with any VESA-compatible x86 graphics adapter. It will not support ROMs which use OpenFirmware (Forth) since there is no support for that in U-Boot. This means that MAC OS cards will not work. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: pci: Don't stop when we get a vendor/device mismatchSimon Glass2015-01-23-1/+1
| | | | | | | These are quite common and we may as well press on and not be so picky. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* bios_emulator: Add some VESA interface debuggingSimon Glass2015-01-23-20/+141
| | | | | | Allow the supported modes to be listed when in debug mode. Signed-off-by: Simon Glass <sjg@chromium.org>
* bios_emulator: Don't display error when emulator terminatesSimon Glass2015-01-23-1/+1
| | | | | | As it turns out this is a normal condition, so suppress the error. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Support ROMs on other archsSimon Glass2015-01-23-0/+6
| | | | | | | | We shouldn't assume that the VGA ROM can always be loaded at c0000. This is only true on x86 machines. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Correct endianness isues in pci_romSimon Glass2015-01-23-11/+14
| | | | | | | | This code is too x86-dependent at present. Correct it so that it can run on big-endian machines. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* bios_emulator: Fix an #ifdef typo in the header fileSimon Glass2015-01-23-1/+1
| | | | | | | This stops the debug mode from working properly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* powerpc: mpc5xxx: remove Total5200 board supportMasahiro Yamada2015-01-23-13/+0
| | | | | | This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: ppc4xx: remove PPChameleonEVB, CATcenter boardsMasahiro Yamada2015-01-23-5/+0
| | | | | | | | | | | These boards are still non-generic boards. It is a good thing that we can drop board-specific hack code from drivers/mtd/nand/nand_base.c Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Stefan Roese <sr@denx.de> Cc: Andrea "llandre" Marson <andrea.marson@dave-tech.it>
* Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2015-01-23-20/+993
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| * sunxi: video: Make pwm polarity configurableHans de Goede2015-01-23-6/+11
| | | | | | | | | | | | | | | | It turns out that there are some panels where the pwm input is not active low, so make it configurable. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: video: Add support for Hitachi tx18d42vm LVDS LCD panelsHans de Goede2015-01-23-0/+5
| | | | | | | | | | | | | | | | | | | | Add support for Hitachi tx18d42vm LVDS LCD panels, these panels have a lcd controller which needs to be initialized over SPI, once that is done they work like a regular LVDS panel. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Anatolij Gustschin <agust@denx.de> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * video: Add support for Hitachi tx18d42vm LVDS LCD panelsHans de Goede2015-01-22-3/+103
| | | | | | | | | | | | | | | | | | Add support for Hitachi tx18d42vm LVDS LCD panels, these panels have a lcd controller which needs to be initialized over SPI, once that is done they work like a regular LVDS panel. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Anatolij Gustschin <agust@denx.de>
| * sunxi: video: Use frontend for dma on sun4i to fix memory bandwidth problemsHans de Goede2015-01-22-4/+130
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Testing has shown that on sun4i the display backend engine does not have deep enough fifo-s causing flickering / tearing in full-hd mode due to fifo underruns. On sun4i use the display frontend engine to do the dma from memory, as the frontend does have deep enough fifo-s. As added advantage of this is that it results in much better memory bandwidth as it reduces the amount of dram bank switches, for more details see: http://ssvb.github.io/2014/11/11/revisiting-fullhd-x11-desktop-performance-of-the-allwinner-a10.html Note that this changes the pipeline searched for in the simplefb node, we can get away with doing this now, since no kernel has yet shipped with simplefb dtb nodes, and I will make sure to get a simplefb node with the new pipeline into 3.19 before it ships. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * video: ssd2828: Allow using 'pclk' as the PLL clock sourceSiarhei Siamashka2015-01-22-7/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of using the internal 'tx_clk' clock source, it is also possible to use the pixel clock signal from the parallel LCD interface ('pclk') as the reference clock for PLL. The 'tx_clk' clock speed may be different on different boards/devices (the allowed range is 8MHz - 30MHz). Which is not very convenient, especially considering the need to know the exact 'tx_clk' clock speed. This clock speed may be difficult to identify without having device schematics and/or accurate documentation/sources every time. Using 'pclk' is free from all these problems. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Anatolij Gustschin <agust@denx.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * video: sunxi: Hook up SSD2828 with the sunxi video driverSiarhei Siamashka2015-01-22-0/+38
| | | | | | | | | | | | | | | | | | | | Convert GPIO names from Kconfig strings into pin numbers for the 'ssd2828_config' struct. Add SSD2828 initialization between enabling the parallel LCD interface and turning on the backlight. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * video: Add support for SSD2828 (parallel LCD to MIPI bridge)Siarhei Siamashka2015-01-22-0/+616
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SSD2828 can take pixel data coming from a parallel LCD interface and translate it on the fly into MIPI DSI interface for driving a MIPI compatible TFT display. SSD2828 is configured over SPI interface, which may or may not have MISO pin wired up on some hardware. So a write-only SPI mode also has to be supported. The SSD2828 support code is implemented as a utility function and needs to be called from real display drivers, which are responsible for driving parallel LCD hardware in front of the video pipeline. The usage instructions are provided as comments in the header file. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Anatolij Gustschin <agust@denx.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: axp221: Add ELDO[1-3] supportSiarhei Siamashka2015-01-22-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | And also add Kconfig option for selecting ELDO3 voltage. The reason for having this option is that the Android kernel sets ELDO3 to 1.2V when powering up LCD in the case if 'lcd_if' configuration variable is set to 6 (LCD_IF_EXT_DSI) in the FEX file. Most likely to supply power for a SSD2828 chip. However on the MSI Primo81 tablet, which is using this particular 'lcd_if = 6' setup for LCD, setting the ELDO3 voltage appears to be unnecessary and it works regardless. Having no schematics of this tablet, I can only guess that 1.2V is supplied to SSD2828 in some other way. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: axp209: Disable interrupts when intializing the axp209Hans de Goede2015-01-22-1/+13
| | | | | | | | | | | | | | | | | | | | We do not use the axp209 interrupt, and at least in my mini-x (which does not have a power button) the pwr-button pin and the irq pin are soldered together, so if the axp209 keeps it irq asserted too long it will see a 10s pwr-button press and hard power off the board, disabling the irqs fixes this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: mmc: Add support for sun9i (A80)Hans de Goede2015-01-22-2/+14
| | | | | | | | | | | | | | The clocks on the A80 are hooked up slightly different, add support for this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: mmc: Use a realistic timeout when sending a mmc commandHans de Goede2015-01-22-1/+1
| | | | | | | | | | | | | | | | Wait 1 second for the sdcard to respond, rather then waiting for 0xfffff milliseconds. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: display: Make lcd display clk phase configurableHans de Goede2015-01-22-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While running some tests with an Olinuxino-A13-Micro + a 7" Olimex LCD module I noticed that the screen flickered. This is caused by the lcd display clk phase reg value being set to 0, where it should be 1 in this setup. This commit adds a Kconfig option for the lcd display clk phase, so that we can set it per board. This defaults to 1, because looking at all the fex files in sunxi-boards, that is by far the most used value. This commit updated the Ippo and MSI Primo73 tablet defconfigs to override the default of 1 with 0, as that is the correct value for those tablets, this keeps the register settings the same as before this commit. The Olinuxino-A13 defconfigs are not updated, changing the register setting for these boards from 0 to 1, this is intentional. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2015-01-22-13/+678
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| * | net/vsc9953: Add driver for Vitesse VSC9953 L2 Switch IPCodrin Ciubotariu2015-01-16-0/+498
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a driver for VSC9953 L2 Switch. This Vitesse IP is integrated in Freescale T1040 and T1020 SoCs. The L2 switch has 10 Ethernet ports: 2 internal fixed-links (ports 8 and 9) at 2.5 Gbps and and 8 external ports at 1 Gbps. The external ports may be connected to PHYs over QSGMII and SGMII. Commands have also been added to enable/disable a port and to check a port's link speed, duplexity and status. The commands are: ethsw port <port_nr> enable|disable - enable/disable an l2 switch port ethsw port <port_nr> show - show an l2 switch port's configuration port_nr=0..9; use "all" for all ports For more detailse please see doc/README.t1040-l2switch Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | net/fm: Enable FMAN ports if l2switch ports are connected over SGMIICodrin Ciubotariu2015-01-16-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If SerDes is configured to connect L2 Switch ports from T1040 over SGMII or QSGMII, the two FMAN fixed ports (FM1@DTSEC1 and FM2@DTSEC2) that are connected to two L2 swtch ports must be enabled. These ports don't have PHYs and must be treated accordingly. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | net/fm: Fix error when FMAN MAC has no PHYCodrin Ciubotariu2015-01-16-12/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-boot assumes that all FMAN ports have a PHY. Some SoCs (like T1040) have fixed links. This means that the ports are connected MAC to MAc and there is no Ethernet PHY attatched. This patch initializes a FMAN MAC even if it doesn't have a PHY attached. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | phylib: add support for aquantia PHYsShaohui Xie2015-01-16-0/+160
| | | | | | | | | | | | | | | | | | | | | | | | This patch supports AQ1202, AQ2104, AQR105 PHY. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | Merge branch 'phys_t' of git://www.denx.de/git/u-boot-microblazeTom Rini2015-01-22-5/+6
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| * | | mmc: zynq: Use phys_addr_t for addressesMichal Simek2015-01-21-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | phys_addr_t is designed for physical addresses that's why use it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | net: ll_temac: Fix compilation warning because of phys_addr_tMichal Simek2015-01-21-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fix the compilation warning w+../drivers/net/xilinx_ll_temac.c: In function 'll_temac_init': w+../drivers/net/xilinx_ll_temac.c:235:3: warning: format '%X' expects argument of type 'unsigned int', but argument 4 has type 'phys_addr_t' [-Wformat] introduced by "net: Declare physical address as phys_addr_t unsigned type" (sha1: 16ae7827226ce8b255245d1932e8069f00997a26). Reported-by: Tom Rini <trini@ti.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | net: gem: Use phys_addr_t instead of int for addressesMichal Simek2015-01-21-2/+3
| | |/ | |/| | | | | | | | | | | | | | | | Use phys_addr_t for physical address declaration. It is also unsigned type instead of sign. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | Merge branch 'fpga' of git://www.denx.de/git/u-boot-microblazeTom Rini2015-01-22-5/+19
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| * | fpga: xilinx: Show fpga info if definedMichal Simek2015-01-21-4/+5
| | | | | | | | | | | | | | | | | | | | | Show fpga_op->info even if desc->iface_fns is not defined. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | fpga: xilinx: Check if fpga operations are definedMichal Simek2015-01-21-2/+15
| | | | | | | | | | | | | | | | | | | | | Ensure that operations are correctly setup. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | fpga: Export fpga_get_desc for SPLMichal Simek2015-01-21-1/+1
| | | | | | | | | | | | | | | | | | | | | SPL needs to detect FPGA device which will be used for loading bitstream. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mmcTom Rini2015-01-20-25/+987
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| * | | mmc: Skip changing bus width for MMC cards earlier than version 4.0Andrew Gabbasov2015-01-19-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Wider bus widths (larger than default 1 bit) appeared in MMC standard version 4.0. So, for MMC cards of any earlier version trying to change the bus width (including ext_csd comparison) does not make any sense. It may work incorrectly and at least cause unnecessary timeouts. So, just skip the entire bus width related activity for earlier versions. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com> Tested-by: Alexey Brodkin <abrodkin@synopsys.com>
| * | | mmc: Avoid redundant switching to 1-bit bus width for MMC cardsAndrew Gabbasov2015-01-19-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If all the commands switching an MMC card to 4- or 8-bit bus width fail, and the bus width for the controller and the driver is still set to default 1 bit, there is no need to send one more command to switch the card to 1-bit bus width. Also, if the card or host controller do not support wider bus widths, there is no need to send a switch command at all. However, if one of switch commands succeeds, but the subsequent ext_csd fields comparison fails, the card should be switched to some other bus width (next in the list for the loop), or to default 1-bit bus width as a last resort. That's why it would be incorrect to just remove the 1-bit bus width case from the list, it should still be processed in some cases. panto: Minor cosmetic edit removing superfluous parentheses. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com> Tested-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
| * | | mmc: extend mmcinfo output to show partition write reliability settingsDiego Santa Cruz2015-01-19-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This extends the mmcinfo hardware partition info output to show partitions with write reliability enabled with the "WRREL" string. If the partition does not have write reliability enabled the "WRREL" string is omitted; this is analogous to the ehhanced attribute. Example output: Device: OMAP SD/MMC Manufacturer ID: fe OEM: 14e Name: MMC16 Tran Speed: 52000000 Rd Block Len: 512 MMC version 4.41 High Capacity: Yes Capacity: 13.8 GiB Bus Width: 4-bit Erase Group Size: 8 MiB HC WP Group Size: 16 MiB User Capacity: 13.8 GiB ENH WRREL User Enhanced Start: 0 Bytes User Enhanced Size: 512 MiB Boot Capacity: 16 MiB ENH RPMB Capacity: 128 KiB ENH GP1 Capacity: 64 MiB ENH WRREL GP2 Capacity: 64 MiB ENH WRREL Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
| * | | mmc: extend the mmc hardware partitioning API with write reliabilityDiego Santa Cruz2015-01-19-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The eMMC partition write reliability settings are to be set while partitioning a device, as per the eMMC spec, so changes to these attributes needs to be done in the hardware partitioning API. This commit adds such support. Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
| * | | mmc: add API to do eMMC hardware partitioningDiego Santa Cruz2015-01-19-0/+155
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds an API to do hardware partitioning on eMMC devices. The new mmc_hwpart_config() function does the partitioning in one go. As the different attributes and partitioning options on eMMC may be interdependent validation has to be done based on the complete partitioning configuration. The function accepts three modes: - MMC_HWPART_CONF_CHECK: just validates that the configuration is valid. - MMC_HWPART_CONF_SET: validates and sets all the fields in EXT_CSD but without setting the "partitioning completed" bit, and thus is reversible. - MMC_HWPART_CONF_COMPLETE: does everything and is thus not reversible. Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
| * | | mmc: the ext_csd data may be used during init even if reading failedDiego Santa Cruz2015-01-19-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mmc_startup() function uses the ext_csd data even if reading it from the mmc device failed. This bug was introduced in commit bc897b1d4d86597311430dbe7b3e6c807c8c53e5. We now bail out if reading it fails, this should not be a problem as ext_csd was introduced in MMC 4.0 and this code is conditional on MMC >= 4.0. Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
| * | | mmc: eMMC partitioning data is not effective till partitioning completedDiego Santa Cruz2015-01-19-23/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The eMMC spec says that partitioning is only effective after the PARTITION_SETTING_COMPLETED is set in EXT_CSD (and a power cycle was done, but that we cannot know). Thus the partition sizes and attributes should be ignored when that bit is not set, otherwise the various capacities are not coherent (e.g., the user data capacity will be that of the unpartitioned device while partition sizes would be non-zero). Prescence of non-zero partitioning data is nevertheless still used to activate the high-capacity size definitions (EXT_CSD_ERASE_GROUP_DEF) as it is necessary to set that to write any of the partitioning fields in EXT_CSD, so having partitioning data means someone previously activated that and we should keep it activated. Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
| * | | mmc: read the high capacity WP group size for eMMCDiego Santa Cruz2015-01-19-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Read the eMMC high capacity write protect group size at mmc device initialization. This is useful to correctly partition an eMMC device, as partitions need to be aligned to this size. Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
| * | | mmc: fix erase_grp_size computation with high-capacity size definitionDiego Santa Cruz2015-01-19-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The erase_grp_size in struct mmc is to be a size in 512-byte sectors but the code used to compute it for eMMC when EXT_CSD_ERASE_GROUP_DEF is enabled computed it as bytes, leading to erase sizes and alignment much larger than what is actually required by the mmc device. Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
| * | | mmc: read the size of eMMC enhanced user data areaDiego Santa Cruz2015-01-19-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This modification reads the size of the eMMC enhanced user data area upon initialization of an mmc device, it will be used later by mmcinfo. Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
| * | | mmc: computation of eMMC GP partition size was missing 512 KiB factorDiego Santa Cruz2015-01-19-0/+1
| | | | | | | | | | | | | | | | Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
| * | | mmc: incomplete test to switch to high-capacity group size definitionsDiego Santa Cruz2015-01-19-22/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The eMMC spec mandates that the high-capacity group size definitions should be enabled when the device is partitioned (by setting ERASE_GROUP_DEF in EXT_CSD). The current test to determine when this is required misses a few cases. In particular a device may have been partitioned without setting the enhanced attribute on any partition or partitioning may be completed without creating any extra partitions. This change moves the code to set ERASE_GROUP_DEF to after reading all partition information. It is also enabled when PARTITIONING_SETTING_COMPLETED is set as it is necessary to enable ERASE_GROUP_DEF before setting that bit, so it means that the user previously switched to the high capacity definitions. Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
| * | | mmc: extend mmcinfo to show enhanced partition attributeDiego Santa Cruz2015-01-19-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This extends the mmcinfo command's output to show which eMMC partitions have the enhanced attribute set. Note that the eMMC spec says that if the enhanced attribute is supported then the boot and RPMB partitions are of the enhanced type. The output of mmcinfo becomes: Device: OMAP SD/MMC Manufacturer ID: fe OEM: 14e Name: MMC16 Tran Speed: 52000000 Rd Block Len: 512 MMC version 4.41 High Capacity: Yes Capacity: 13.8 GiB Bus Width: 4-bit User Capacity: 13.8 GiB ENH Boot Capacity: 16 MiB ENH RPMB Capacity: 128 KiB ENH GP1 Capacity: 64 MiB ENH GP2 Capacity: 64 MiB ENH Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
generated by cgit v1.1 at 2024-12-19 03:43:53 +0000