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* fpga: zynqpl: Clean partial bitstream handlingMichal Simek2014-05-20-12/+6
| | | | | | | | Do not do partial bitstream detection based on bitstream size and use bitstream_type argument which is passed from the fpga core. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* fpga: Define bitstream type based on command selectionMichal Simek2014-05-20-12/+19
| | | | | | | | | | Clean up partial, full and compressed bitstream handling. U-Boot supports full bitstream loading and partial based on detection which is not 100% correct. Extending fpga_load/fpga_loadbitstream() with one more argument which stores bitstream type. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-05-16-7/+63
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| * drivers/usb : Define usb control register mask for w1c bitsNikhil Badola2014-05-16-5/+10
| | | | | | | | | | | | | | | | | | | | Define and use CONTROL_REGISTER_W1C_MASK to make sure that w1c bits of usb control register do not get reset while writing any other bit Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * fsl/pci: Add workaround for erratum A-005434Chunhe Lan2014-05-16-2/+7
| | | | | | | | | | | | | | | | | | | | By default, all PEX inbound windows PEX_PEXIWARn[TRGT] are mapped to 0xF, which is local memory. But for BSC9132, 0xF is CCSR, 0x0 is local memory. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * net: phy/vitesse: Add support for VSC8664 phy moduleChunhe Lan2014-05-16-0/+46
| | | | | | | | | | | | | | | | This patch adds support for VSC8664 PHY module which can be found on Freescale's T4240RDB boards. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | mvtwsi: Remove unnecessary twsi_baud_rate and twsi_slave_address globalsHans de Goede2014-05-14-19/+4
| | | | | | | | | | | | | | | | | | These are used only once, so their is no need to have them global. This also stops mvtwsi from using any bss vars making it easier to use before dram init (to talk to the pmic to set the dram voltage). Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | mvtwsi: Fix clock programmingHans de Goede2014-05-14-5/+2
|/ | | | | | | | | | | | | | | | The TWSI_FREQUENCY macro was wrong in 2 ways: 1) It was casting the result of the calculations to an u8, while i2c clk rates are often >= 100Khz which won't fit in a u8, drop the cast. 2) It had an extra factor of 2 in the divider which neither the datasheet nor the Linux driver have. The comment for the default value was wrongly saying that m lives in bits 4-7, while in reality it is in bits 3-6, as can be seen from the correct shift by 3 used in i2c_init(). While at it remove the unused twsi_actual_speed variable. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-05-13-8/+12
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| * qe: disable qe when qe-ucode fails to be uploaded for "deep sleep"Zhao Qiang2014-05-13-1/+8
| | | | | | | | | | | | | | | | when qe-ucode fails to be uploaded, "deep sleep" will hang. if there is no qe-ucode, disable qe module for platforms which support "deep sleep" Signed-off-by: Zhao Qiang <B45475@freescale.com>
| * powerpc/85xx: add T4080 SoC supportShengzhou Liu2014-05-13-0/+1
| | | | | | | | | | | | | | | | The T4080 SoC is a low-power version of the T4160. T4080 combines 4 dual-threaded Power Architecture e6500 cores with single cluster and two memory complexes. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
| * powerpc/fman/memac: use default MDIO_HOLD valueShaohui Xie2014-05-13-6/+2
| | | | | | | | | | | | | | | | Current driver uses a Maximum value for MDIO_HOLD when doing 10G MDIO access, this is due to an errata A-006260 on T4 rev1.0 which is fixed on rev2.0, so remove the maximum value to use the default value for rev2.0. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
| * powerpc/85xx: Add T4240RDB board supportChunhe Lan2014-05-13-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T4240RDB board Specification ---------------------------- Memory subsystem: 6GB DDR3 128MB NOR flash 2GB NAND flash Ethernet: Eight 1G SGMII ports Four 10Gbps SFP+ ports PCIe: Two PCIe slots USB: Two USB2.0 Type A ports SDHC: One SD-card port SATA: One SATA port UART: Dual RJ45 ports Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> [York Sun: fix CONFIG_SYS_QE_FMAN_FW_ADDR in T4240RDB.h]
* | Merge branch 'fpga' of git://www.denx.de/git/u-boot-microblazeTom Rini2014-05-13-310/+235
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| * | fpga: zynq: Use helper function zynq_validate_bitstreamSiva Durga Prasad Paladugu2014-05-13-7/+25
| | | | | | | | | | | | | | | | | | | | | | | | Use helper function zynq_validate_bitstream so that the code can be reused easily for different cases of dma transfer. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | fpga: zynq: Use helper functions for zynq dmaSiva Durga Prasad Paladugu2014-05-13-86/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use zynq_dma_xfer_init, zynq_align_dma_buffer, zynq_dma_transfer helper function performing dma transfers so that the code can be reused easily for different cases of dma transfer. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | fpga: zynq: Remove sparse warningsMichal Simek2014-05-13-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Warnings: drivers/fpga/zynqpl.c:150:32: warning: Using plain integer as NULL pointer drivers/fpga/zynqpl.c:152:16: warning: Using plain integer as NULL pointer Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | fpga: xilinx: Simplify load/dump/info function handlingMichal Simek2014-05-13-165/+43
| | | | | | | | | | | | | | | | | | | | | | | | Connect FPGA version with appropriate operations to remove huge switch-cases for every FPGA family. Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | fpga: xilinx: Avoid CamelCase for in Xilinx_descMichal Simek2014-05-13-47/+47
| | | | | | | | | | | | | | | | | | No functional changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | fpga: virtex2: Avoid CamelCaseMichal Simek2014-05-13-24/+24
| | | | | | | | | | | | | | | | | | No functional changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | fpga: spartan3: Avoid CamelCaseMichal Simek2014-05-13-27/+27
| | | | | | | | | | | | | | | | | | No functional changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | fpga: spartan2: Avoid CamelCaseMichal Simek2014-05-13-27/+27
| |/ | | | | | | | | | | No functional changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini2014-05-13-4/+9
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| * at91: video: atmel_hlcdfb.c: fix bad timing configurationWu, Josh2014-05-05-4/+4
| | | | | | | | | | | | | | | | | | | | The right correspondance between LCD margins and LCD timings is: * upper margin -> vertical back porch * lower margin -> vertical front porch * left margin -> horizontal back porch * right margin -> horizontal front porch Signed-off-by: Josh Wu <josh.wu@atmel.com>
| * video: mxc_ipuv3_fb: stash frame buffer pointer in global data.Eric Nelson2014-04-30-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates the i.MX video driver to store the frame-buffer address in the fb_base field of the global data structure *gd. By doing this, you can find the frame buffer address using the 'bdinfo' command: U-Boot > bdinfo arch_number = 0x00000EB9 ... FB base = 0x4F35F1C0 This is very useful when debugging display connections. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Marek Vasut <marex@denx.de>
* | net/designware: call phy_connect_dev() to properly setup phylib deviceIan Campbell2014-05-12-0/+2
| | | | | | | | | | | | | | | | | | | | | | This sets up the linkage from the phydev back to the ethernet device. This symptom of not doing this which I noticed was: <NULL> Waiting for PHY auto negotiation to complete.... rather than: dwmac.1c50000 Waiting for PHY auto negotiation to complete.... Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Cc: Alexey Brodkin <Alexey.Brodkin@synopsys.com>
* | tps6586x: staticize funtionsManish Badarkhe2014-05-12-2/+2
| | | | | | | | | | | | Make funtions static which are locally used in file. Signed-off-by: Manish Badarkhe <badarkhe.manish@gmail.com>
* | net: rename and refactor eth_rand_ethaddr() functionMasahiro Yamada2014-05-12-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some functions in include/net.h are ported from include/linux/etherdevice.h of Linux Kernel. For ex. is_zero_ether_addr() is_multicast_ether_addr() is_broadcast_ether_addr() is_valid_ether_addr(); So, we should use the same function name as that of Linux Kernel, eth_rand_addr(), for consistency. Besides, eth_rand_addr() has been implemented as an inline function. So it should not be surrounded by #ifdef CONFIG_RANDOM_MACADDR. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net/phy: enable get_phy_id redefinableShengzhou Liu2014-05-12-1/+2
| | | | | | | | | | | | | | | | | | As some PHYs have non-standard PHY ID registers, PHY Id can't be read correctly by current get_phy_id function, so we enable get_phy_id redefinable to permit specific PHY driver having own specific get_phy_id function. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* | AR8035/phy: Enable autonegotiation function for ar8035Xiaobo Xie2014-05-12-3/+1
| | | | | | | | | | | | | | | | | | Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before, but used "if (phydev->supported & SUPPORTED_Autoneg)" now. So assign "phydev->supported" to "phydev->drv->features" for ar8035 to enable autonegotiation. Then removed the genphy_config_aneg() function. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
* | serial: nsl16550: add hw flow control supportKaricheri, Muralidharan2014-05-12-0/+6
| | | | | | | | | | | | | | | | keystone serial hw support hw flow control. This patch enables hw flow control for keystone EVMs as an optional feature based on CONFIG_SERIAL_HW_FLOW_CONTROL. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
* | bd_info: remove bi_barudrate member from struct bd_infoMasahiro Yamada2014-05-12-7/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gd->bd->bi_baudrate is a copy of gd->baudrate. Since baudrate is a common feature for all architectures, keep gd->baudrate only. It is true that bi_baudrate was passed to the kernel in that structure but it was a long time ago. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> Cc: Simon Glass <sjg@chromium.org> Cc: Wolfgang Denk <wd@denx.de> Cc: Heiko Schocher <hs@denx.de> Acked-by: Michal Simek <monstr@monstr.eu> (For microblaze)
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-05-09-213/+1224
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| * \ Merge branch 'u-boot/master'Albert ARIBAUD2014-05-09-3159/+2638
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/net/Makefile (trivial merge)
| * \ \ Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2014-04-21-204/+1194
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| | * | | keystone2: net: add keystone ethernet driverKaricheri, Muralidharan2014-04-17-0/+717
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ethernet driver configures the CPSW, SGMI and Phy and uses the the Navigator APIs. The driver supports 4 Ethernet ports and can work with only one port at a time. Port configurations are defined in board.c. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
| | * | | spi: davinci: add support for multiple bus and chip selectKaricheri, Muralidharan2014-04-17-3/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently davinci spi driver supports only bus 0 cs 0. This patch allows driver to support bus 1 and bus 2 with configurable number of chip selects. Also defaults are selected in a way to avoid regression on other platforms that uses davinci spi driver and has only one spi bus. Signed-off-by: Rex Chang <rchang@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| | * | | k2hk: add support for k2hk SOC and EVMVitaly Andrianov2014-04-17-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | k2hk EVM is based on Texas Instruments Keystone2 Hawking/Kepler SoC. Keystone2 SoC has ARM v7 Cortex-A15 MPCore processor. Please refer the ti/k2hk_evm/README for details on the board, build and other information. This patch add support for keystone architecture and k2hk evm. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: WingMan Kwok <w-kwok2@ti.com> Signed-off-by: Sandeep Nair <sandeep_n@ti.com>
| | * | | i2c, davinci: convert driver to new mutlibus/mutliadapter frameworkVitaly Andrianov2014-04-17-180/+250
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - add davinci driver to new multibus/multiadpater support - adapted all config files, which uses this driver Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Acked-by: Heiko Schocher <hs@denx.de>
| | * | | i2c, davinci: move i2c_defs.h to the drivers/i2c directoryKaricheri, Muralidharan2014-04-17-0/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves the davinci i2c_defs.h file to drivers.i2c directory. It will allow to reuse the davinci_i2c driver for TI Keystone2 SOCs. Not used "git mv" command to move the file because small part of it with definitions specific for Davinci SOCs has to remain in the arch/arm/include/asm/arch-davinci. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Acked-by: Tom Rini <trini@ti.com>
| | * | | NAND: DaVinci: allow forced disable of subpage writesKaricheri, Muralidharan2014-04-17-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a configurable mechanism to disable subpage writes in the DaVinci NAND driver. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Acked-by: Tom Rini <trini@ti.com>
| | * | | SPL:SPI: Add Falcon Mode supportTom Rini2014-04-17-6/+40
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
| | * | | spi: ti_qspi: Add delay for successful bulk erase.Poddar, Sourav2014-04-17-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bulk erase is not happening properly on dra7 due to erase timing constraints, add a delay so that erase timing constraints are properly met. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Yebio Mesfin <ymesfin@ti.com>
| | * | | mtd: Build nand_util.o for CONFIG_ENV_IS_IN_NAND in SPLTom Rini2014-04-17-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Tom Rini <trini@ti.com>
| | * | | mtd: Add a CONFIG_SPL_MTD_SUPPORT for a more full NAND subsystem in SPLTom Rini2014-04-17-27/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This mainly converts the am335x_spl_bch driver to the "normal" format which means a slight change to nand_info within the driver. Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Tom Rini <trini@ti.com>
| * | | | Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'Albert ARIBAUD2014-04-21-9/+29
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| | * | | | usb: tegra: combine header fileStefan Agner2014-04-17-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Combine the Tegra USB header file into one header file for all SoCs. Use ifdef to account for the difference, especially Tegra20 is quite different from newer SoCs. This avoids duplication, mainly for Tegra30 and newer devices. Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * | | | usb: tegra: fix PHY configurationStefan Agner2014-04-17-3/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Tegra30 and later, the PTS (parallel transceiver select) and STS (serial transceiver select) are part of the HOSTPC1_DEVLC_0 register rather than PORTSC1_0 register. Since the reset configuration usually matches the intended configuration, this error did not show up on Tegra30 devices. Also use the slightly different bit fields of first USB, (USBD) on Tegra20 and move those definitions to the Tegra20 specific header file. Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * | | | usb: tegra: fix USB2 powerdown for Tegra30 and laterStefan Agner2014-04-17-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clear the forced powerdown bit in the UTMIP_PLL_CFG2_0 register which brings USB2 in UTMI mode to work. This was clearly missing since the forced powerdown bit is set in reset by default for all USB ports. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * | | | ARM: tegra: Tegra20 pinmux cleanupStephen Warren2014-04-17-5/+5
| | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This renames all the Tegra20 pinmux pins and functions so they have a prefix which matches the type name. The entries in tegra20_pingroups[] are all updated to remove the columns which are no longer used. All affected code is updated to match. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
generated by cgit v1.1 at 2024-12-28 23:25:25 +0000