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* Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic2014-02-11-1513/+1233
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| * drivers: delete unused header filesMasahiro Yamada2014-01-24-1217/+0
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * esdhc: Detecting 8 bit width before mmc initializationHaijun.Zhang2014-01-22-0/+5
| | | | | | | | | | | | | | | | | | | | The upper 4 data signals of esdhc are shared with spi flash. So detect if the upper 4 pins are assigned to esdhc before enable sdhc 8 bit width. Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * esdhc: Workaround for card can't be detected on T4240QDSHaijun.Zhang2014-01-22-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Card detection pin is ineffective on T4240QDS Rev1.0. There are two cards can be connected to board. 1. eMMC card is built-in board, can not be removed. so For eMMC card it is always there. 2. Card detecting pin is functional for SDHC card in Rev2.0. This workaround force sdhc driver scan and initialize the card regardless of whether the card is inserted or not in case Rev1.0. Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * net/fm: revert commit 732dfe090d50af53bb682d0c8971784f8de1f90fShengzhou Liu2014-01-21-52/+1
| | | | | | | | | | | | | | | | This patch reverts patch 'add ft_fixup_xgec to support 3rd and 4th 10GEC'. When dual-role MAC acts as 10G,it still uses fsl,fman-port-1g-rx/tx as before. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
| * powerpc:mpc85xx: Add ifc nand boot support for TPL/SPLPo Liu2014-01-21-7/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using the TPL method for nand boot by sram was already supported. Here add some code for mpc85xx ifc nand boot. - For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec. - Use a clear function name for nand spl boot. - Add CONFIG_SPL_DRIVERS_MISC_SUPPORT to compile the fsl_ifc.c in spl/Makefile; Signed-off-by: Po Liu <Po.Liu@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc85xx: Revise workaround for DDR-A003York Sun2014-01-21-2/+67
| | | | | | | | | | | | | | | | | | | | | | | | Existing workaround only handles one RDIMM on reference design. In case of two RDIMMs being used, the workaround requires two separate writes to DDR_SDRAM_MD_CNTL register. This patch also restores two debug registers changed by the workaround. Signed-off-by: York Sun <yorksun@freescale.com> CC: Ben Collins <ben.c@servergy.com> CC: James Yang <James.Yang@freescale.com>
| * powerpc/t2080qds: some update for t2080qdsShengzhou Liu2014-01-21-4/+6
| | | | | | | | | | | | | | | | | | | | - add more serdes protocols support. - fix some serdes lanes route. - fix SGMII doesn't work and incorrect mdio display for XFI when serdes 0x6d. - correct boot location info for SD/SPI boot. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2014-01-20-5/+45
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| | * i2c: fti2c010: fix compiler warning on paddr[]Kuo-Jung Su2014-01-13-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the following compiler warnings: fti2c010.c: In function 'fti2c010_read': fti2c010.c:204:8: warning: 'paddr' may be used uninitialized in this function [-Wuninitialized] fti2c010.c: In function 'fti2c010_write': fti2c010.c:266:8: warning: 'paddr' may be used uninitialized in this function [-Wuninitialized] Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> Cc: Heiko Schocher <hs@denx.de>
| | * drivers/designware_i2c - add suppor of CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOWAlexey Brodkin2014-01-13-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we agreed on legacy implementation of "eeprom_{read|write}" (http://patchwork.ozlabs.org/patch/295825/) I had to fix/make it work again DesignWare I2C driver for cases when 1 EEPROM IC fake I2C with anumber of "built-in" ICs with different chip addresses. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Tom Rini <trini@ti.com> cc: Armando Visconti <armando.visconti@st.com> Cc: Stefan Roese <sr@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Heiko Schocher <hs@denx.de> Cc: Vipin KUMAR <vipin.kumar@st.com> Cc: Tom Rix <Tom.Rix@windriver.com> Cc: Mischa Jonker <mjonker@synopsys.com> Cc: Kuo-Jung Su <dantesu@faraday-tech.com>
| | * i2c: Fix i2c speed commandDarwin Rambo2014-01-13-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This corrects i2c core to interpret the value returned by i2c_set_bus_speed as a success indicator rather than the actual speed that was set. When i2c_set_bus_speed returns a failure code, the speed is unknown so the adapter speed is set to zero. Signed-off-by: Darwin Rambo <drambo@broadcom.com> Reviewed-by: Tim Kryger <tim.kryger@linaro.org> Reviewed-by: Steve Rae <srae@broadcom.com> Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| | * rcar_i2c: Clear status before start master receiveNobuhiro Iwamatsu2014-01-13-0/+2
| | | | | | | | | | | | | | | Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| | * rcar_i2c: Fix receiving wait conditionHisashi Nakamura2014-01-13-2/+2
| | | | | | | | | | | | | | | Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * | nand, gpmc: fix reading after switching eccJeroen Hofstee2014-01-17-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The omap_gpmc allows switching ecc at runtime. Since the NAND_SUBPAGE_READ flag is only set, it is kept when switching to hw ecc, which is not correct. This leads to calling chip->ecc.read_subpage which is not a valid pointer. Therefore clear the flag when switching ecc so reading in hw mode works again. Cc: Scott Wood <scottwood@freescale.com> Cc: Pekon Gupta <pekon@ti.com> Cc: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
| * | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-01-16-1/+2
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| * \ \ Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2014-01-14-2/+2
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| | * | | net: phy: atheros: Fix the masks for AR8031/8035Fabio Estevam2014-01-14-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the same masks as used in the kernel: https://git.kernel.org/cgit/linux/kernel/git/stable/linux-stable.git/tree/drivers/net/phy/at803x.c?id=refs/tags/v3.12.6 With such changes Ethernet is functional on hummingboard solo. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Marek Vasut <marex@denx.de> Patch: 306640
| * | | | mmc: dwmmc: mode change to 0644Minkyu Kang2014-01-14-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't know why but, file permission was changed Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | | fuelgauge: max17042: fix i2c read issue which causes infinity loop.Przemyslaw Marczak2014-01-14-34/+86
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issues: - reading i2c data by passing u16 pointer causes errors in read data. - max17042 status register fields have not only Power On Reset meaning so using proper mask is required. Changes: - read i2c data to type u32 instead of u16 - avoids buffer overflow - compare FG status register using mask not just one bit value - add checking return value to functions fg read/write - add model lock and model check count - add debug msg Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com>
| * | | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2014-01-13-188/+934
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| | * | | sf: params: Removed flag SECT_4K for Micron N25Q128Siva Durga Prasad Paladugu2014-01-12-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the flag SECT_4K for device N25Q128 as the 4K-byte sub sector erase granularity is available only for top/bottom 8 sectors in some of the N25Q128 chips. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| | * | | sf: Add CONFIG_SF_DUAL_FLASHJagannadha Sutradharudu Teki2014-01-12-5/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This config will use for defining greater than single flash support. currently - DUAL_STACKED and DUAL_PARALLEL. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| | * | | sf: Add dual memories support - DUAL_PARALLELJagannadha Sutradharudu Teki2014-01-12-7/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch added support for accessing dual memories in parallel connection with single chipselect line from controller. For more info - see doc/SPI/README.dual-flash Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| | * | | sf: Add dual memories support - DUAL_STACKEDJagannadha Sutradharudu Teki2014-01-12-11/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch added support for accessing dual memories in stacked connection with single chipselect line from controller. For more info - see doc/SPI/README.dual-flash Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| | * | | sf: ops: Unify read_ops bank configurationJagannadha Sutradharudu Teki2014-01-12-8/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unified the bar code from read_ops into a spi_flash_bar() Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| | * | | sf: Code cleanupsJagannadha Sutradharudu Teki2014-01-12-13/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - comment typo's - func args have a proper names Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| | * | | sf: Divide flash register ops from QEB codeJagannadha Sutradharudu Teki2014-01-11-53/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | QEB code comprises of couple of flash register read/write operations, this patch moved flash register operations on to sf_op Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| | * | | sf: probe: Enable macronix quad read/write cmds supportJagannadha Sutradharudu Teki2014-01-11-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added macronix flash quad read/write commands support and it's up to the respective controller driver usecase to configure the respective commands by defining SPI RX/TX operation modes from include/spi.h on the driver. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| | * | | sf: Add macronix set QEB supportJagannadha Sutradharudu Teki2014-01-11-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds set QEB support for macronix flash devices which are trying to program/read quad operations. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| | * | | sf: Discover read dummy_byteJagannadha Sutradharudu Teki2014-01-11-7/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Discovered the read dummy_byte based on the configured read command. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| | * | | sf: Add QUAD_IO_FAST read supportJagannadha Sutradharudu Teki2014-01-11-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support QUAD_IO_FAST read command. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| | * | | sf: Separate the flash params tableJagannadha Sutradharudu Teki2014-01-11-145/+135
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Moved the flash params table from sf_probe.c and placed on to sf_params.c, hence flash params file will alter based on new addons. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| | * | | sf: probe: Enable RD_FULL and WR_QPPJagannadha Sutradharudu Teki2014-01-11-30/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enabled RD_FULL and WR_QPP for supported flashes in micron, winbond and spansion. Remaining parts will be add in future patches. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| | * | | sf: Set quad enable bit supportJagannadha Sutradharudu Teki2014-01-11-2/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides support to set the quad enable bit on flash. quad enable bit needs to set before performing any quad IO operations on respective SPI flashes. Currently added set quad enable bit for winbond and spansion flash devices. stmicro flash doesn't require to set as qeb is volatile. remaining flash devices support will add in future patches. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| | * | | sf: ops: Add configuration register writing supportJagannadha Sutradharudu Teki2014-01-11-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides support to program a flash config register. Configuration register contains the control bits used to configure the different configurations and security features of a device. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| | * | | sf: Add quad read/write commands supportJagannadha Sutradharudu Teki2014-01-11-86/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add quad commands support like - QUAD_PAGE_PROGRAM => for write program - QUAD_OUTPUT_FAST ->> for read program Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| | * | | sf: Add extended read commands supportJagannadha Sutradharudu Teki2014-01-11-86/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current sf uses FAST_READ command, this patch adds support to use the different/extended read command. This implementation will determine the fastest command by taking the supported commands from the flash and the controller, controller is always been a priority. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| | * | | spi: sh_spi: Use sh_spi_clear_bit() instead of open-codedAxel Lin2014-01-11-8/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have a sh_spi_clear_bit() function, there's no reason not to use it. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| | * | | spi: Add Faraday SPI controller supportKuo-Jung Su2014-01-11-0/+509
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Faraday FTSSP010 is a multi-function controller which supports I2S/SPI/SSP/AC97/SPDIF. However This patch implements only the SPI mode. NOTE: The DMA and CS/Clock control logic has been altered since hardware revision 1.19.0. So this patch would first detects the revision id of the underlying chip, and then switch to the corresponding software control routines. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> CC: Tom Rini <trini@ti.com>
| * | | Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini2014-01-13-2/+2
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| | * | | video: ipu reg: Correct reserved array size in struct ipu_idmacLiu Ying2014-01-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The array reserved as a placeholder in the structure ipu_idmac should contain 44 32bit unsigned integer entries instead of 45 ones, because the placeholder is located bewteen the register IDMAC_SC_CORD1 and the register IDMAC_CH_BUSY_1 with the address offsets of 0x804c and 0x8100 respectively. Reported-by: Robin Gong <b38343@freescale.com> Acked-by: Robin Gong <b38343@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
| | * | | video: ipu reg: Correct reserved1 array size in struct ipu_cmLiu Ying2014-01-12-1/+1
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The array reserved1 as a placeholder in the structure ipu_cm should contain 4 32bit unsigned integer entries instead of 16 ones, because the placeholder is located bewteen the register IPU_CH_DB_MODE_SEL_1 and the register IPU_ALT_CH_DB_MODE_SEL_0 with the address offsets of 0x154 and 0x168 respectively. Reported-by: Robin Gong <b38343@freescale.com> Acked-by: Robin Gong <b38343@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
| * | | usb: exynos5: arndale: Add network supportInderpal Singh2014-01-13-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Arndale board has AX88760, which is USB 2.0 Hub & USB 2.0 Ethernet Combo controller, connected to HSIC Phy of USB host controller via USB3503 hub. This patch uses board specific board_usb_init function to perform reset sequence for USB3503 hub and enables the relevant config options for network to work. Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org> Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
| * | | usb: ehci: exynos: set/reset hsic physInderpal Singh2014-01-13-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The controller has 3 ports. The port0 is for USB 2.0 Phy, port1 and port2 are for HSIC phys. The usb 2.0 phy is already being setup. This patch sets up the hsic phys. Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
| * | | usb: gadget: fotg210: EP0 fifo empty indication is non-reliableKuo-Jung Su2014-01-13-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fifo size of ep0 is 64 bytes, and if the packet size grater than 64 bytes, the driver would have to fill up the fifo multiple times, and before filling up the fifo, the driver should make sure the fifo is empty by checking fifo empty indication. However there is a hardware bug that the fifo empty indication is somehow a bit earlier than fifo reset. So if I don't add an extra delay here, the data might be corrupted. (i.e., 1 byte missing) After a couple of tests, it truns out that 1 usec is good enough. This workaround should be applied to all hardware revisions. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> CC: Marek Vasut <marex@denx.de>
| * | | usb: gadget: fotg210: add w1c interrupt status supportKuo-Jung Su2014-01-13-0/+14
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since hardware revision 1.11.0, the following interrupt status registers are now W1C (i.e., write 1 clear): 1. Interrupt Source Group 0 Register (0x144) (EP0 Abort: BIT5) 2. Interrupt Source Group 2 Register (0x14C) (All bits) And before revision 1.11.0, these registers are all R/W. Which means software must write a 0 to clear the status. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> CC: Marek Vasut <marex@denx.de>
* | | NET: fec_mxc: fix MDIO clock prescaler calculationMarkus Niebel2014-02-11-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The prescaler value for MDC is calculated wrong for MX6S. Implement the same logic as linux here which handles ENET_MAC different then original FEC. Tested on a custom board with i.MX6S and 100MBit PHY Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
* | | pci: mx6: Implement reset callbackMarek Vasut2014-02-11-3/+44
| | | | | | | | | | | | | | | | | | | | | Add a callback so that a board can implement it's own specific routine to toggle the port's #PERST line or #define a GPIO to do so. Signed-off-by: Marek Vasut <marex@denx.de>
* | | ARM: mx6: Add PCI express driverMarek Vasut2014-01-26-0/+566
| |/ |/| | | | | | | | | | | | | | | | | | | | | Add PCIe driver for the Freescale i.MX6 SoC . This driver operates the PCIe block in RC mode only, the EP mode is NOT supported. The driver is tested with the Intel e1000 NIC driver. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
generated by cgit v1.1 at 2024-12-28 05:05:43 +0000