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* net: phy: atheros: Fix the masks for AR8031/8035Fabio Estevam2014-01-14-2/+2
| | | | | | | | | | | | | Use the same masks as used in the kernel: https://git.kernel.org/cgit/linux/kernel/git/stable/linux-stable.git/tree/drivers/net/phy/at803x.c?id=refs/tags/v3.12.6 With such changes Ethernet is functional on hummingboard solo. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Marek Vasut <marex@denx.de> Patch: 306640
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2014-01-13-188/+934
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| * sf: params: Removed flag SECT_4K for Micron N25Q128Siva Durga Prasad Paladugu2014-01-12-2/+2
| | | | | | | | | | | | | | | | | | Remove the flag SECT_4K for device N25Q128 as the 4K-byte sub sector erase granularity is available only for top/bottom 8 sectors in some of the N25Q128 chips. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sf: Add CONFIG_SF_DUAL_FLASHJagannadha Sutradharudu Teki2014-01-12-5/+14
| | | | | | | | | | | | | | This config will use for defining greater than single flash support. currently - DUAL_STACKED and DUAL_PARALLEL. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sf: Add dual memories support - DUAL_PARALLELJagannadha Sutradharudu Teki2014-01-12-7/+12
| | | | | | | | | | | | | | | | | | This patch added support for accessing dual memories in parallel connection with single chipselect line from controller. For more info - see doc/SPI/README.dual-flash Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sf: Add dual memories support - DUAL_STACKEDJagannadha Sutradharudu Teki2014-01-12-11/+57
| | | | | | | | | | | | | | | | | | This patch added support for accessing dual memories in stacked connection with single chipselect line from controller. For more info - see doc/SPI/README.dual-flash Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sf: ops: Unify read_ops bank configurationJagannadha Sutradharudu Teki2014-01-12-8/+5
| | | | | | | | | | | | Unified the bar code from read_ops into a spi_flash_bar() Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sf: Code cleanupsJagannadha Sutradharudu Teki2014-01-12-13/+8
| | | | | | | | | | | | | | - comment typo's - func args have a proper names Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sf: Divide flash register ops from QEB codeJagannadha Sutradharudu Teki2014-01-11-53/+77
| | | | | | | | | | | | | | QEB code comprises of couple of flash register read/write operations, this patch moved flash register operations on to sf_op Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sf: probe: Enable macronix quad read/write cmds supportJagannadha Sutradharudu Teki2014-01-11-4/+4
| | | | | | | | | | | | | | | | | | Added macronix flash quad read/write commands support and it's up to the respective controller driver usecase to configure the respective commands by defining SPI RX/TX operation modes from include/spi.h on the driver. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sf: Add macronix set QEB supportJagannadha Sutradharudu Teki2014-01-11-0/+35
| | | | | | | | | | | | | | This patch adds set QEB support for macronix flash devices which are trying to program/read quad operations. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sf: Discover read dummy_byteJagannadha Sutradharudu Teki2014-01-11-7/+30
| | | | | | | | | | | | | | Discovered the read dummy_byte based on the configured read command. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sf: Add QUAD_IO_FAST read supportJagannadha Sutradharudu Teki2014-01-11-0/+3
| | | | | | | | | | | | This patch adds support QUAD_IO_FAST read command. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sf: Separate the flash params tableJagannadha Sutradharudu Teki2014-01-11-145/+135
| | | | | | | | | | | | | | | | Moved the flash params table from sf_probe.c and placed on to sf_params.c, hence flash params file will alter based on new addons. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sf: probe: Enable RD_FULL and WR_QPPJagannadha Sutradharudu Teki2014-01-11-30/+30
| | | | | | | | | | | | | | | | | | This patch enabled RD_FULL and WR_QPP for supported flashes in micron, winbond and spansion. Remaining parts will be add in future patches. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sf: Set quad enable bit supportJagannadha Sutradharudu Teki2014-01-11-2/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides support to set the quad enable bit on flash. quad enable bit needs to set before performing any quad IO operations on respective SPI flashes. Currently added set quad enable bit for winbond and spansion flash devices. stmicro flash doesn't require to set as qeb is volatile. remaining flash devices support will add in future patches. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sf: ops: Add configuration register writing supportJagannadha Sutradharudu Teki2014-01-11-0/+24
| | | | | | | | | | | | | | | | | | This patch provides support to program a flash config register. Configuration register contains the control bits used to configure the different configurations and security features of a device. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sf: Add quad read/write commands supportJagannadha Sutradharudu Teki2014-01-11-86/+96
| | | | | | | | | | | | | | | | This patch add quad commands support like - QUAD_PAGE_PROGRAM => for write program - QUAD_OUTPUT_FAST ->> for read program Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sf: Add extended read commands supportJagannadha Sutradharudu Teki2014-01-11-86/+108
| | | | | | | | | | | | | | | | | | | | | | Current sf uses FAST_READ command, this patch adds support to use the different/extended read command. This implementation will determine the fastest command by taking the supported commands from the flash and the controller, controller is always been a priority. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * spi: sh_spi: Use sh_spi_clear_bit() instead of open-codedAxel Lin2014-01-11-8/+2
| | | | | | | | | | | | | | | | We have a sh_spi_clear_bit() function, there's no reason not to use it. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * spi: Add Faraday SPI controller supportKuo-Jung Su2014-01-11-0/+509
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Faraday FTSSP010 is a multi-function controller which supports I2S/SPI/SSP/AC97/SPDIF. However This patch implements only the SPI mode. NOTE: The DMA and CS/Clock control logic has been altered since hardware revision 1.19.0. So this patch would first detects the revision id of the underlying chip, and then switch to the corresponding software control routines. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> CC: Tom Rini <trini@ti.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini2014-01-13-2/+2
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| * | video: ipu reg: Correct reserved array size in struct ipu_idmacLiu Ying2014-01-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The array reserved as a placeholder in the structure ipu_idmac should contain 44 32bit unsigned integer entries instead of 45 ones, because the placeholder is located bewteen the register IDMAC_SC_CORD1 and the register IDMAC_CH_BUSY_1 with the address offsets of 0x804c and 0x8100 respectively. Reported-by: Robin Gong <b38343@freescale.com> Acked-by: Robin Gong <b38343@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
| * | video: ipu reg: Correct reserved1 array size in struct ipu_cmLiu Ying2014-01-12-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | The array reserved1 as a placeholder in the structure ipu_cm should contain 4 32bit unsigned integer entries instead of 16 ones, because the placeholder is located bewteen the register IPU_CH_DB_MODE_SEL_1 and the register IPU_ALT_CH_DB_MODE_SEL_0 with the address offsets of 0x154 and 0x168 respectively. Reported-by: Robin Gong <b38343@freescale.com> Acked-by: Robin Gong <b38343@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* | usb: exynos5: arndale: Add network supportInderpal Singh2014-01-13-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Arndale board has AX88760, which is USB 2.0 Hub & USB 2.0 Ethernet Combo controller, connected to HSIC Phy of USB host controller via USB3503 hub. This patch uses board specific board_usb_init function to perform reset sequence for USB3503 hub and enables the relevant config options for network to work. Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org> Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
* | usb: ehci: exynos: set/reset hsic physInderpal Singh2014-01-13-0/+39
| | | | | | | | | | | | | | | | The controller has 3 ports. The port0 is for USB 2.0 Phy, port1 and port2 are for HSIC phys. The usb 2.0 phy is already being setup. This patch sets up the hsic phys. Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
* | usb: gadget: fotg210: EP0 fifo empty indication is non-reliableKuo-Jung Su2014-01-13-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fifo size of ep0 is 64 bytes, and if the packet size grater than 64 bytes, the driver would have to fill up the fifo multiple times, and before filling up the fifo, the driver should make sure the fifo is empty by checking fifo empty indication. However there is a hardware bug that the fifo empty indication is somehow a bit earlier than fifo reset. So if I don't add an extra delay here, the data might be corrupted. (i.e., 1 byte missing) After a couple of tests, it truns out that 1 usec is good enough. This workaround should be applied to all hardware revisions. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> CC: Marek Vasut <marex@denx.de>
* | usb: gadget: fotg210: add w1c interrupt status supportKuo-Jung Su2014-01-13-0/+14
|/ | | | | | | | | | | | | | Since hardware revision 1.11.0, the following interrupt status registers are now W1C (i.e., write 1 clear): 1. Interrupt Source Group 0 Register (0x144) (EP0 Abort: BIT5) 2. Interrupt Source Group 2 Register (0x14C) (All bits) And before revision 1.11.0, these registers are all R/W. Which means software must write a 0 to clear the status. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> CC: Marek Vasut <marex@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-01-10-86/+121
|\ | | | | | | | | | | | | | | | | | | Bringing in the MMC tree means that CONFIG_BOUNCE_BUFFER needed to be added to include/configs/exynos5-dt.h now. Conflicts: include/configs/exynos5250-dt.h Signed-off-by: Tom Rini <trini@ti.com>
| * TI:omap3: Drop omap3_zoom2Tom Rini2014-01-07-3/+2
| | | | | | | | | | | | | | The omap3_zoom2 board has not been updated for a correct CONFIG_SYS_HZ and Tom Rix's email has long been bouncing. Signed-off-by: Tom Rini <trini@ti.com>
| * Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-01-06-83/+114
| |\ | | | | | | | | | | | | | | | | | | | | | Conflicts: include/micrel.h The conflict above was trivial, caused by four lines being added in both branches with different whitepace.
| | * arm: mx5: Add fuse supply enable in fsl_iimSergey Alyoshin2014-01-03-1/+12
| | | | | | | | | | | | | | | | | | | | | Enable fuse supply before fuse programming and disable after. Signed-off-by: Sergey Alyoshin <alyoshin.s@gmail.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| | * power: power_fsl: Pass p->bus in the same way for SPI and I2C casesFabio Estevam2013-11-27-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to pass p->bus differently when the PMIC is connected via SPI or via I2C. Handle the both cases in the same way. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * Net: FEC: Fix huge memory leakMarek Vasut2013-11-21-78/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fec_halt() never free'd both RX and TX DMA descriptors that were allocated in fec_init(), nor did it free the RX buffers. Rework the FEC driver so that these descriptors and buffers are allocated only once in fec_probe(). Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| | * mxs_gpio: fix the handling in gpio_direction_output()Michael Heimpold2013-11-13-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Setting the direction and an output value should be done by 1) set the desired output value, 2) switch to output. If this is done in the inverse order, there can be a glitch on the GPIO line. This patch fixes this by using the order as described above. Signed-off-by: Michael Heimpold <mhei@heimpold.de> Acked-by: Stefano Babic <sbabic@denx.de>
| * | i2c: tegra: Add the fifth bus on SoC with more than 4 busesAlban Bedel2013-12-18-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Create the i2c adapter object for the fifth bus on SoC with more than 4 buses. This allow using all the bus available on T30. Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mmcTom Rini2014-01-09-25/+130
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| * | | socfpga/dwmmc: Adding DesignWare MMC driver support for SOCFPGAChin Liang See2014-01-09-0/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To add the DesignWare MMC driver support for Altera SOCFPGA. It required information such as clocks and bus width from platform specific files (SOCFPGA handoff files) Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
| * | | mmc: add setdsr supportMarkus Niebel2014-01-09-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The eMMC and the SD-Card specifications describe the optional SET_DSR command. During measurements at our lab we found that some cards implementing this feature having really strong driver strengts per default. This can lead to voltage peaks above the specification of the host on signal edges for data sent from a card to the host. Since availability of a given card type may be shorter than the time a certain hardware will be produced it is useful to have support for this command (Alternative would be changing termination resistors and adapting the driver strength of the host to the used card.) Following proposal for an implementation: - new field that reflects CSD field DSR_IMP in struct mmc - new field for design specific DSR value in struct mmc - board code can set DSR value in mmc struct just after registering an controller - mmc_startup sends the the stored DSR value before selecting a card, if DSR_IMP is set Additionally the mmc command is extended to make is possible to play around with different DSR values. The concept was tested on a i.MX53 based platform using a Micron eMMC card where the default DSR is 0x0400 (12mA) but in our design 0x0100 (0x0100) were enough. To use this feature for instance on a mx53loco one have to add a call to mmc_set_dsr() in board_mmc_init() after calling fsl_esdhc_initialize() for the eMMC. Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
| * | | mmc: Minor cleanup of sdhci.cDarwin Rambo2014-01-09-13/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixup prints to show where the print is done from, and a few minor formatting/grammar issues. Signed-off-by: Darwin Rambo <drambo@broadcom.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
| * | | mmc/dwmmc: use bounce buffer for data exchange between CPU and MMC controllerAlexey Brodkin2014-01-09-10/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bounce buffer implementation takes care of proper data buffer alignemt and correct flush/invalidation of data cache at once so we no longer depend on input data variety and make sure CPU and MMC controller deal with expected data in case of enabled data cache. Bounce buffer requires to add its definition (CONFIG_BOUNCE_BUFFER) in board configuration, otherwise corresponding library won't be compiled and linker will fail to build resulting executable. Difference since v1 - fixed compile-time warning with type casting to "void *": Slight edit to remove UTF8 characters in the commit message. Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> ==== passing argument 2 of 'bounce_buffer_start' discards 'const' qualifier from pointer target type ==== Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Mischa Jonker <mjonker@synopsys.com> Cc: Alim Akhtar <alim.akhtar@samsung.com> Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Amar <amarendra.xt@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Andy Fleming <afleming@gmail.com>
| * | | mmc/dwmmc: Using calloc instead mallocChin Liang See2014-01-08-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To enhance the SDMMC DesignWare driver to use calloc instead of malloc. This will avoid the incident that uninitialized members of mmc structure are later used for NULL comparison. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Mischa Jonker <mjonker@synopsys.com> Cc: Alexey Brodkin <abrodkin@synopsys.com> Cc: Andy Fleming <afleming@freescale.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* | | | sandbox: tpm: Fix nvwrite commandChe-Liang Chiou2014-01-08-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original codes misused recvbuf in source buffer instead of sendbuf, and read from incorrect offset 14 instead of 22. Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Che-Liang Chiou <clchiou@chromium.org>
* | | | sandbox: tpm: Add TPM emulationSimon Glass2014-01-08-0/+263
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a simple TPM emulator for sandbox. It only supports a small subset of TPM operations. However, these are enough to perform common tasks. Note this is an initial commit to get this working, but it could use cleaning up (for example constants instead of open-coded values). Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | | sandbox: block driver using host file/device as backing storeHenrik Nordström2014-01-08-0/+125
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide a way to use any host file or device as a block device in U-Boot. This can be used to provide filesystem access within U-Boot to an ext2 image file on the host, for example. The support is plumbed into the filesystem and partition interfaces. We don't want to print a message in the driver every time we find a missing device. Pass the information back to the caller where a message can be printed if desired. Signed-off-by: Henrik Nordström <henrik@henriknordstrom.net> Signed-off-by: Simon Glass <sjg@chromium.org> - Removed change to part.c get_device_and_partition() Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | mtd: onenand: Fix unaligned accessMarek Vasut2013-12-31-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix unaligned access in OneNAND core. The problem is that the ffchars[] array is an array of "unsigned char", but in onenand_write_ops_nolock() can be passed to the memcpy_16() function. The memcpy_16() function will treat the buffer as an array of "unsigned short", thus triggering unaligned access if the compiler decided ffchars[] to be not aligned. I managed to trigger the problem with regular ELDK 5.4 GCC compiler. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Scott Wood <scottwood@freescale.com> Cc: Tom Rini <trini@ti.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2013-12-19-14/+294
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| * | | driver: mtd: sf_ops: claim bus while doing memcpyPoddar, Sourav2013-12-19-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | claim spi bus while doing memory copy, this will set up the spi controller device control register before doing a memory read. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Yebio Mesfin <ymesfin@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | spi: tegra: clear RDY bit prior to every transferYen Lin2013-12-19-13/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RDY bit indicates that a transfer is complete. This needs to be cleared by SW before every single HW transaction, rather than only at the start of each SW transaction (those being made up of n HW transactions). It seems that earlier HW may have cleared this bit autonomously when starting a new transfer, and hence this code was not needed in practice. However, this is generally a good idea in all cases. In Tegra124, the HW behaviour appears to have changed, and SW must explicitly clear this bit. Otherwise, SW will believe that transfers have completed when they have not, and may e.g. read stale data from the RX FIFO. Signed-off-by: Yen Lin <yelin@nvidia.com> [swarren, rewrote commit description, unified duplicate RDY clearing code and moved it right before the start of the HW transaction, unconditionally exit loop after reading RX data, rather than checking if TX FIFO is empty, since it is guaranteed to be] Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | spi: Add support SH Quad SPI driverNobuhiro Iwamatsu2013-12-18-0/+278
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a driver for Renesas SoC's Quad SPI bus. This supports with 8 bits per transfer to use with SPI flash. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
generated by cgit v1.1 at 2024-12-23 23:43:56 +0000