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* fm/mEMAC: add mEMAC frame workRoy Zang2012-10-22-2/+323
| | | | | | | | | | | The multirate ethernet media access controller (mEMAC) interfaces to 10Gbps and below Ethernet/IEEE 802.3 networks via either RGMII/RMII interfaces or XAUI/XFI/SGMII/QSGMII using the high-speed SerDes interface. Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: Add B4860 and variant SoCsYork Sun2012-10-22-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Freescale B4860 and variant SoCs. Features of B4860 are (incomplete list): Six fully-programmable StarCore SC3900 FVP subsystems, divided into three clusters-each core runs up to 1.2 GHz, with an architecture highly optimized for wireless base station applications Four dual-thread e6500 Power Architecture processors organized in one cluster-each core runs up to 1.8 GHz Two DDR3/3L controllers for high-speed, industry-standard memory interface each runs at up to 1866.67 MHz MAPLE-B3 hardware acceleration-for forward error correction schemes including Turbo or Viterbi decoding, Turbo encoding and rate matching, MIMO MMSE equalization scheme, matrix operations, CRC insertion and check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration, and UMTS chip rate acceleration CoreNet fabric that fully supports coherency using MESI protocol between the e6500 cores, SC3900 FVP cores, memories and external interfaces. CoreNet fabric interconnect runs at 667 MHz and supports coherent and non-coherent out of order transactions with prioritization and bandwidth allocation amongst CoreNet endpoints. Data Path Acceleration Architecture, which includes the following: Frame Manager (FMan), which supports in-line packet parsing and general classification to enable policing and QoS-based packet distribution Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading of queue management, task management, load distribution, flow ordering, buffer management, and allocation tasks from the cores Security engine (SEC 5.3)-crypto-acceleration for protocols such as IPsec, SSL, and 802.16 RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and outbound). Supports types 5, 6 (outbound only) Large internal cache memory with snooping and stashing capabilities for bandwidth saving and high utilization of processor elements. The 9856-Kbyte internal memory space includes the following: 32 Kbyte L1 ICache per e6500/SC3900 core 32 Kbyte L1 DCache per e6500/SC3900 core 2048 Kbyte unified L2 cache for each SC3900 FVP cluster 2048 Kbyte unified L2 cache for the e6500 cluster Two 512 Kbyte shared L3 CoreNet platform caches (CPC) Sixteen 10-GHz SerDes lanes serving: Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total of up to 8 lanes Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue- less antenna connection Two 10-Gbit Ethernet controllers (10GEC) Six 1G/2.5-Gbit Ethernet controllers for network communications PCI Express controller Debug (Aurora) Two OCeaN DMAs Various system peripherals 182 32-bit timers Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: Add T4240 SoCYork Sun2012-10-22-5/+167
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Freescale T4240 SoC. Feature of T4240 are (incomplete list): 12 dual-threaded e6500 cores built on Power Architecture® technology Arranged as clusters of four cores sharing a 2 MB L2 cache. Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture v2.06-compliant) Three levels of instruction: user, supervisor, and hypervisor 1.5 MB CoreNet Platform Cache (CPC) Hierarchical interconnect fabric CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet end-points 1.6 Tbps coherent read bandwidth Queue Manager (QMan) fabric supporting packet-level queue management and quality of service scheduling Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Memory prefetch engine (PMan) Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: Packet parsing, classification, and distribution (Frame Manager 1.1) Queue management for scheduling, packet sequencing, and congestion management (Queue Manager 1.1) Hardware buffer management for buffer allocation and de-allocation (BMan 1.1) Cryptography acceleration (SEC 5.0) at up to 40 Gbps RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0) 32 SerDes lanes at up to 10.3125 GHz Ethernet interfaces Up to four 10 Gbps Ethernet MACs Up to sixteen 1 Gbps Ethernet MACs Maximum configuration of 4 x 10 GE + 8 x 1 GE High-speed peripheral interfaces Four PCI Express 2.0/3.0 controllers Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with Type 11 messaging and Type 9 data streaming support Interlaken look-aside interface for serial TCAM connection Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Four I2C controllers Four 2-pin or two 4-pin UARTs Integrated Flash controller supporting NAND and NOR flash Two eight-channel DMA engines Support for hardware virtualization and partitioning enforcement QorIQ Platform's Trust Architecture 1.1 Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* driver/pci: Fix compiling errorYork Sun2012-10-22-0/+4
| | | | | | | | Fix compiling error in case CONFIG_SYS_PCIE2_MEM_VIRT or CONFIG_SYS_PCIE3_MEM_VIRT not defined. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* fsl_pci: use 'Header Type' field to judge PCIE modeMinghuan Lian2012-10-22-14/+16
| | | | | | | | | | | The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is EP or RC mode. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2012-10-19-219/+2405
|\ | | | | | | | | | | | | Conflicts: drivers/serial/serial_lh7a40x.c Signed-off-by: Tom Rini <trini@ti.com>
| * dm: Move s3c24xx USB driver to a proper placeMarek Vasut2012-10-18-0/+2211
| | | | | | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marex@denx.de> Cc: David Müller <d.mueller@elsoft.ch> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: U-Boot DM <u-boot-dm@lists.denx.de>
| * dm: wdt: arm: Move tnetv107x into drivers/watchdog/Marek Vasut2012-10-18-0/+181
| | | | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marex@denx.de> Cc: Oliver Brown <obrown@adventnetworks.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: U-Boot DM <u-boot-dm@lists.denx.de>
| * Remove lh7a40x cpu and serial driverAlbert ARIBAUD2012-10-16-226/+13
| | | | | | | | | | | | | | Since commit 957731ed (ARM: remove broken "lpd7a40x" boards), lh7a40x cpu and serial driver have become unused. Remove them. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | input: Add ANSI 3.64 escape sequence generation.Hung-Te Lin2012-10-19-15/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | To support Non-ASCII keys (ex, Fn, PgUp/Dn, arrow keys, ...), we need to translate key code into escape sequence. (Updated by sjg@chromium.org to move away from a function to store keycodes, so we can easily record how many were sent. We now need to return this from input_send_keycodes() so we know whether keys were generated.) Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@ti.com>
* | input: Fix i8042 keyboard resetMarc Jones2012-10-19-5/+27
| | | | | | | | | | | | | | | | | | | | | | The i8042 keyboard reset was not checking the results of the output buffer after the reset command. This can jam up some KBC/keyboards. Also, remove a write to the wrong register and the CONFIG setting around the incorrect write. Signed-off-by: Marc Jones <marc.jones@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@ti.com>
* | input: i8042: Provide feature to disable keyboard before booting kernelLouis Yung-Chieh Lo2012-10-19-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The BIOS leaves the keyboard enabled during boot time so that any keystroke would interfere kernel driver initialization. Add a way to disable the keyboard to make sure no scancode will be generated during the boot time. Note that the keyboard will be re-enabled again after the kernel driver is up. This code can be called from the board functions. Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@ti.com>
* | input: Provide a board specific mechanism to decide whether to skip i8042 initGabe Black2012-10-19-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | This change adds a board overridable function which can be used to decide whether or not to initialize the i8042 keyboard controller. On systems where it isn't actually connected to anything, this can save a significant amount of boot time. On Stumpy, this saves about 200ms on boot. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@ti.com>
* | input: Use finer grain udelays while waitng for the i8042 keyboard buffer to ↵Gabe Black2012-10-19-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | empty On x86, the i8042 keyboard controller driver frequently waits for the keyboard input buffer to be empty to make sure the controller has had a chance to process the data it was given. The way the delay loop was structured, if the controller hadn't cleared the corresponding status bit immediately, it would wait 1ms before checking again. If the keyboard responded quickly but not instantly, the driver would still wait a full 1ms when perhaps 1us would have been sufficient. Because udelay is a busy wait anyway, this change decreases the delay between checks to 1us. Also, this change gets rid of a hardcoded 250ms delay. On Stumpy, this saves 100-150ms during boot. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@ti.com>
* | ColdFire: uart: fix build failure for missing header filesAlison Wang2012-10-19-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | The following commit introduces some build failures for ColdFire platform. commit abaef69fbe683197607febeb2cc619490aca2a10 Author: Marek Vasut <marex@denx.de> Date: Thu Sep 13 16:51:38 2012 +0200 Add the missed header files. Sign-off-by: Alison Wang <b18965@freescale.com>
* | m68k: net: Fix unused variable in mcfmii.cMarek Vasut2012-10-19-3/+1
| | | | | | | | | | | | | | | | | | | | | | The following warning was produced, fix it: mcfmii.c: In function 'mcffec_miiphy_write': mcfmii.c:318:8: warning: variable 'rdreg' set but not used [-Wunused-but-set-variable] Signed-off-by: Marek Vasut <marex@denx.de> Cc: "Jin Zhengxiong-R64188" <R64188@freescale.com> Cc: Jason Jin <jason.jin@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2012-10-17-35/+104
|\ \
| * | i2c: sh_i2c: use setbits/clrbits macroTetsuyuki Kobayashi2012-10-16-4/+4
| | | | | | | | | | | | | | | | | | | | | Use setbits/clrbits macro when read-modify-write register. Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Acked-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * | i2c: sh_i2c.c: check error in i2c_read and i2c_writeTetsuyuki Kobayashi2012-10-16-18/+32
| | | | | | | | | | | | | | | | | | | | | | | | Before this patch, i2c_{read,write} always returned 0. Check TACK in i2c_raw_{read,write} so that i2c_{read,write} return non-zero when error. Acked-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
| * | i2c: sh_i2c: enable i2c_probeTetsuyuki Kobayashi2012-10-16-5/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | Before this patch i2c_probe() always returned 0 and "i2c probe" command did not work properly. Modify i2c_set_addr() to check TACK when waiting DTE and make i2c_probe() call this function. Acked-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
| * | i2c: sh_i2c.c: support I2C2, I2C3 and I2C4Tetsuyuki Kobayashi2012-10-16-0/+15
| | | | | | | | | | | | | | | | | | | | | sh_i2c.c support I2C0 and I2C1. This patch extends it to I2C4. Acked-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
| * | i2c: sh_i2c.c: adjust for SH73A0Tetsuyuki Kobayashi2012-10-16-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Adjust i2c_raw_read() in sh_i2c.c to work for SH73A0. After this patch, "i2c md" and "i2c mw" command on U-Boot work properly on KZM-A9-GT board. Acked-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
| * | i2c: sh_i2c.c: correct BUSY bit define in ICSRTetsuyuki Kobayashi2012-10-16-1/+1
| | | | | | | | | | | | | | | | | | | | | Correct BUSY bit define in ICSR from (1<<3) to (1<<4). Acked-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
| * | i2c: sh_i2c.c: support iccl and icch extensionTetsuyuki Kobayashi2012-10-16-8/+22
| |/ | | | | | | | | | | | | | | R-mobile SoC (at least SH73A0) has extension bits to store 8th bit of iccl and icch. This patch add support for the extentin bits. Acked-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
* | kerneldoc: Annotate drivers/serial/serial.cMarek Vasut2012-10-17-0/+165
| | | | | | | | | | | | | | | | Add kerneldoc annotations into serial core. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tom Rini <trini@ti.com>
* | serial: Reorder get_current()Marek Vasut2012-10-17-9/+12
| | | | | | | | | | | | | | | | | | | | Reorder the get_current() function to make it a bit more readable. The code does not grow and there is minor change in the code logic, where dev != NULL is now checked in any case. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tom Rini <trini@ti.com>
* | serial: Reorder serial_assign()Marek Vasut2012-10-17-5/+6
| | | | | | | | | | | | | | | | | | | | Reorder serial_assign() function to get rid of the extra level of indentation. Also, adjust the return value to be -EINVAL instead of positive one to be more consistent. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tom Rini <trini@ti.com>
* | serial: Use default_serial_puts() in driversMarek Vasut2012-10-17-167/+22
| | | | | | | | | | | | | | | | | | | | Replace the in-place ad-hoc implementation of serial_puts() within the drivers with default_serial_puts() call. This cuts down on the code duplication quite a bit. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tom Rini <trini@ti.com>
* | serial: Implement default_serial_puts()Marek Vasut2012-10-17-0/+7
|/ | | | | | | | | | | | | | U-Boot contains a lot of duplicit implementations of serial_puts() call which just pipes single characters into the port in loop. Implement function that does this behavior into common code, so others can make easy use of it. This function is called default_serial_puts() and it's sole purpose is to call putc() in loop on the whole string passed to it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tom Rini <trini@ti.com>
* mx51: Fix USB PHY clocksBenoît Thébaudeau2012-10-15-1/+2
| | | | | | | | | | | | | | | The i.MX51 has a single USB PHY clock, while the i.MX53 has two. These 3 clocks have different clock gate control bit-fields. The existing code was correct only for i.MX53, so this patch fixes the i.MX51 use case. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Jana Rapava <fermata7@gmail.com> Cc: Wolfgang Grandegger <wg@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il>
* mx5: Use explicit clock gate namesBenoît Thébaudeau2012-10-15-1/+1
| | | | | | | | Use clock gate definitions having names showing clearly the gated clock instead of names giving only a register field index. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: Use MXC_I2C_CLK in imx i2c driverMatthias Weisser2012-10-15-2/+2
| | | | | | | | i2c didn't work on imx25 due to missing MXC_IPG_PERCLK. Now using MXC_I2C_CLK on all imx systems using i2c. Signed-off-by: Matthias Weisser <weisserm@arcor.de> Acked-by: Stefano Babic <sbabic@denx.de>
* i.MX6: provide functional names for CCM_CCGR0-CCGR6 bit fieldsEric Nelson2012-10-15-2/+8
| | | | | | | | | | | | | Add meaningful constants for each clock channels and use them for enabling and disabling i.MX6 clocks. Includes an update to enable/disable the IPU1 clock in drivers/video/ipu_common to remove IMX5x register access when used on i.MX6 as discussed in V1: http://patchwork.ozlabs.org/patch/185129/ Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* tegra: nand: add board pinmuxLucas Stach2012-10-15-1/+0
| | | | | | | | Boards may require a different pinmux setup for NAND than the default one. Add a way to call into board specific code to set this up. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Tegra20: Move some include files to arch-tegra for sharing with Tegra30Tom Warren2012-10-15-14/+12
| | | | | | | | | | | The move is pretty straight-forward. ap20.h and tegra20.h were renamed to ap.h and tegra.h. Some files remain in arch-tegra20 but 'include' a file in 'arch-tegra' with #defines & structs that will be common between T20 and T30 HW. HW-specific #defines, etc. stay in the 'arch-tegra20' 'root' file. All boards build OK w/MAKEALL -s tegra20. Checkpatch.pl runs clean. Seaboard works OK. Signed-off-by: Tom Warren <twarren@nvidia.com>
* input: Add debugging for key matrix key codesSimon Glass2012-10-15-0/+2
| | | | | | | | | These are read from the fdt - add a debug feature to display the mapping on start-up. See that we get debug output listing the keycodes Signed-off-by: Simon Glass <sjg@chromium.org>
* input: Allow key ghosting filter to be disabledSimon Glass2012-10-15-3/+8
| | | | | | | Some keyboards will not need a key ghosting filter, so make this feature optional. Signed-off-by: Simon Glass <sjg@chromium.org>
* input: Separate out keyboard repeat/delay from initSimon Glass2012-10-15-6/+12
| | | | | | | | | | | It is inconvenient to have to specify the keyboard repeat and delay at init time if it is not yet available, so move this into a separate function. Some drivers will want to do this when their keyboard init routine is actually called. Signed-off-by: Simon Glass <sjg@chromium.org>
* input: Correct key_matrix fdt decodingSimon Glass2012-10-15-4/+7
| | | | | | | | | Some issues with this were not addressed in the previous series. Fix up the binding decoding to deal with what is actually expected in the fdt. This corrects the broken keyboard on seaboard. Signed-off-by: Simon Glass <sjg@chromium.org>
* sata.h: Make all sata/ata drivers include <sata.h>Pavel Herrmann2012-10-15-16/+7
| | | | | | | | | | - block_dev_desc_t says that block_(read|write) take lbaint_t for blkcnt not ulong. - We also move the extern of sata_dev_desc into <sata.h> - Remove now duplicate declarations from driver-specific headers. Signed-off-by: Tom Rini <trini@ti.com> Signed-off-by: Pavel Herrmann <morpheus.ibis@gmail.com>
* sil_sata: Make sata_write() comply with <part.h>Tom Rini2012-10-15-3/+3
| | | | | | | sata_write() takes a const void as the last argument. Fixing this means we also need to make ata_low_level_rw_lba{28,48} also take a const void. Signed-off-by: Tom Rini <trini@ti.com>
* sata_dwc: Make sata_write() use const void, per <part.h>Tom Rini2012-10-15-1/+1
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* pata_bfin: Make sata_{read,write}() comply with <part.h>Tom Rini2012-10-15-2/+2
| | | | | | These functions take lbaint_t for blkcnt. Signed-off-by: Tom Rini <trini@ti.com>
* fsl_sata: Make sata_{read,write}() comply with <part.h>Tom Rini2012-10-15-4/+6
| | | | | | | | | - sata_write() takes a const void as the last argument. Fixing this means we also need to make ata_low_level_rw_lba{28,48} also take a const void. - Both sata_{read,write} take lbaint_t for blkcnt and ulong for blknr Signed-off-by: Tom Rini <trini@ti.com>
* dwc_ahsata: Make sata_write() comply with <part.h>Tom Rini2012-10-15-4/+4
| | | | | | | | sata_write() takes a const void as the last argument. Fixing this means we also need to make ata_low_level_rw_lba{28,48} also take a const void. Acked-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@ti.com>
* ata_piix: sata_write must take a const void argument.Tom Rini2012-10-15-2/+2
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* ata_piix: Fix checkpatch issuesTom Rini2012-10-15-267/+232
| | | | | | | | While in here also: - Switch to debug from custom PRINTF for debugging. - Use mdelay rather than custom msleep. Signed-off-by: Tom Rini <trini@ti.com>
* pxa25x: Add support for USB ethernet gadgetLukasz Dalek2012-10-15-0/+2222
| | | | | | | Add to pxa25x based devices support for USB ethernet gadget. This is a port of pxa25x UDC driver from Linux kernel. Signed-off-by: Lukasz Dalek <luk0104@gmail.com>
* usbether: Removed DEV_CONFIG_{CDC,SUBSET}Lukasz Dalek2012-10-15-45/+30
| | | | | | | Removed DEV_CONFIG_CDC and DEV_CONFIG_SUBSET and replaced it with CONFIG_USB_ETH_CDC and CONFIG_USB_ETH_SUBSET. Signed-off-by: Lukasz Dalek <luk0104@gmail.com>
* usbether: Define CONFIG_USB_ETH_{CDC,SUBSET}Lukasz Dalek2012-10-15-5/+14
| | | | | | | Introduced CONFIG_USB_ETH_CDC and CONFIG_USB_ETH_SUBSET as preparation for removal DEV_CONFIG_CDC and DEV_CONFIG_SUBSET Signed-off-by: Lukasz Dalek <luk0104@gmail.com>
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