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* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-04-15-915/+1948
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| * Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-04-14-5/+3
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| | * fsl_esdhc: Fix DMA transfer completion waiting loopAndrew Gabbasov2013-04-14-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rework the waiting for transfer completion loop condition to continue waiting until both Transfer Complete and DMA End interrupts occur. Checking of DLA bit in Present State register looks not needed in addition to interrupts status checking, so it can be removed from the condition. Also, DMA Error condition is added to the list of data errors, checked in the loop. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
| | * fsl_esdhc: flush cache after IO completionEric Nelson2013-04-14-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | The cache should invalidate the read buffer for the SD card interface after the transfer complete, not command-complete. Tested-by: Andrew Gabbasov <Andrew_Gabbasov@mentor.com> Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| * | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-04-14-8/+9
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| | * spi: mxc_spi: Set master mode for all channelsFabio Estevam2013-04-13-8/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The glitch in the SPI clock line, which commit 3cea335c34 (spi: mxc_spi: Fix spi clock glitch durant reset) solved, is back now and itwas re-introduced by commit d36b39bf0d (spi: mxc_spi: Fix ECSPI reset handling). Actually the glitch is happening due to always toggling between slave mode and master mode by configuring the CHANNEL_MODE bits in this reset function. Since the spi driver only supports master mode, set the mode for all channels always to master mode in order to have a stable, "glitch-free" SPI clock line. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-04-12-977/+2396
| |\ \ | | | | | | | | | | | | | | | | Conflicts: drivers/video/exynos_fb.c
| * | | kirkwood_nand: allow usage of NAND_ECC_SOFT_BCHGerlando Falauto2013-04-12-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_NAND_ECC_BCH is set use 4-bit error correction code instead of the 1-bit error correction code on the NAND device. Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com> cc: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Acked-by: Scott Wood <scottwood@freescale.com>
| * | | arm: Remove support for unused s3c64xxBenoît Thébaudeau2013-04-12-593/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Following the removal of the smdk6400 board, the s3c64xx SoC becomes unused, so remove associated code. It will still be possible to restore it later from the Git history if necessary. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * | | nand: mxc: Switch NAND SPL to generic SPLBenoît Thébaudeau2013-04-12-5/+597
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This also fixes support for mx31pdk and tx25, which had been broken by commit e05e5de7fae5bec79617e113916dac6631251156. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Scott Wood <scottwood@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | nand: mxc: Use appropriate page number in syndrome functionsBenoît Thébaudeau2013-04-12-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The syndrome functions should use the page number passed as argument instead of the page number saved upon NAND_CMD_READ0. This does not make any difference if the NAND_NO_AUTOINCR option is set, but otherwise this fixes accesses to the wrong pages. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Scott Wood <scottwood@freescale.com>
| * | | nand: mxc: Fix debug trace in mxc_nand_read_oob_syndrome()Benoît Thébaudeau2013-04-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The page number indicated in the debug trace of mxc_nand_read_oob_syndrome() did not match the page being worked on. By the way, replace the GCC-specific __FUNCTION__ with __func__. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Scott Wood <scottwood@freescale.com>
| * | | nand: mxc: Add support for i.MX5Benoît Thébaudeau2013-04-12-11/+108
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Scott Wood <scottwood@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | nand: mxc: Prepare to add support for i.MX5Benoît Thébaudeau2013-04-12-46/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add some abstraction to NFC definitions so that some parts of the current code can also be used for future i.MX5 code. Clean up a few things by the way. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Scott Wood <scottwood@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | mtd: nand: mxc_nand: Fix is_16bit_nand()Fabio Estevam2013-04-12-34/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently is_16bit_nand() is a per SoC function and it decides the bus nand width by reading some boot related registers. This method works when NAND is the boot medium, but does not work if another boot medium is used. For example: booting from a SD card and then using NAND to store the environment variables, would lead to the following error: NAND bus width 16 instead 8 bit No NAND device found!!! 0 MiB Use CONFIG_SYS_NAND_BUSWIDTH_16BIT symbol to decide the bus width. If it is defined in the board file, then consider 16-bit NAND bus-width, otherwise assume 8-bit NAND is used. This also aligns with Documentation/devicetree/bindings/mtd/nand.txt, which states: nand-bus-width : 8 or 16 bus width if not present 8 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * | | mtd: nand: Introduce CONFIG_SYS_NAND_BUSWIDTH_16BITFabio Estevam2013-04-12-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce CONFIG_SYS_NAND_BUSWIDTH_16BIT option so that other NAND controller drivers could use it when a 16-bit NAND is deployed. drivers/mtd/nand/ndfc has CONFIG_SYS_NDFC_16BIT, so just rename it, so that other NAND drivers could reuse the same symbol. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * | | omap_gpmc: add support for hw assisted BCH8Andreas Bießmann2013-04-08-91/+276
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The kernel states: ---8<--- The OMAP3 GPMC hardware BCH engine computes remainder polynomials, it does not provide automatic error location and correction: this step is implemented using the BCH library. --->8--- And we do so in u-boot. This implementation uses the same layout for BCH8 but it is fix. The current provided layout does only work with 64 Byte OOB. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Tom Rini <trini@ti.com> Cc: Ilya Yanok <ilya.yanok@cogentembedded.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Mansoor Ahamed <mansoor.ahamed@ti.com> Cc: Thomas Weber <thomas.weber.linux@googlemail.com>
| * | | omap_gpmc: change nandecc commandAndreas Bießmann2013-04-08-26/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With uppcoming BCH support on OMAP devices we need to decide between differnt algorithms when switching the ECC engine. Currently we support 1-bit hammign and 8-bit BCH on HW backend. In order to switch between differnet ECC algorithms we need to change the interface of omap_nand_switch_ecc() also. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Tom Rini <trini@ti.com> Cc: Thomas Weber <thomas.weber.linux@googlemail.com>
| * | | asm/omap_gpmc.h: consolidate common definesAndreas Bießmann2013-04-08-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | arch/arm/include/asm/arch-am33xx/omap_gpmc.h and arch/arm/include/asm/arch-omap3/omap_gpmc.h are almost the same, consolidate the common parts into a new header. Introduce a new asm/omap_gpmc.h which defines the command part and pulls in the architecture specific one. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Tom Rini <trini@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| * | | omap3_beagle: Flush UART3 xmit on enable if TEMT is brokenManfred Huber2013-04-08-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Flush UART3 xmit on enable if TEMT is broken On some OMAP3 devices when UART3 is configured for boot mode before SPL starts only THRE bit is set. We have to empty the transmitter before initialization starts. This patch avoids the use of CONFIG_SYS_NS16550_BROKEN_TEMT. Signed-off-by: Manfred Huber <man.huber@arcor.de> Tested-by: Javier Martinez Canillas <javier@dowhile0.org> Tested-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | | musb: set MUSB speed based on CONFIGBin Liu2013-04-08-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not config MUSB to highspeed mode if CONFIG_USB_GADGET_DUALSPEED is not set, in which case Ether gadget only operates in fullspeed. Reviewed-by: Tom Rini <trini@ti.com> Signed-off-by: Bin Liu <b-liu@ti.com>
| * | | musb: am335x: disable bulk split-combine featureBin Liu2013-04-08-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On TI AM335x devices, MUSB has bulk split/combine feature enabled in the ConfigData register, but the current MUSB driver does not support it yet. Therefore, disable the feature for now, until the driver adds the support. One usecase which is broken because of this feature is that Ether gadget stops working in Fullspeed mode (by un-defining CONFIG_USB_GADGET_DUALSPEED) After desabled this feature, MUSB driver send packets in proper size (no more than 64 bytes) in Fullspeed mode. This has been validated with Ether gadget in Fullspeed mode on AM335x EVM. Signed-off-by: Bin Liu <b-liu@ti.com>
| * | | Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2013-04-04-88/+832
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| | * | | Exynos: Add hardware accelerated SHA256 and SHA1Akshay Saraswat2013-03-29-0/+498
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SHA-256 and SHA-1 accelerated using ACE hardware. Signed-off-by: ARUN MANKUZHI <arun.m@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * | | spi: exynos: Fix compiler warnings for non-dt systemsVivek Gautam2013-03-29-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enclosing process_nodes() and spi_get_config() inside CONFIG_OF_CONTROL, since they are compiled only for DT systems. This fixes following warning: exynos_spi.c:391:12: warning: 'process_nodes' defined but not used [-Wunused-function] Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | | video: exynos_dp: Add function to parse DP DT nodeAjay Kumar2013-03-27-0/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add function to parse the required platform data fron DP DT node and fill the edp_info structure. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | | video: exynos_dp: Make dp_regs globalAjay Kumar2013-03-27-45/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dp_regs variable was redundantly defined across all the functions in the driver even though it contains just the same address. We make it global and initialize it once using exynos_dp_set_base_addr(). >From then on, other funtions can use the address stored in the global variable. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | | video: exynos_fb: add DT support for FIMD driverAjay Kumar2013-03-27-0/+180
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add function to parse FIMD data from device tree. The driver still supports non-DT case. Define panel_info statically in some file if you are not using DT. If you have defined DT node for FIMD, panel_info will be filled using the bindings of FIMD DT node. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | | video: exynos_fb: Make fimd_ctrl globalAjay Kumar2013-03-27-25/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fimd_ctrl variable was redundantly defined across all the functions in the driver even though it contains just the same address. We make it global and initialize it in exynos_fimd_lcd_init. From then on, other funtions can use the data in the global variable. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | | video: exynos_dp: Remove callbacks from the driverAjay Kumar2013-03-27-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replaced the functionality of callbacks by using a standard set of functions. Instead of implementing and hooking up a callback, put the same code in one of the standard set of functions by overriding it. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | | video: exynos_fb: Remove callbacks from the driverAjay Kumar2013-03-27-16/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replaced the functionality of callbacks by using a standard set of functions. Instead of implementing and hooking up a callback, put the same code in one of the standard set of functions by overriding it. This patch is tested only on SMDK5250. For Trats and universal_c210 board, it is only compile tested. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-04-04-4/+11
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| | * | | spi: mxc_spi: Fix ECSPI reset handlingDirk Behme2013-04-04-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reviewing the ECSPI reset handling shows two issues: 1. For the enable/reset bit (MXC_CSPICTRL_EN) in the control reg (ECSPIx_CONGREG) the i.MX6 technical reference manual states: -- cut -- ECSPIx_CONREG[0]: EN: Writing zero to this bit disables the block and resets the internal logic with the exception of the ECSPI_CONREG. -- cut -- Note the exception mentioned: The CONREG itself isn't reset. Fix this by manually writing the reset value 0 to the whole register. This sets the EN bit to zero, too (i.e. includes the old ~MXC_CSPICTRL_EN). 2. We want to reset the whole SPI block here. So it makes no sense to first read the old value of the CONREG and write it back, later. This will give us the old (historic/random) value of the CONREG back. And doesn't reset the CONREG. To get a clean CONREG after the reset of the block, too, don't use the old (historic/random) value of the CONREG while doing the reset. And read the clean CONREG after the reset. This was found while working on a SPI boot device where the i.MX6 boot ROM has already initialized the SPI block. The initialization by the boot ROM might be different to what the U-Boot driver wants to configure. I.e. we need a clean reset of SPI block, including the CONREG. Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com>
| | * | | mmc: i.MX6: fsl_esdhc: Define maximum bus width supported by a boardAbbas Raza2013-04-03-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Maximum bus width supported by some i.MX6 boards is not 8bit like others. In case where both host controller and card support 8bit transfers, they agree to communicate on 8bit interface while some boards support only 4bit interface. Due to this reason the mmc 8bit default mode fails on these boards. To rectify this, define maximum bus width supported by these boards (4bit). If max_bus_width is not defined, it is 0 by default and 8bit width support will be enabled in host capabilities otherwise host capabilities are modified accordingly. It is tested with a MMCplus card. Signed-off-by: Abbas Raza <Abbas_Raza@mentor.com> cc: stefano Babic <sbabic@denx.de> cc: Andy Fleming <afleming@gmail.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
| * | | | ARM: bcm2835: fix get_timer() to return msStephen Warren2013-04-04-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Apparently, CONFIG_SYS_HZ must be 1000. Change this, and fix the timer driver to conform to this. Have the timer implementation export a custom API get_timer_us() for use by the BCM2835 MMC API, which needs us resolution for a HW workaround. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* | | | | Merge branch 'tpm' of git://git.denx.de/u-boot-x86Tom Rini2013-04-15-5/+1416
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| * | | | | tpm: Add Infineon slb9635_i2c TPM driverRong Chang2013-04-12-0/+1411
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a driver for the I2C TPM from Infineon. Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> Signed-off-by: Rong Chang <rongchang@chromium.org> Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | | tpm: Add casts for proper compilationTaylor Hutt2013-04-12-5/+5
| | |_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When building for the Sandbox version, the casts in this change are necessary to avoid compilation issues. Signed-off-by: Taylor Hutt <thutt@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | | | Revert "mtd: cfi_flash: Fix CFI flash driver for 8-bit bus support"Stefan Roese2013-04-12-55/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 239cb9d904cfa8ab50d840a47b3306189d695c75. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | Revert "cfi_flash: Use uintptr_t for casts from u32 to void *"Stefan Roese2013-04-12-1/+1
|/ / / / | | | | | | | | | | | | | | | | | | | | This reverts commit 81a4f7098ba137ea1961cb997ca16d57de2b3483. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | ubi: ubifs: Turn off verbose printsJoe Hershberger2013-04-11-6/+12
| | | | | | | | | | | | | | | | | | | | | | | | The prints are out of control. SILENCE! Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* | | | ubi: Fix broken cleanup code in attach_by_scanningJoe Hershberger2013-04-11-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The unwind code was not reversing operations correctly and was causing a hang on any error condition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* | | | dfu: NAND specific routines for DFU operationPantelis Antoniou2013-04-10-0/+196
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support for NAND storage devices to work with the DFU framework. Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com> Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Scott Wood <scottwood@freescale.com>
* | | | nand: Extend nand_(read|write)_skip_bad with *actual and limit parametersTom Rini2013-04-10-8/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We make these two functions take a size_t pointer to how much space was used on NAND to read or write the buffer (when reads/writes happen) so that bad blocks can be accounted for. We also make them take an loff_t limit on how much data can be read or written. This means that we can now catch the case of when writing to a partition would exceed the partition size due to bad blocks. To do this we also need to make check_skip_len count not just complete blocks used but partial ones as well. All callers of nand_(read|write)_skip_bad are adjusted to call these with the most sensible limits available. The changes were started by Pantelis and finished by Tom. Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com> Signed-off-by: Tom Rini <trini@ti.com>
* | | | dfu: Support larger than memory transfers.Pantelis Antoniou2013-04-10-89/+262
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously we didn't support upload/download larger than available memory. This is pretty bad when you have to update your root filesystem for example. This patch removes that limitation (and the crashes when you transfered any file larger than 4MB) by making raw image writes be done in chunks and making file maximum size be configurable. The sequence number is a 16 bit counter; make sure we handle rollover correctly. This fixes the wrong transfers for large (> 256MB) images. Also utilize a variable to handle initialization, so that we don't rely on just the counter sent by the host. Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com> Signed-off-by: Tom Rini <trini@ti.com>
* | | | dfu:ext4:fix: Change ext4write command order of parametersŁukasz Majewski2013-04-08-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Following commit: "cmd_ext4: BREAK and correct ext4write parameter order" SHA1:0171d52c410cbaa9290b1b214e695697c835bfe5 introduced cleanup of ext4write semantics to be consistent with other filesystem's writing commands (e.g. fatwrite). This commit provides correct ext4write command generation at DFU eMMC code. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
* | | | Merge branch 'master' of git://www.denx.de/git/u-boot-cfi-flashTom Rini2013-04-04-23/+78
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| * | | | cfi_flash: Use uintptr_t for casts from u32 to void *Stefan Roese2013-04-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes this build warning: Configuring for qemu_mips64 - Board: qemu-mips64, Options: SYS_BIG_ENDIAN text data bss dec hex filename 215344 13082 218720 447146 6d2aa qemu_mips64/u-boot cfi_flash.c: In function 'flash_map': cfi_flash.c:217:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Signed-off-by: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@ti.com>
| * | | | mtd: cfi_flash: Write buffer size adjustment for M29EW Numonyx devicesJagannadha Sutradharudu Teki2013-04-02-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch addjusted the write buffer size for M29EW devices those are operated in 8-bit mode. The M29EW devices seem to report the CFI information wrong when it's in 8 bit mode. There's an app note from Numonyx on this issue and there's a patch in the open source as well for Linux, but it doesn't seem to be in mainline. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Tested-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | mtd: cfi_flash: Fix CFI flash driver for 8-bit bus supportaaron.williams@caviumnetworks.com2013-04-02-23/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit is based on that patch from aaron.williams@caviumnetworks.com with same commit title. pulled the same code changes into current u-boot tree. http://patchwork.ozlabs.org/patch/140863/ http://lists.denx.de/pipermail/u-boot/2011-April/089606.html This patch corrects the addresses used when working with Spansion/AMD FLASH chips. Addressing for 8 and 16 bits is almost identical except in the 16-bit case the LSB of the address is always 0. The confusion arose because the addresses in the datasheet for 16-bit mode are word addresses but this code assumed it was byte addresses. I have only been able to test this on our Octeon boards which use either an 8-bit or 16-bit bus. I have not tested the case where there's an 8-bit part on a 16-bit bus. This patch also adds some delays as suggested by Spansion. If a part can be both 8 and 16-bits, it forces it to work in 8-bit mode if an 8-bit bus is detected. Apart from the pulled changes, fixed few minor code cleanups and tested on 256M29EW, 512M29EW flashes. Before this fix: --------------- Bank # 1: CFI conformant flash (8 x 8) Size: 64 MB in 512 Sectors AMD Standard command set, Manufacturer ID: 0xFF, Device ID: 0xFF Erase timeout: 4096 ms, write timeout: 2 ms Buffer write timeout: 5 ms, buffer size: 1024 bytes After this fix: -------------- Bank # 1: CFI conformant flash (8 x 8) Size: 64 MB in 512 Sectors AMD Standard command set, Manufacturer ID: 0x89, Device ID: 0x7E2301 Erase timeout: 4096 ms, write timeout: 2 ms Buffer write timeout: 5 ms, buffer size: 1024 bytes Signed-off-by: Aaron Williams <aaron.williams@caviumnetworks.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Tested-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
generated by cgit v1.1 at 2024-12-23 08:19:12 +0000