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| | * sound: Move Samsung-specific code into its own fileSimon Glass2014-03-17-221/+210
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i2s code is in fact Samsung-specific, but there might be other implementation. Move this code into its own file. This makes it slightly more obviously how to adjust the code to support another SoC, when someone takes this task on. Also drop non-FDT support, since it isn't used on Exynos 5. Tested-by: Che-Liang Chiou <clchiou@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| | * sandbox: Add LCD driverSimon Glass2014-03-17-0/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a simple LCD driver which uses SDL to display the image. We update the image regularly, while still providing for reasonable performance. Adjust the common lcd code to support sandbox. For command-line runs we do not want the LCD to be displayed, so add a --show_lcd option to enable it. Tested-by: Che-Liang Chiou <clchiou@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| | * sandbox: Add a simple sound driverSimon Glass2014-03-17-0/+25
| | | | | | | | | | | | | | | | | | | | | Add a sound driver for sandbox, which uses SDL. Tested-by: Che-Liang Chiou <clchiou@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| | * cros_ec: Implement I2C pass-throughSimon Glass2014-03-17-2/+268
| | | | | | | | | | | | | | | | | | | | | | | | | | | The Chrome EC has a feature where you can access its I2C buses through a pass-through arrangement. Add a command to support this, and export the function for it also. Reviewed-by: Vadim Bendebury <vbendeb@google.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| | * cros_ec: sandbox: Add Chrome OS EC emulationSimon Glass2014-03-17-0/+576
| | | | | | | | | | | | | | | | | | | | | | | | Add a simple emulation of the Chrome OS EC for sandbox, so that it can perform various EC tasks such as keyboard handling. Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| | * cros_ec: Correct comparison between signed and unsigned numbersSimon Glass2014-03-17-16/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to signed/unsigned comparison, '< sizeof(struct)' does not do the right thing, since if ec_command() returns a -ve number we will consider this be success. Adjust all comparisons to avoid this problem. This error was found with sandbox, which gives a segfault in this case. On ARM we may instead silently fail. We should also consider turning on -Wsign-compare to catch this sort of thing in future. Reviewed-by: Andrew Chew <achew@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Andrew Chew <achew@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
| | * cros_ec: spi: Add support for EC protocol version 3Randall Spangler2014-03-17-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | Protocol version 3 will be attempted first; if the EC doesn't support it, u-boot will fall back to the old protocol version (2). Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| | * cros_ec: Add base support for protocol v3Simon Glass2014-03-17-1/+164
| | | | | | | | | | | | | | | | | | | | | Protocol v2 was shipped with snow, link and spring. Protocol v3 is for pit and is targetted at SPI operation. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * cros_ec: Clean up multiple EC protocol supportRandall Spangler2014-03-17-44/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Version 1 protocols (without command version) were already no longer supported in cros_ec.c. This removes some dead code from the cros_ec_i2c driver. Version 2 protcols (with command version) are now called protocol_version=2, instead of cmd_version_is_supported=1. A subsequent change will introduce protocol version 3 for SPI. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| | * cros_ec: Sync up with latest Chrome OS EC versionSimon Glass2014-03-17-16/+17
| | | | | | | | | | | | | | | | | | The EC messages have been expanded and some parts have been renamed. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * cros_ec: Move #ifdef to permit flash region accessSimon Glass2014-03-17-1/+2
| | | | | | | | | | | | | | | | | | | | | Flash region access is not tied to having commands, so adjust the #ifdef to reflect this. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * cros_ec: Support systems with no EC interruptSimon Glass2014-03-17-4/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some systems do not have an EC interrupt. Rather than assuming that the interrupt is always present, and hanging forever waiting for more input, handle the missing interrupt. This works by reading key scans only until we get an identical one. This means the EC keyscan FIFO is empty. Tested-by: Che-Liang Chiou <clchiou@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| | * cros_ec: Drop old EC version support from EC driverVadim Bendebury2014-03-17-89/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to support old style EC moving forward. Ultimately we should get rid of the check_version() API. For now just return error in case the EC does not seem to support the new API. Reviewed-by: Vadim Bendebury <vbendeb@google.com> Tested-by: Vadim Bendebury <vbendeb@google.com> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| | * cros_ec: Add a function for decoding the Chrome OS EC flashmapSimon Glass2014-03-17-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | In order to talk to the EC properly we need to be able to understand the layout of its internal flash memory. This permits emulation of the EC for sandbox, and also software update in a system with a real EC. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * mtd: spi: Fix page size for S25FL032P,S25FL064PMarek Vasut2014-03-17-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit 6af8dc3ebccb3b1e4b2e479315e49545e7f53150 broke support for S25FL032P and S25FL064P by carelessly removing the code handling special page size for these two SPI NOR flashes and unifying the code under the assumption that Extended JEDEC ID of 0x4d00 always implies 512b page size. Add special case handling for these two SPI NOR flashes. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| | * spi: atmel_dataflash: Simplify AT91F_SpiEnable implementationAxel Lin2014-03-17-19/+12
| | | | | | | | | | | | | | | | | | | | | | | | Refactor the code a bit to make it better in readability. Remove the comments because now the intention of the code is pretty clear. Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| | * sf: ops: Squash the malloc+memset comboJagannadha Sutradharudu Teki2014-03-17-2/+6
| | | | | | | | | | | | | | | | | | | | | Squash the malloc()+memset() combo in favor of calloc(). Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Acked-by: Marek Vasut <marex@denx.de>
| | * sf: Squash the malloc+memset comboMarek Vasut2014-03-17-2/+1
| | | | | | | | | | | | | | | | | | | | | Squash the malloc()+memset() combo in favor of calloc(). Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| | * sf: Add S25FL128S_256K IDsMarek Vasut2014-03-17-0/+1
| | | | | | | | | | | | | | | | | | | | | Add IDs for this new chip. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| | * sf: Fix entries for S25FL256S_256K and S25FL512S_256KMarek Vasut2014-03-17-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Both of these chips have 256kB big sectors, thus the _256K suffix, compared to their _64K counterparts, which have 64kB sectors. Also, they have four times less sectors than their _64K counterparts. Signed-off-by: Marek Vasut <marex@denx.de> Tested-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| | * usb: net: introduce support for Moschip USB ethernetGerhard Sittig2014-03-12-0/+820
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | introduce an 'mcs7830' driver for Moschip MCS7830 based (7730/7830/7832) USB 2.0 Ethernet Devices see "MCS7830 -- USB 2.0 to 10/100M Fast Ethernet Controller" at http://www.asix.com.tw/products.php?op=pItemdetail&PItemID=109;74;109 the driver was implemented based on the U-Boot Asix driver with additional information gathered from the Moschip Linux driver, development was done on "Delock 61147" and "Logilink UA0025C" dongles Signed-off-by: Gerhard Sittig <gsi@denx.de> Acked-by: Marek Vasut <marex@denx.de>
| * | Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2014-03-13-1/+242
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| | * | usb: dfu: add static alt num count in dfu_config_entities()Przemyslaw Marczak2014-03-13-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Thanks to this multiple call of function dfu_config_entities() gives continuous dfu alt numbering until call dfu_free_entities(). This allows to store dfu entities in multiple variables. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Łukasz Majewski <l.majewski@samsung.com> Tested-by: Heiko Schocher <hs@denx.de> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | drivers:mmc:sdhci: enable support for DTPiotr Wilczek2014-03-12-0/+129
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables support for device tree for sdhci driver. Non DT case is still supported. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | video:exynos_fb:fdt: add additional fdt dataPiotr Wilczek2014-03-12-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the new exynos_lcd_misc_init() function for optional lcd specific initialisation. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | video:mipidsim:fdt: Add DT support for mipi dsim driverPiotr Wilczek2014-03-12-0/+96
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | This patch enables parsing mipi data from device tree. Non device tree case is still supported. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-03-13-0/+33
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| * | | drivers: net: cpsw: init phy with gigabit featuresIlya Ledvich2014-03-12-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CPSW ia a gigabit device. Use the PHY_GBIT_FEATURES macro to determine phy supported features. Tested on cm_t335. Signed-off-by: Ilya Ledvich <ilya@compulab.co.il>
| * | | drivers/spi/omap3: Bug fix of premature write transfer completionVasili Galka2014-03-12-2/+3
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | The logic determining SPI "write" transfer completion was faulty. At certain conditions (e.g. slow SPI clock freq) the transfers were interrupted before completion. Both EOT and TXS flags of channel status registeer shall be checked to ensure that all data was transferred. Tested on AM3359 chip. Signed-off-by: Vasili Galka <vasili@visionmap.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-03-10-2/+210
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| | * | mtd: nand: atmel: prepare for nand spl boot supportBo Shen2014-03-09-0/+208
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prepare for nand spl boot support. It supports nand software ECC and hardware PMECC. This patch is take <drivers/mtd/nand/nand_spl_simple.c> as reference. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2014-03-10-487/+11
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| | * | | usb: create common header virtual root hub descriptorsStephen Warren2014-03-10-485/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many USB host controller drivers contain almost identical copies of the same virtual root hub descriptors. Put these into a common file to avoid duplication. Note that there were some very minor differences between the descriptors in the various files, such as: - USB 1.0 vs. USB 1.1 - Manufacturer/Device ID - Max packet size - String content I assume these aren't relevant. Cc: Thomas Lange <thomas@corelatus.se> Cc: Shinya Kuribayashi <skuribay@pobox.com> Cc: Gary Jennejohn <garyj@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Eric Millbrandt <emillbrandt@coldhaus.com> Cc: Pierre Aubert <p.aubert@staubli.com> Cc: Stefan Roese <sr@denx.de> Cc: Daniel Hellstrom <daniel@gaisler.com> Cc: Denis Peter <d.peter@mpl.ch> Cc: Rodolfo Giometti <giometti@linux.it> Cc: Zhang Wei <wei.zhang@freescale.com> Cc: Mateusz Zalega <m.zalega@samsung.com> Cc: Remy Bohmer <linux@bohmer.net> Cc: Markus Klotzbuecher <mk@denx.de> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Gary Jennejohn <garyj@denx.de> Cc: C Nauman <cnauman@diagraph.com> Cc: David Müller <d.mueller@elsoft.ch> Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Thomas Abraham <t-abraham@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Andrew Murray <amurray@embedded-bits.co.uk> Cc: Matej Frančeškin <matej.franceskin@comtrade.com> Cc: Cliff Cai <cliff.cai@analog.com> Cc: Bryan Wu <cooloney@gmail.com> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
| | * | | usb: ehci: fully align interrupt QHs/QTDsStephen Warren2014-03-10-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These data structures are passed to cache-flushing routines, and hence must be conform to both the USB the cache-flusing alignment requirements. That means aligning to USB_DMA_MINALIGN. This is important on systems where cache lines are >32 bytes. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * | | ush: ehci: initialize altnext pointers in QHStephen Warren2014-03-10-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Section 4.10.2 "Advance Queue" of ehci-specification-for-usb.pdf specifies how an EHCI controller loads a new QTD for processing if the QH is not already marked as active. It states: ===== If the field Bytes to Transfer is not zero and the T-bit in the Alternate Next qTD Pointer is set to zero, then the host controller uses the Alternate Next qTD Pointer. Otherwise, the host controller uses the Next qTD Pointer. If Next qTD Pointer’s T-bit is set to a one, then the host controller exits this state and uses the horizontal pointer to the next schedule data structure. ===== Hence, we must ensure that the alternate next QTD pointer's T-bit (TERMINATE) is set, so the EHCI controller knows to use the next QTD pointer. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | cfb_console: align fields in gzipped .bmp filesEric Nelson2014-03-10-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | .bmp files contain 32-bit integers aligned at offsets of +2, +6, et cetera within the bmp_header structure (see include/bmp_layout.h). Support for gzip-compressed .bmp files is present in the cfb_console display subsystem by uncompressing them prior to use. This patch forces the in-memory header to be aligned properly for these compressed images by extracting them to a 2-byte offset in the memory returned by malloc. Since malloc will always return a 4-byte aligned value, this forces the .bmp header fields to be naturally aligned on 4-byte addresses. Refer to these files for more details: doc/README.displaying-bmps Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| * | | | ahci: wait longer for link.Ian Campbell2014-03-10-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I have observed timeouts on a cubietruck. The increase to 40ms is completely arbitrary and Works For Me(tm). I couldn't find a good reference for how long you are supposed to wait, although googling around it seems like tens of ms rather than single digits is more common. I don't think there is any harm in waiting a bit longer. Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
| * | | | ahci-plat: Provide a weak scsi_init hookIan Campbell2014-03-10-0/+5
| |/ / / | | | | | | | | | | | | | | | | | | | | This allow the platform to register the platform ahci device. Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
| * | | ppc4xx: Remove 4xx NAND booting supportStefan Roese2014-03-07-13/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As ppc4xx currently only supports the deprecated nand_spl infrastructure and nobody seems to have time / resources to port this over to the newer SPL infrastructure, lets remove NAND booting completely. This should not affect the "normal", non NAND-booting ppc4xx platforms that are currently supported. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Tirumala Marri <tmarri@apm.com> Cc: Matthias Fuchs <matthias.fuchs@esd.eu> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> Tested-by: Matthias Fuchs <matthias.fuchs@esd.eu>
| * | | net/phy: Correct AR8021 phy_maskHaijun.Zhang2014-03-07-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There was wrong phy_mask for AR8021 device, so the AR8021 can't be probed correctly. Changed it from 0x4fffff to 0x4ffff0. Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
| * | | net: asix: don't pad odd-length TX packetsStephen Warren2014-03-07-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For Ethernet/USB RX packets, the ASIX HW pads odd-sized packets so that they have an even size. Currently, asix_recv() does remove this padding, and asic_send() adds equivalent padding in the TX path. However, the HW does not appear to need this packing for TX packets in practical testing with "ASIX Elec. Corp. AX88x72A 000001" Vendor: 0x0b95 Product 0x7720 Version 0.1. The Linux kernel does no such padding for the TX path. Remove the padding from the TX path: * For consistency with the Linux kernel. * NVIDIA has a Tegra simulator which validates that the length of USB packets sent to an ASIX device matches the packet length value inside the packet data. Having U-Boot and the kernel do the same thing when creating the TX packets simplifies the simulator's validation. Cc: Lucas Stach <dev@lynxeye.de> Cc: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Marek Vasut <marex@denx.de> Tested-by: Gerhard Sittig <gsi@denx.de>
| * | | Merge branch 'master' of git://git.denx.de/u-boot-nand-flashTom Rini2014-03-04-392/+186
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| | * | | mtd: nand: omap: move omap_elm.h from arch/arm/include/asm to drivers/mtd/nandpekon gupta2014-03-04-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | omap_elm.h is a generic header used by OMAP ELM driver for all TI platfoms. Hence this file should be present in generic folder instead of architecture specific include folder. Build tested using: ./MAKEALL -s am33xx -s omap3 -s omap4 -s omap5 Signed-off-by: Pekon Gupta <pekon@ti.com>
| | * | | mtd: nand: omap: move omap_gpmc.h from arch/arm/include/asm to drivers/mtd/nandpekon gupta2014-03-04-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | omap_gpmc.h is a generic header used by OMAP NAND driver for all TI platfoms. Hence this file should be present in generic folder instead of architecture specific include folder. Build tested using: ./MAKEALL -s am33xx -s omap3 -s omap4 -s omap5 Signed-off-by: Pekon Gupta <pekon@ti.com>
| | * | | mtd: nand: omap: merge duplicate GPMC data from different arch-xx headers ↵pekon gupta2014-03-04-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into common omap_gpmc.h Each SoC platform (AM33xx, OMAP3, OMAP4, OMAP5) has its own copy of GPMC related defines and declarations scattered in SoC platform specific header files like include/asm/arch-xx/cpu.h However, GPMC hardware remains same across all platforms thus this patch merges GPMC data scattered across different arch-xx specific header files into single header file include/asm/arch/omap_gpmc.h Build tested using: ./MAKEALL -s am33xx -s omap3 -s omap4 -s omap5 Signed-off-by: Pekon Gupta <pekon@ti.com>
| | * | | mtd: nand: omap: optimized chip->ecc.correct() for H/W ECC schemespekon gupta2014-03-03-90/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | chip->ecc.correct() is used for detecting and correcting bit-flips during read operations. In omap-nand driver it implemented as: (a) omap_correct_data(): for h/w based ECC_HAM1 scheme (b) omap_correct_data_bch() + CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW_DETECTION_SW for ECC_BCH8 scheme using GPMC and software lib/bch.c (c) omap_correct_data_bch() + CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW for ECC_BCH8 scheme using GPMC and ELM This patch updates (c) - checks for calc_ecc[]==0x00 so that error_correction is not required for known good pages. - adds scalability for other ECC_BCHx scheme by merging following omap_rotate_ecc_bch() + omap_fix_errors_bch() => omap_correct_data_bch() - fixing logic for bit-flip correction based on error_loc[count] Signed-off-by: Pekon Gupta <pekon@ti.com>
| | * | | mtd: nand: omap: optimize chip->ecc.calculate() for H/W ECC schemespekon gupta2014-03-03-163/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | chip->ecc.calculate() is used for calculating and fetching of ECC syndrome by processing the data passed during Read/Write accesses. All H/W based ECC schemes use GPMC controller to calculate ECC syndrome. But each BCHx_ECC scheme has its own implemetation of post-processing and fetching ECC syndrome from GPMC controller. This patch updates OMAP_ECC_BCH8_CODE_HW ECC scheme in following way: - merges multiple chip->calculate API for different ECC schemes omap_calculate_ecc() + omap_calculate_ecc_bch() + omap_calculate_ecc_bch_sw() ==> omap_calculate_ecc() - removes omap_ecc_disable() and instead uses it as inline. Signed-off-by: Pekon Gupta <pekon@ti.com>
| | * | | mtd: nand: omap: optimize chip->ecc.hwctl() for H/W ECC schemespekon gupta2014-03-03-142/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | chip->ecc.hwctl() is used for preparing the H/W controller before read/write NAND accesses (like assigning data-buf, enabling ECC scheme configs, etc.) Though all ECC schemes in OMAP NAND driver use GPMC controller for generating ECC syndrome (for both Read/Write accesses). But but in current code HAM1_ECC and BCHx_ECC schemes implement individual function to achieve this. This patch (1) removes omap_hwecc_init() and omap_hwecc_init_bch() as chip->ecc.hwctl will re-initializeGPMC before every read/write call. omap_hwecc_init_bch() -> omap_enable_ecc_bch() (2) merges the GPMC configuration code for all ECC schemes into single omap_enable_hwecc(), thus adding scalability for future ECC schemes. omap_enable_hwecc() + omap_enable_ecc_bch() -> omap_enable_hwecc() Signed-off-by: Pekon Gupta <pekon@ti.com>
| * | | | sandbox: Convert GPIOs to use driver modelSimon Glass2014-03-04-78/+139
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert sandbox over to use driver model GPIOs. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | dm: Add GPIO support and testsSimon Glass2014-03-04-0/+268
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add driver model support for GPIOs. Since existing GPIO drivers do not use driver model, this feature must be enabled by CONFIG_DM_GPIO. After all GPO drivers are converted over we can perhaps remove this config. Tests are provided for the sandbox implementation, and are a sufficient sanity check for basic operation. The GPIO uclass understands the concept of named banks of GPIOs, with each GPIO device providing a single bank. Within each bank the GPIOs are numbered using an offset from 0 to n-1. For example a bank named 'b' with 20 offsets will provide GPIOs named b0 to b19. Anonymous GPIO banks are also supported, and are just numbered without any prefix. Each time a GPIO driver is added to the uclass, the GPIOs are renumbered accordinging, so there is always a global GPIO numbering order. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Pavel Herrmann <morpheus.ibis@gmail.com> Signed-off-by: Viktor Křivák <viktor.krivak@gmail.com> Signed-off-by: Tomas Hlavacek <tmshlvck@gmail.com>
generated by cgit v1.1 at 2024-11-27 21:52:10 +0000