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* Merge branch 'master' of git://git.denx.de/u-boot-arcTom Rini2016-04-11-16/+0
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| * arc: get rid of running_on_hwAlexey Brodkin2016-04-11-16/+0
| | | | | | | | | | | | | | | | ISS is obsolete now and nSIM is used for simulation instead. In its turn nSIM properly handles baud-rate settings so get rid of now useless check. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | lib/crc8: Add crc start valueStefan Roese2016-04-11-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To make the usage of this function more flexible, lets add the CRC start value as parameter to this function. This way it can be used by other functions requiring different start values than 0 as well. For non-zero CRC start values to work, I've reworked the function a bit. The new implementation is copied from the Linux version in drivers/i2c/i2c-core.c / i2c_smbus_pec(). Which supports non-zero CRC stating values. I've double-checked that the results for zero starting values are identical to the results from the original version of this function. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* | bootcounter_ram: Flush dcache after data is written into SDRAMStefan Roese2016-04-11-0/+3
| | | | | | | | | | | | | | | | | | | | This patch adds a call to flush_dcache_range() to bootcount_store() to make sure, that the bootcounter data (including the patterns) is written to memory. Without this, platforms with dcache enabled may not have the bootcounter updated upon reset. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Valentin Longchamp <valentin.longchamp@keymile.com>
* | stm32: stm32_flash: add memory barrier during flash writeVikas Manocha2016-04-11-0/+4
| | | | | | | | | | | | | | | | After writing data to flash space, next instruction is checking if flash controller is busy writing to the flash memory. Memory barrier is required here to avoid transaction re-ordering for data write and busy status check. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* | spmi: Fix sandbox spmi driver memory corruptionMateusz Kulikowski2016-04-11-1/+2
|/ | | | | | | | | | | There is off-by-one error in sandbox_emul_gpio that causes segfault of certain tests. EMUL_GPIO_REG_END is the address of last valid (emulated) register. This patch fixed this (by adding one more element to emulated register array). Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Tested-by: Stephen Warren <swarren@nvidia.com>
* Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2016-04-10-1/+0
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| * arm: socfpga: Nuke useless includeMarek Vasut2016-04-10-1/+0
| | | | | | | | | | | | | | | | | | | | The dwmmc.h include was forgotten during the migration of dwmmc probing to DM. Since the shiny DM is in place now, remove this relic of the past. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
* | musb: Properly call musb_stop() on probe failureHans de Goede2016-04-10-1/+3
| | | | | | | | | | | | | | musb_lowlevelinit(): if no device is plugged in / detected call musb_stop() to undo the preceding musb_start() call. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | musb: sunxi: Do not allocate musb struct multiple timesHans de Goede2016-04-10-4/+7
| | | | | | | | | | | | | | | | | | | | The probe function of the musb host driver can be called multiple times. The code assumes that it can save the pointer to the allocated musb struct in the driver model priv_auto_alloc data, but this data gets free-ed on a probe failure or on removal, so we must save the pointer elsewhere. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | usb: bcm_udc_otg: enable clocksSteve Rae2016-04-10-0/+4
| | | | | | | | | | | | Turn on the USB OTG clocks. Signed-off-by: Steve Rae <srae@broadcom.com>
* | drivers:usb:common:fsl-dt-fixup: fix return value of fdt_usb_get_node_typeSriram Dash2016-04-10-11/+14
| | | | | | | | | | | | | | Changes the return type of fdt_usb_get_node_type from char* to int Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
* | drivers:usb:common:fsl-dt-fixup: Add device-tree fixup support for xhci ↵Sriram Dash2016-04-10-16/+17
| | | | | | | | | | | | | | | | | | controller Enables usb device-tree fixup code to incorporate xhci controller Signed-off-by: Ramneek Mehresh <ramneek.mehresh@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
* | drivers:usb:common:fsl-dt-fixup: Remove code duplication for ↵Sriram Dash2016-04-10-43/+29
| | | | | | | | | | | | | | | | | | | | | | fdt_usb_get_node_type Call fdt_usb_get_node_type() from fdt_fixup_usb_mode_phy_type() to avoid code duplication. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Acked-by: Marek Vasut <marex@denx.de>
* | drivers:usb:common:fsl-dt-fixup: Move device-tree fixup framework to common fileSriram Dash2016-04-10-195/+219
| | | | | | | | | | | | | | | | | | Move usb device-tree fixup framework from ehci-fsl.c to common place so that it can be used by other drivers as well (xhci-fsl.c). Signed-off-by: Ramneek Mehresh <ramneek.mehresh@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Acked-by: Marek Vasut <marex@denx.de>
* | usb: ehci-hcd: Fix crash when no ops are provided to ehci_register()Mateusz Kulikowski2016-04-10-2/+2
| | | | | | | | | | | | | | | | | | | | | | This commit fixes crash on BananaPi (and possibly others) casued by 3f9f8a5b83f8aec40c9f4ee496046a695e333c45. Crash reason: When no ops were passed to ehci_register(), USB host driver caused NULL pointer dereference. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
* | drivers: musb-new: Add USB DRC driver for Microchip PIC32 OTG controller.Purna Chandra Mandal2016-04-10-1/+297
| | | | | | | | | | | | | | | | This driver adds support of PIC32 MUSB OTG controller as dual role device. It implements platform specific glue to reuse musb core. Signed-off-by: Cristian Birsan <cristian.birsan@microchip.com> Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
* | drivers: remove writes{b,w,l,q} and reads{b,w,l,q}.Purna Chandra Mandal2016-04-10-15/+0
|/ | | | | | | Definition of writes{bwlq}, reads{bwlq} are now added into arch specific asm/io.h. So removing them from driver to fix re-definition error Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-04-06-49/+235
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| * armv8: LS2080A: Consolidate LS2080A and LS2085AYork Sun2016-04-06-4/+13
| | | | | | | | | | | | | | | | | | | | | | | | LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * drivers: net: vsc9953: Fix bug when PVID is shown for disabled ports onlyCodrin Ciubotariu2016-04-06-1/+1
| | | | | | | | | | | | Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * drivers: net: vsc9953: Do not configure disabled portsCodrin Ciubotariu2016-04-06-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | Some SerDes protocols might not enable all l2switch ports. In this case, these ports should not be configured to perform Rx/Tx operations. This also fixes an issue when flooded frames were also switched to disabled ports and frames start to accumulate, consuming memory and eventually causing head-of-line blocking for other frames. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * fsl: esdhc: support driver modelPeng Fan2016-04-06-40/+213
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support Driver Model for fsl esdhc driver. 1. Introduce a new structure struct fsl_esdhc_priv 2. Refactor fsl_esdhc_initialize which is originally used by board code. - Introduce fsl_esdhc_init to be common usage for DM and non-DM - Introduce fsl_esdhc_cfg_to_priv to build the bridge for non-DM part. - The original API for board code is still there, but we use 'fsl_esdhc_cfg_to_priv' and 'fsl_esdhc_init' to serve it. 3. All the functions are changed to use 'struct fsl_esdhc_priv', except fsl_esdhc_initialize. 4. Since clk driver is not implemented, use mxc_get_clock to geth the clk and fill 'priv->sdhc_clk'. Has been tested on i.MX6UL 14X14 EVK board: " =>dm tree .... simple_bus [ + ] | `-- aips-bus@02100000 mmc [ + ] | |-- usdhc@02190000 mmc [ + ] | |-- usdhc@02194000 .... => mmc list FSL_SDHC: 0 (SD) FSL_SDHC: 1 (SD) " Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: York Sun <york.sun@nxp.com> Cc: Yangbo Lu <yangbo.lu@nxp.com> Cc: Hector Palacios <hector.palacios@digi.com> Cc: Eric Nelson <eric@nelint.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Simon Glass <sjg@chromium.org> Tested-By: Eric Nelson <eric@nelint.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | kirkwood_nand: claim MPP pins on the flyChris Packham2016-04-06-0/+19
| | | | | | | | | | | | | | | | | | | | | | Claim the MPP pins for the NAND flash controller only when it's actually being used. This allows the pins to be shared with the SPI interface which already supports an equivalent on-access MPP reconfiguration. Reviewed-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Acked-by: Scott Wood <oss@buserror.net> Signed-off-by: Stefan Roese <sr@denx.de>
* | spi: kirkwood_spi: Add support for multiple chip-selects on MVEBUStefan Roese2016-04-06-0/+14
|/ | | | | | | | | | | | | Currently only chip-select 0 is supported by the kirkwood SPI driver. The Armada XP / 38x SoCs also use this driver and support multiple chip selects. This patch adds support for multiple CS on MVEBU. The register definitions are restructured a bit with this patch. Grouping them to the corresponding registers. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Jagan Teki <jteki@openedev.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2016-04-04-15/+369
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| * net: zynq_gem: Add SGMII support for zynqMPSiva Durga Prasad Paladugu2016-04-04-2/+11
| | | | | | | | | | | | | | | | | | PCS auto negotaiation bit should be enabled along with SGMII autonegotation enabled in phy. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * net: phy: Add SGMII support for TI phySiva Durga Prasad Paladugu2016-04-04-1/+38
| | | | | | | | | | | | | | | | | | Add support of SGMII to TI phy dp838367 Enable the SGMII and PCS settings in phy control, CFG2 and BIST registers Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * net: zynq_gem: Return error incase of invalid phy addressSiva Durga Prasad Paladugu2016-04-04-3/+1
| | | | | | | | | | | | | | | | Return error from probe in case of invalid phy address. This fixes the issue of uboot crash if phy is not detected. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * block: Add support for Ceva sataMichal Simek2016-04-04-0/+114
| | | | | | | | | | | | | | Initial Ceva Sata init code. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * net: axi_emac: Report phy-node error message permanentlyMichal Simek2016-04-04-1/+1
| | | | | | | | | | | | Do not use debug() when printing error message. Use printf instead. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * net: gem: Allow to set the MAC from an EEPROMJoe Hershberger2016-04-04-0/+18
| | | | | | | | | | | | | | | | | | | | Provide board specific option how to read MAC address from ROM. Do it in generic way to be reusable by differnet boards. If this is not enough board specific functions can be created. Signed-off-by: Joe Hershberger <joe.hershberger@gmail.com> # driver part Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * net: xilinx_axi: Clear Isolate bit if found during phy setupSiva Durga Prasad Paladugu2016-04-04-1/+19
| | | | | | | | | | | | | | | | | | | | In SGMII cases the isolate bit might set after DMA and ethernet resets and hence check and clear during setup_phy if it was set. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * net: xilinx_axi: Use interface type instead of zeroSiva Durga Prasad Paladugu2016-04-04-1/+1
| | | | | | | | | | | | | | | | | | Pass appropriate interface type to phy_connect instead of zero. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * net: zynq_gem: Add support for SGMII interfaceSiva Durga Prasad Paladugu2016-04-04-7/+19
| | | | | | | | | | | | | | | | Add support of SGMII interface for zynq GEM. Read xlnx,emio property from DT. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * phy: Add phy driver support for xilinx PCS/PMA coreSiva Durga Prasad Paladugu2016-04-04-0/+148
| | | | | | | | | | | | | | | | Add phy driver support for xilinx PCS/PMA core Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | net: mvpp2.c: Add Marvell mvpp2 network driver for Armada 375Stefan Roese2016-04-04-0/+4199
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the mvpp2 ethernet controller which is integrated in the Marvell Armada 375 SoC. This port is based on the Linux driver (v4.4), which has been stripped of the in U-Boot unused portions. Tested on the Marvell Armada 375 eval board db-88f6720. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Acked-by: Joe Hershberger <joe.hershberger@gmail.com>
* | spi: kirkwood_spi.c: Add compatible match ID for Armada 375Stefan Roese2016-04-04-0/+1
|/ | | | | | | | This enables this driver for the Marvell Armada 375 SoC. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviwer-by: Jagan Teki <jteki@openedev.com>
* net: phy: Realtek RTL8211B/C PHY ID fixKarsten Merker2016-04-02-1/+2
| | | | | | | | | | | | | | | | | | | | | | | The RTL8211B_driver structure in drivers/net/phy/realtek.c contains a wrong PHY ID (0x1cc910 instead of 0x1cc912) in the uid field. The lowest four bits of the PHY ID encode the chip revision (B+C/D/E/F) of the RTL8211 and the code originally applied a mask of 0xfffff0 to the PHY ID, so that matching the PHY ID to the appropriate driver code was only done on the chip type (RTL8211), but not on a specific revision. After introduction of support for the RTL8211E, which needed another startup function than the older chip revisions, commit 42205047674d7fc9e0aa747273fbc7dcfbac3183 changed the mask to 0xffffff to make the chip revision relevant for the match, but didn't provide the now-relevant lower bits of the uid field for the RTL8211B/C. Fix this by setting the full PHY ID in the RTL8211B_driver uid field. Fixes: 42205047674d ("net/phy: realtek: Fix the PHY ID mask to ensure the correct Realtek PHY is detected") Signed-off-by: Karsten Merker <merker@debian.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* drivers: block: add block device cacheEric Nelson2016-04-01-1/+195
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a block device cache to speed up repeated reads of block devices by various filesystems. This small amount of cache can dramatically speed up filesystem operations by skipping repeated reads of common areas of a block device (typically directory structures). This has shown to have some benefit on FAT filesystem operations of loading a kernel and RAM disk, but more dramatic benefits on ext4 filesystems when the kernel and/or RAM disk are spread across multiple extent header structures as described in commit fc0fc50. The cache is implemented through a minimal list (block_cache) maintained in most-recently-used order and count of the current number of entries (cache_count). It uses a maximum block count setting to prevent copies of large block reads and an upper bound on the number of cached areas. The maximum number of entries in the cache defaults to 32 and the maximum number of blocks per cache entry has a default of 2, which has shown to produce the best results on testing of ext4 and FAT filesystems. The 'blkcache' command (enabled through CONFIG_CMD_BLOCK_CACHE) allows changing these values and can be used to tune for a particular filesystem layout. Signed-off-by: Eric Nelson <eric@nelint.com>
* gpio: Add support for Qualcomm PM8916 gpiosMateusz Kulikowski2016-04-01-0/+313
| | | | | | | | | | | This driver supports GPIOs present on PM8916 PMIC. There are 2 device drivers inside: - GPIO driver (4 "generic" GPIOs) - Keypad driver that presents itself as GPIO with 2 inputs (power and reset) Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* pmic: Add support for Qualcomm PM8916 PMICMateusz Kulikowski2016-04-01-0/+113
| | | | | | | | This PMIC is connected on SPMI bus so needs SPMI support enabled. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* drivers: spmi: Add support for Qualcomm SPMI bus driverMateusz Kulikowski2016-04-01-1/+196
| | | | | | | | Support SPMI arbiter on Qualcomm Snapdragon devices. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* spmi: Add sandbox test driverMateusz Kulikowski2016-04-01-0/+166
| | | | | | | | This patch adds emulated spmi bus controller with part of pm8916 pmic on it to sandbox and tests validating SPMI uclass. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* drivers: Add SPMI bus uclassMateusz Kulikowski2016-04-01-0/+68
| | | | | | | | | | | | Qualcom processors use proprietary bus to talk with PMIC devices - SPMI (System Power Management Interface). On wiring level it is similar to I2C, but on protocol level, it's multi-master and has simple autodetection capabilities. This commit adds simple uclass that provides bus read/write interface. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* ehci: Add support for Qualcomm EHCIMateusz Kulikowski2016-04-01-0/+190
| | | | | | | | | | This driver is able to reconfigure OTG controller into HOST mode. Board can add board-specific initialization as board_prepare_usb(). It requires USB_ULPI_VIEWPORT enabled in board configuration. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Simon Glass <sjg@chromium.org>
* ehci-ci.h: drop generic USBCMD fieldsMateusz Kulikowski2016-04-01-2/+2
| | | | | | | | Use definitions from ehci.h instead. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Simon Glass <sjg@chromium.org>
* usb: Rename ehci-fsl.h to ehci-ci.hMateusz Kulikowski2016-04-01-7/+7
| | | | | | | | | | | | | Most of ehci-fsl header describe USB controller designed by Chipidea and used by various SoC vendors. This patch renames it to a generic header: ehci-ci.h Contents of file are not changed (so it contains several references to freescale SoCs). Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Simon Glass <sjg@chromium.org>
* eth: asix88179: Print packet length properlyMateusz Kulikowski2016-04-01-1/+1
| | | | | | | | | Debug printf used '%u' to print size_t variable. This caused warnings on 64-bit machines. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* usb: ulpi: Fix compile warning in read/write on 64-bit machines.Mateusz Kulikowski2016-04-01-2/+3
| | | | | | | | | | | | | | | | | | | ulpi_read and ulpi_write are used to read/write registers via ULPI bus. Code generates compilation warnings on 64-bit machines where pointer is cast to u32. This patch drops all but last 8 bits of register address. It is possible, because addresses on ULPI bus are 6- or 8-bit. It is not possible (according to ULPI 1.1 spec) to have more than 8-bit addressing. This patch should not cause regressions as all calls to ulpi_read/write use either structure pointer (@ address 0) or integer offsets cast to pointer - addresses requested are way below 8-bit range. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
generated by cgit v1.1 at 2024-07-15 09:56:46 +0000