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* driver/ddr: Fix DDR register timing_cfg_8York Sun2014-07-22-0/+3
| | | | | | | The field wrtord_bg should add 2 clocks if on the fly chop is enabled, according to DDR controller manual for DDR4. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr: Fix DDR4 driver for ARMYork Sun2014-07-22-2/+5
| | | | | | | Previously the driver was only tested on Power SoCs. Different barrier instructions are needed for ARM SoCs. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/nand: Add support of 16K SRAM for IFC 2.0Prabhakar Kushwaha2014-07-22-2/+8
| | | | | | | | | Internal SRAM has been incresed from 8KB to 16KB for IFC cotroller ver 2.0. Update the page offset calculation logic to support the same. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* fsl/pcie: Change 'no link' to 'undetermined' for pcie endpointZang Roy-R619112014-07-22-2/+8
| | | | | | | | | | | Even u-boot boots up, the pcie link may not setup correctly when Freescale SOC acts as endpoint. So change the link status from 'no link' to 'undetermined' to reduce the confusion. The link status can check from host side eventually. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* driver/nand: Update SRAM initialize logic for IFC.Prabhakar Kushwaha2014-07-22-4/+31
| | | | | | | | | | | | | IFC controller v1.1.0 requires internal SRAM initialize by reading NAND flash. Higher controller versions have provided "SRAM init" bit in NCFGR register space. update SRAM initialize logic to reflect the same. Also print error message in case of Page read error. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* driver/nand:Define MAX_BANKS same as SoC defined for IFCPrabhakar Kushwaha2014-07-22-1/+5
| | | | | | | | | | The number of chip select used by IFC controller vary from one SoC to other. For eg. P1010 has 4, T4240 has 8. Update MAX_BANKS same as SoC defined Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* qe: move immap_qe.h from arch directory into common directoryZhao Qiang2014-07-22-6/+6
| | | | | | | | ls1021 is arm-core and supports qe too. Move immap_qe.h into common directory for both arm and powerpc. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* net/fm: call fm_port_to_index() with proper checksRotariu Marian-Cristian2014-07-22-1/+8
| | | | | | | | Some of the fm_port_to_index() callers did not check for -1 return value and used -1 as an array index. Signed-off-by: Marian Rotariu <marian.rotariu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* AHCI: Increase link timeout to 200msIan Campbell2014-07-22-1/+1
| | | | | | | | | | | | | In 73545f75b66d "ahci: wait longer for link" I increased the timeout to 40ms based on the observed behaviour of a WD disk on a Cubietruck. Since then Karsten Merker and myself have both observed timeouts with HGST disks (Karsten on Cubietruck, me on Cubieboard2). Increasing the timeout to ~175ms fixes this, so go to 200ms for a bit of headroom. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Cc: Karsten Merker <merker@debian.org> Acked-by: Hans de Goede <hdegoede@redhat.com>
* serial: ns16550: use a const variable instead of macroMasahiro Yamada2014-07-22-3/+3
| | | | | | | | Just for type checking. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de>
* serial: ns16550: use DIV_ROUND_CLOSEST macro to compute the divisorMasahiro Yamada2014-07-22-7/+3
| | | | | | | | | The function still returns the same value. The comment block is no longer necessary because our intention is clear enough by using DIV_ROUND_CLOSEST() macro. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* serial: ns16550: drop CONFIG_OMAP1610 from the special caseMasahiro Yamada2014-07-22-6/+0
| | | | | | | | | | | | | | | | | | | If CONFIG_OMAP1610 is defined, the code returning the fixed value (26) is enabled. But this case is covered by the following code. (CONFIG_SYS_NS16550_CLK + (gd->baudrate * (MODE_X_DIV / 2))) / (MODE_X_DIV * gd->baudrate) = (48000000 + (115200 * (16 / 2))) / (16 * 115200) = 48921600 / 1843200 = 26 The "#ifdef CONFIG_OMAP1610" was added by commit 6f21347d more than ten years ago. In those days, the divide-and-round was not used. I guess that is why this weird code was added here. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> Cc: Rishi Bhattacharya <rishi@ti.com>
* driver/usb: include upper/lower_32_bits() from linux/compat.hLijun Pan2014-07-22-4/+2
| | | | | | | upper_32_bits() and lower_32_bits() have been ported into linux/compat.h. Start use them now in drivers/usb/host/xhci.h. Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2014-07-21-2/+77
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| * fsl_i2c: add support for 3rd and 4th I2CShengzhou Liu2014-07-16-2/+20
| | | | | | | | | | | | Add support for 3rd and 4th I2C. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
| * i2c, omap24xx: add i2c deblock sequenzHeiko Schocher2014-07-16-0/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a bus busy is detected when intializing the driver, toggle 9 times the scl pin. Therefore enable the test mode of the controller, in which the scl, sda pins can be controlled manually. Tested on the siemens boards pxm2, rut and dxr2. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Hannes Petermaier <oe5hpm@oevsv.at> Cc: Lubomir Popov <lpopov@mm-sol.com> Cc: Steve Sakoman <steve@sakoman.com> Cc: Sandeep Paulraj <s-paulraj@ti.com> Cc: Vincent Stehlé <v-stehle@ti.com> Cc: Samuel Egli <samuel.egli@siemens.com>
* | mmc: prevent some warnings with make W=1Jeroen Hofstee2014-07-18-4/+4
| | | | | | | | | | | | | | | | Add missing prototypes for global functions and make local functions static. cc: panto@antoniou-consulting.com Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* | dirvers: mmc: use __weakJeroen Hofstee2014-07-18-11/+9
| | | | | | | | | | use weak instead of alias to prevent some clang warnings. Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* | dm: add missing includesJeroen Hofstee2014-07-18-0/+2
| | | | | | | | | | | | | | | | | | | | lists.c / root.c do not include their own header and they could potentially implement a different function. Therefore actually include the headers. cc: sjg@chromium.org Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Acked-by: Simon Glass <sjg@chromium.org>
* | mtd: cfi_flash: fix clang warningJeroen Hofstee2014-07-18-1/+1
|/ | | | | | | | | | | | clang warns this check is silly; it is since s is a local variable. u-boot/drivers/mtd/cfi_flash.c:2363:13: warning: comparison of array 's' not equal to a null pointer is always true else if ((s != NULL) && (strcmp(s, "yes") == 0)) { cc: Stefan Roese <sr@denx.de> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* usb: phy: omap_usb_phy: implement usb_phy_power() for AM437xFelipe Balbi2014-07-09-1/+16
| | | | | | | | Newer AM437x silicon requires us to explicitly power up the USB2 PHY. By implementing usb_phy_power() we can achieve that. Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: host: xhci: make sure to power up PHYFelipe Balbi2014-07-09-0/+1
| | | | | | | some boards won't work if the PHY isn't explicitly powered up. Signed-off-by: Felipe Balbi <balbi@ti.com>
* board: gdsys: Make gdsys osd hardware detection more robustDirk Eibach2014-07-07-1/+0
| | | | Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
* i2c: IHS I2C master driverDirk Eibach2014-07-07-0/+205
| | | | | | | | IHS I2C master support was merely a hack in the osd driver. Now it is a proper u-boot I2C framework driver, supporting the v2.00 master features. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
* blackfin: Fix warning about undefined functionVasili Galka2014-07-07-0/+1
| | | | | | | get_sclk() was not defined in bfin_wdt.c, include the corresponding header. Cc: Sonic Zhang <sonic.adi@gmail.com> Signed-off-by: Vasili Galka <vvv444@gmail.com>
* mpc8xx: remove v37 board supportMasahiro Yamada2014-07-07-7/+1
| | | | | | This board is old enough and has no maintainer. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* mpc8xx: remove rbc823 board supportMasahiro Yamada2014-07-07-66/+1
| | | | | | This board is old enough and has no maintainer. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* mpc8xx: remove RPXlite_dw, quantum board supportMasahiro Yamada2014-07-07-89/+0
| | | | | | These boards are old enough and have no maintainers. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* tpm: don't use unneeded double bracketsJeroen Hofstee2014-07-07-1/+1
| | | | | | | | clang is tempted to inteprete such a condition as a assignment as well. Since it isn't don't use double brackets. cc: Tom Wai-Hong Tam <waihong@chromium.org> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* build: define CPU only when arch/${ARCH}/cpu/${CPU} existsMasahiro Yamada2014-07-07-1/+1
| | | | | | | | | | | | | | | | | | | The directory arch/${ARCH}/cpu/${CPU} does not exist in avr32, blackfin, microblaze, nios2, openrisc, sandbox, x86. These architectures have only one CPU type. Defining CPU should not be required for such architectures. This commit allows cpu field (= the 3rd field of boards.cfg) to be kept blank. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Sonic Zhang <sonic.zhang@analog.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Thomas Chou <thomas@wytron.com.tw> Cc: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
* Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2014-07-07-17/+27
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| * i2c: tegra: dump alen in debug statementsStephen Warren2014-07-03-4/+4
| | | | | | | | | | | | | | | | | | Since tegra_i2c_{read,write}'s debug() call dumps the chip address, dump the address length (alen) too, so the address value can be correctly interpreted. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Yen Lin <yelin@nvidia.com>
| * i2c: tegra: write clean data to TX FIFOStephen Warren2014-07-03-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Tegra I2C controller's TX FIFO contains 32-bit words. If the final FIFO entry of a transaction contains fewer than 4 bytes, the driver currently fills the unused FIFO bytes with uninitialized data. This can be confusing when reading back the FIFO content for debugging purposes. Solve this by explicitly initializing the variable containing FIFO data before filling it (partially) with data. With this change, send_recv_packets()'s loop's if (is_write) code mirrors the else (i.e. read) branch. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Yen Lin <yelin@nvidia.com>
| * i2c: tegra: use repeated start for readsStephen Warren2014-07-03-8/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I2C read transactions are typically implemented as follows: START(write) address REPEATED_START(read) data... STOP However, Tegra's I2C driver currently implements reads as follows: START(write) address STOP START(read) data... STOP This sequence confuses at least the AS3722 PMIC on the Jetson TK1 board, leading to corrupted read data in some cases. Fix the driver to chain the transactions together using repeated starts to solve this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Yen Lin <yelin@nvidia.com>
* | watchdog/denali: Adding DesignWare watchdog driver supportChin Liang See2014-07-05-0/+75
| | | | | | | | | | | | | | | | | | | | | | | | To add the DesignWare watchdog driver support. It required information such as register base address and clock info from configuration header file within include/configs folder. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com>
* | arm: ep9315: Return back Cirrus Logic EDB9315A board supportSergey Kostanbaev2014-07-04-0/+314
| | | | | | | | | | | | | | This patch returns back support for old ep93xx processors family Signed-off-by: Sergey Kostanbaev <sergey.kostanbaev@gmail.com> Cc: albert.u.boot@aribaud.net
* | gpio: spear_gpio: Fix gpio_set_value() implementationAxel Lin2014-07-04-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In current gpio_set_value() implementation, it always sets the gpio control bit no matter the value argument is 0 or 1. Thus the GPIOs never set to low. This patch fixes this bug. The address bus is used as a mask on read/write operations, so that independent software drivers can set their GPIO bits without affecting any other pins in a single write operation. Thus we don't need a read-modify-write to update the register. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Vipin Kumar <vipin.kumar@st.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
* | armv8/fsl-lsch3: Add support to load and start MC FirmwareJ. German Rivera2014-07-03-0/+275
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding support to load and start the Layerscape Management Complex (MC) firmware. First, the MC GCR register is set to 0 to reset all cores. MC firmware and DPL images are copied from their location in NOR flash to DDR. MC registers are updated with the location of these images. Deasserting the reset bit of MC GCR register releases core 0 to run. Core 1 will be released by MC firmware. Stop bits are not touched for this step. U-boot waits for MC until it boots up. In case of a failure, device tree is updated accordingly. The MC firmware image uses FIT format. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Shruti Kanetkar <Shruti@Freescale.com>
* | ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoCYork Sun2014-07-03-0/+5
|/ | | | | | | | | | | | | | Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-07-02-40/+1035
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| * Merge remote-tracking branch 'u-boot-samsung/master'Albert ARIBAUD2014-07-01-6/+12
| |\ | | | | | | | | | | | | | | | | | | | | | Conflicts: boards.cfg Conflict was trivial between goni maintainer change and lager_nor removal.
| | * PMIC: MAX77686: fix invalid bus checkJeroen Hofstee2014-06-23-5/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since p->bus is unsigned checking for negative values is optimized away. Since bus is already used as an argument use tmp. While at it, don't declare variables in the middle of a function. cc: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * Exynos: SPI: Fix reading data from SPI flashAkshay Saraswat2014-06-23-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPI recieve and transfer code in exynos_spi driver has a logical bug. We read data in a variable which can hold an integer. Then we assign this integer 32 bit value to another variable which has data type uchar. Latter represents a unit of our recieve buffer. Everytime when we write a value to our recieve buffer we step ahead by 4 units when actually we wrote to one unit. This results in the loss of 3 bytes out of every 4 bytes recieved. This patch intends to fix this bug. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2014-07-01-3/+84
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| | * | spi: davinci: Fix register address for SPI1_BUSAxel Lin2014-06-19-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Fix a trivial copy-paste bug. Signed-off-by: Axel Lin <axel.lin@ingics.com>
| | * | ARM: keystone: aemif: move aemif driver to drivers/memory/ti-aemif.cKhoronzhuk, Ivan2014-06-19-0/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move AEMIF driver to drivers/memory/ti-aemif.c along with AEMIF definitions collected in arch/arm/include/asm/ti-common/ti-aemif.h Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * | mtd: nand: davinci: add header file for driver definitionsKhoronzhuk, Ivan2014-06-19-2/+1
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The definitions inside emif_defs.h concern davinci nand driver and should be in it's header. So create header file for davinci nand driver and move definitions from emif_defs.h and nand_defs.h to it. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> [trini: Fixup more davinci breakage] Signed-off-by: Tom Rini <trini@ti.com>
| * | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-06-30-2/+239
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| | * | dwc_ahsata: return failure for MX6 if not IMX6Q/IMX6DTim Harvey2014-06-06-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The IMX6QUAD/DUAL have SATA, but the IMX6SOLO/DL do not. Return failure instead of attempting a memory access that results in a data abort and reset. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| | * | spl: nand: add support for mxs nandTim Harvey2014-06-06-0/+232
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This utilizes existing mxs_nand support layer to provide a method to load an image off nand for SPL. The flash device will be detected in order to support multiple flash devices instead of having layout hard coded at build time. Cc: Stefan Roese <sr@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Andy Ng <andreas2025@gmail.com> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Tapani Utriainen <tapani@technexion.com> Cc: Tom Rini <trini@ti.com> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
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