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* Update Maintainer and Author's email addressAjay Bhargav2016-12-27-6/+6
| | | | | | | | I am not longer using my old email address "ajay.bhargav@einfochips.com". For U-Boot development email address is now updated to contact@8051projects.net Signed-off-by: Ajay Bhargav <contact@8051projects.net>
* timer: Support clocks via phandleZakharov Vlad2016-12-27-3/+14
| | | | | | | | | | | | | Earlier timer driver needed a clock-frequency property in compatible device-tree nodes. Another way is to reference a clock via a phandle. So now timer_pre_probe tries to get clock by reference through device tree. In case it is impossible to get clock device through the reference, clock-frequency property of the timer node is read to provide backward compatibility. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* regulator: fixed: Add support to handle enable-active-high DT propertyVignesh R2016-12-27-1/+6
| | | | | | | | | Add support to handle enable-active-high DT property. This property is used to drive the gpio controlling fixed regulator as active high when claiming gpio line. Signed-off-by: Vignesh R <vigneshr@ti.com> Acked-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2016-12-23-295/+0
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| * spi: Zap armada100_spi.c and envJagan Teki2016-12-21-204/+0
| | | | | | | | | | | | | | | | armada100_spi.c and related env is zapping becuase of "no DM conversion". Cc: Ajay Bhargav <ajay.bhargav@einfochips.com> Signed-off-by: Jagan Teki <jagan@openedev.com>
| * spi: Zap mpc52xx_spi.c, config and related codeJagan Teki2016-12-21-91/+0
| | | | | | | | | | | | | | | | | | armada100_spi.c, related config options and related codes are zapping becuase of "no DM conversion". Cc: Werner Pfister <Pfister_Werner@intercontrol.de> Signed-off-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-samsungTom Rini2016-12-23-0/+69
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| * | power: pmic: add the max8998 controller for DMJaehoon Chung2016-12-22-0/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add the max8998 controller for Driver model. Samsung S5P series are using max8998 pmic controller. In future, it should be supported the regulator framework. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | mmc: Extend dependencies for zynq sdhciMichal Simek2016-12-22-1/+1
| | | | | | | | | | | | | | | | | | | | | There is hard dependency on BLK and DM_MMC which is also used by ATMEL and ROCKCHIP. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | mmc: spear: remove the entire spear_sdhci.c fileJaehoon Chung2016-12-22-28/+0
|/ / | | | | | | | | | | | | | | | | Remove the entire spear_sdhci.c file. There is no use case. This is dead codes. Also there is no place to call "spear_sdhci_init()" anywhere. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2016-12-20-18/+115
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| * | gpio: zynq: Remove empty lineMichal Simek2016-12-20-1/+0
| | | | | | | | | | | | | | | | | | Trivial coding style fix. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | block: Move ceva driver to DMMichal Simek2016-12-20-2/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch also includes ARM64 zynqmp changes: - Remove platform non DM initialization - Remove hardcoded sata base address Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | dm: Add support for scsi/sata based devicesMichal Simek2016-12-20-9/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All sata based drivers are bind and corresponding block device is created. Based on this find_scsi_device() is able to get back block device based on scsi_curr_dev pointer. intr_scsi() is commented now but it can be replaced by calling find_scsi_device() and scsi_scan(). scsi_dev_desc[] is commented out but common/scsi.c heavily depends on it. That's why CONFIG_SYS_SCSI_MAX_DEVICE is hardcoded to 1 and symbol is reassigned to a block description allocated by uclass. There is only one block description by device now but it doesn't need to be correct when more devices are present. scsi_bind() ensures corresponding block device creation. uclass post_probe (scsi_post_probe()) is doing low level init. SCSI/SATA DM based drivers requires to have 64bit base address as the first entry in platform data structure to setup mmio_base. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | net: xilinx: Use mdio_register_seq() to support multiple instancesMichal Simek2016-12-20-6/+3
| |/ | | | | | | | | | | | | | | | | | | | | | | axi_emac, emaclite and gem have the same issue with registering multiple instances with mdio busses. mdio bus name has to be uniq but drivers are setting up only one name for all. Use mdio_register_seq() and pass dev->seq number to allow multiple mdio instances registration. Reported-by: Phani Kiran Kara <phanikiran.kara@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2016-12-20-2/+2
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| * i2c: mv_i2c.c: Correct address endiannessBradley Bolen2016-12-19-2/+2
| | | | | | | | | | | | | | | | | | | | 0c0f719ad2f46c8566a56daee37ebdb7c078c3b1 accidentally changed the endianness of the i2c read and write addresses. This was noticable when accessing EEPROMs that use 2 byte addressing as the LSB was being sent first. Signed-off-by: Bradley Bolen <bradleybolen@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
* | serial: 16550: Add Ingenic JZ4780 supportMarek Vasut2016-12-19-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Add compatibility string for the Ingenic JZ4780 SoC, the necessary UART enable bit into FCR and register shift. Neither are encoded in the DTS coming from Linux, so we need to support it this way. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | serial: 16550: Add port type as driver dataMarek Vasut2016-12-19-10/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add driver data to each compatible string to identify the type of the port. Since all the ports in the driver are entirely compatible with 16550 for now, all are marked with PORT_NS16550. But, there are ports which have specific quirks, like the JZ4780 UART, which do not have any DT property to denote the quirks. Instead, Linux uses the compatible string to discern such ports and enable the necessary quirks. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org>
* | serial: 16550: Add getfcr accessorMarek Vasut2016-12-19-2/+16
| | | | | | | | | | | | | | | | | | | | | | Add function which allows fetching the default FCR register setting from platform data for DM , while retaining old behavior for non-DM by returning UART_FCRVAL. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-12-18-185/+437
|\ \ | |/ |/| | | | | | | Migrate CONFIG_ARCH_USE_MEMSET/MEMCPY with this merge. Signed-off-by: Tom Rini <trini@konsulko.com>
| * i2c: mxc: Make 'no gpio pinctrl state' print as debugJagan Teki2016-12-16-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some I2C bus devicetree nodes, doesn't require to have gpio pinctrl so replace the dev_info to debug so the print never comes on the console and for bus that uses gpio pinctrl anyway have dev_err. Before: ------ U-Boot> i2c dev 1 Setting bus to 1 i2c bus 1 at 0x21a4000, no gpio pinctrl state. After: ------ U-Boot> i2c dev 1 Setting bus to 1 Cc: Simon Glass <sjg@chromium.org> Cc: Heiko Schocher <hs@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Heiko Schocher <hs@denx.de>
| * i2c: mxc: Print hex instead of decimal for bus addressJagan Teki2016-12-16-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Better to print the hex value for bus address instead of decimal, for more readbility on bus addressing. Before: ------ U-Boot> i2c dev 1 Setting bus to 1 i2c bus 1 at 35274752, no gpio pinctrl state. After: ------ U-Boot> i2c dev 1 Setting bus to 1 i2c bus 1 at 0x21a4000, no gpio pinctrl state. Cc: Simon Glass <sjg@chromium.org> Cc: Heiko Schocher <hs@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Heiko Schocher <hs@denx.de>
| * i2c: Kconfig: Add SYS_I2C_MXC entryJagan Teki2016-12-16-0/+8
| | | | | | | | | | | | | | | | | | | | Added kconfig for SYS_I2C_MXC driver. Cc: Stefano Babic <sbabic@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * video: Kconfig: Add VIDEO_IPV3 entryJagan Teki2016-12-16-0/+7
| | | | | | | | | | | | | | | | | | | | Added kconfig entry for CONFIG_VIDEO_IPV3 driver. Cc: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * dm: net: fec: Add .read_rom_hwaddrJagan Teki2016-12-16-9/+9
| | | | | | | | | | | | | | | | | | | | Add .read_rom_hwaddr on dm eth_ops. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * net: fec_mxc: Driver cleanupsJagan Teki2016-12-16-146/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Remove exctra space - Add space - Add tab space - Fix single line comments quotes - Fix 'CHECK: Avoid CamelCase' - Fix 'CHECK: Alignment should match open parenthesis' - Fix 'WARNING: line over 80 characters' - Re-arrage header include files Cc: Simon Glass <sjg@chromium.org> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * net: fec_mxc: Convert into driver modelJagan Teki2016-12-16-26/+246
| | | | | | | | | | | | | | | | | | | | | | | | This patch add driver model support for fec_mxc driver. Cc: Simon Glass <sjg@chromium.org> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: fec_mxc: Remove unneeded eth_device arg from fec_get_hwaddrJagan Teki2016-12-16-3/+2
| | | | | | | | | | | | | | | | | | | | | | fec_get_hwaddr never used eth_device argument, hence removed. Cc: Simon Glass <sjg@chromium.org> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * arm: imx: add i.MX53 Beckhoff CX9020 Embedded PCPatrick Bruenn2016-12-16-2/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add CX9020 board based on mx53loco. Add simplified imx53 base device tree from kernel v4.8-rc8, to reuse serial_mxc with DTE and prepare for device tree migration of other functions and imx53 devices. The CX9020 differs from i.MX53 Quick Start Board by: - use uart2 instead of uart1 - DVI-D connector instead of VGA - no audio - CCAT FPGA connected to emi - enable rtc Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
| * pinctrl: imx6: support i.MX6SLLPeng Fan2016-12-16-0/+2
| | | | | | | | | | | | | | | | | | | | There two iomuxc for i.MX6SLL. One is normal IOMUXC, the other is for IOMUXC_SNVS. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
| * OCOTP: Update OCOTP driver to support i.MX6SLLPeng Fan2016-12-16-8/+8
| | | | | | | | | | | | | | | | | | | | Add the i.MX6SLL support to OCOTP driver. The i.MX6SLL reuses the i.MX6ULL fuse, bank 7 and bank8 have 4 words each, and there is a hole between bank 5 and bank 6. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2016-12-16-175/+94
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| * | Revert "sf: Fix quad bit set for micron devices"Cyrille Pitchen2016-12-15-63/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit c56ae7519f141523ba1248b22b5b5169b21772fe. Once the 'Quad Enable' bit is cleared in their Enhanced Volatile Configuration Register (EVCR), Micron memories expect ALL commands to use the SPI 4-4-4 protocol. Commands using SPI 1-y-z protocols are no longer accepted. Within the reverted commit, the write_evcr() function is implemented using the spi_flash_write_common(), which is a shortcut for the [ spi_flash_cmd_write_enable(), spi_flash_cmd_write(), spi_flash_cmd_wait_ready() ] sequence. Since the internal state of the Micron memory has been changed when the spi_flash_cmd_write() function completes, the later call of the spi_flash_cmd_wait_ready() function fails. Indeed the SPI controller driver is not aware of the SPI protocol switch. Further patches will fix the support of Micron QSPI memories. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> [Rebase on master, use JEDEC_MFR(info) in place of idcode0] Signed-off-by: Jagan Teki <jagan@openedev.com>
| * | sf: Do not force the DT memory map size to exactly match the devicePhil Edworthy2016-12-15-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | As long as the memory mapped size specifeid in the DT is the same or bigger than the device size, it will work. So do not force the sizes to be identical. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | mtd: spi: don't return -1 when scan succeedFabien Parent2016-12-15-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In spi_flash_scan, 'ret' is initialled to -1, but 'ret' is not always used to store a return value, in that case, even when the function succeed, an error (-1) will be returned. Lets just return 0 if we hit the end of the function. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | spi: cadence_qspi: Move DT prop code to match layoutPhil Edworthy2016-12-15-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Move the code to read the "sram-size" property into the other code that reads properties from the node, rather than the SF subnode. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | spi: cadence_qspi: Fix CS timingsPhil Edworthy2016-12-15-11/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Cadence QSPI controller has specified overheads for the various CS times that are in addition to those programmed in to the Device Delay register. The overheads are different for the delays. In addition, the existing code does not handle the case when the delay is less than a SCLK period. This change accurately calculates the additional delays in Ref clocks. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | spi: cadence_qspi: Remove returns from end of void functionsPhil Edworthy2016-12-15-8/+0
| | | | | | | | | | | | | | | | | | Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | spi: cadence_qspi: Use spi mode at the point it is neededPhil Edworthy2016-12-15-9/+5
| | | | | | | | | | | | | | | | | | | | | | | | Instead of extracting mode settings and passing them as separate args to another function, just pass the SPI mode as an arg. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | spi: cadence_qspi: Clean up the #define namesPhil Edworthy2016-12-15-43/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A lot of the #defines are for single bits in a register, where the name has _MASK on the end. Since this can be used for both a mask and the value, remove _MASK from them. Whilst doing so, also remove the unnecessary brackets around the constants. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | spi: cadence_qspi: Use #define for bits instead of bit shiftsPhil Edworthy2016-12-15-18/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most of the code already uses #defines for the bit value, rather than the shift required to get the value. This changes the remaining code over. Whislt at it, fix the names of the "Rd Data Capture" register defs. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | spi: cadence_qspi: Better debug information on the SPI clock ratePhil Edworthy2016-12-15-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Show what the output clock rate actually is. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | spi: cadence_qspi: Fix baud rate calculationPhil Edworthy2016-12-15-16/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the existing code, when the requested SPI clock rate is near to the lowest that can be achieved by the hardware (max divider of the ref clock is 32), the generated clock rate is wrong. For example, with a 50MHz ref clock, when asked for anything less than a 1.5MHz SPI clock, the code sets up the divider to generate 25MHz. This change fixes the calculation. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | spi: cadence_qspi: Fix clearing of pol/pha bitsPhil Edworthy2016-12-15-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Or'ing together bit positions is clearly wrong. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | spi: Add error checking for invalid bus widthsSimon Glass2016-12-15-2/+2
| |/ | | | | | | | | | | | | | | | | | | At present an invalid bus width prints a message but does not return an error. This is the opposite of the correct behaviour. Adjust it to avoid code bloat in the common case, and avoid hard-to-debug failure in the uncommon case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
* | driver: fsl-mc: qbman: Add QBMAN 4.1 supportPriyanka Jain2016-12-15-13/+48
|/ | | | | | | | | | | | | | | LS2080A SoC family has QBMAN ver 4.0 whereas newer SoCs like LS2088A, LS1088A has QBMAN ver 4.1 QBMAN ver 4.0 and ver 4.1 supports dqrr size as 4 and 8 respectively. Add support of to check QBMAN version based on SoC SVR update dqrr_size accordingly update code to support larger dqrr_size Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Merge git://www.denx.de/git/u-boot-marvellTom Rini2016-12-12-0/+226
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| * arm64: mvebu: pinctrl: Add pin control driver for A8K familyKonstantin Porotchkin2016-12-12-0/+226
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a DM port of Marvell pin control driver. The A8K SoC family contains several silicone dies interconnected in a single package. Every die is normally equipped with its own pin controller unit. There are 2 pin controllers in A70x0 SoC and 3 in A80x0 SoC. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | spl: Add a name to the SPL load-image methodsSimon Glass2016-12-09-1/+1
|/ | | | | | | | | | | It is useful to name each method so that we can print out this name when using the method. Currently this happens using a separate function. In preparation for unifying this, add a name to each method. The name is only available if we have libcommon support (i.e can use printf()). Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-07-02 17:46:47 +0000