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* mmc/dwmmc: use bounce buffer for data exchange between CPU and MMC controllerAlexey Brodkin2014-01-09-10/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bounce buffer implementation takes care of proper data buffer alignemt and correct flush/invalidation of data cache at once so we no longer depend on input data variety and make sure CPU and MMC controller deal with expected data in case of enabled data cache. Bounce buffer requires to add its definition (CONFIG_BOUNCE_BUFFER) in board configuration, otherwise corresponding library won't be compiled and linker will fail to build resulting executable. Difference since v1 - fixed compile-time warning with type casting to "void *": Slight edit to remove UTF8 characters in the commit message. Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> ==== passing argument 2 of 'bounce_buffer_start' discards 'const' qualifier from pointer target type ==== Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Mischa Jonker <mjonker@synopsys.com> Cc: Alim Akhtar <alim.akhtar@samsung.com> Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Amar <amarendra.xt@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Andy Fleming <afleming@gmail.com>
* mmc/dwmmc: Using calloc instead mallocChin Liang See2014-01-08-2/+2
| | | | | | | | | | | | | | | To enhance the SDMMC DesignWare driver to use calloc instead of malloc. This will avoid the incident that uninitialized members of mmc structure are later used for NULL comparison. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Mischa Jonker <mjonker@synopsys.com> Cc: Alexey Brodkin <abrodkin@synopsys.com> Cc: Andy Fleming <afleming@freescale.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* mtd: onenand: Fix unaligned accessMarek Vasut2013-12-31-1/+7
| | | | | | | | | | | | | | | Fix unaligned access in OneNAND core. The problem is that the ffchars[] array is an array of "unsigned char", but in onenand_write_ops_nolock() can be passed to the memcpy_16() function. The memcpy_16() function will treat the buffer as an array of "unsigned short", thus triggering unaligned access if the compiler decided ffchars[] to be not aligned. I managed to trigger the problem with regular ELDK 5.4 GCC compiler. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Scott Wood <scottwood@freescale.com> Cc: Tom Rini <trini@ti.com>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2013-12-19-14/+294
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| * driver: mtd: sf_ops: claim bus while doing memcpyPoddar, Sourav2013-12-19-0/+6
| | | | | | | | | | | | | | | | | | | | claim spi bus while doing memory copy, this will set up the spi controller device control register before doing a memory read. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Yebio Mesfin <ymesfin@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * spi: tegra: clear RDY bit prior to every transferYen Lin2013-12-19-13/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RDY bit indicates that a transfer is complete. This needs to be cleared by SW before every single HW transaction, rather than only at the start of each SW transaction (those being made up of n HW transactions). It seems that earlier HW may have cleared this bit autonomously when starting a new transfer, and hence this code was not needed in practice. However, this is generally a good idea in all cases. In Tegra124, the HW behaviour appears to have changed, and SW must explicitly clear this bit. Otherwise, SW will believe that transfers have completed when they have not, and may e.g. read stale data from the RX FIFO. Signed-off-by: Yen Lin <yelin@nvidia.com> [swarren, rewrote commit description, unified duplicate RDY clearing code and moved it right before the start of the HW transaction, unconditionally exit loop after reading RX data, rather than checking if TX FIFO is empty, since it is guaranteed to be] Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * spi: Add support SH Quad SPI driverNobuhiro Iwamatsu2013-12-18-0/+278
| | | | | | | | | | | | | | | | | | This patch adds a driver for Renesas SoC's Quad SPI bus. This supports with 8 bits per transfer to use with SPI flash. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sf: probe: add support for MX25L2006ELuka Perkov2013-12-18-0/+1
| | | | | | | | | | | | | | Add support for Macronix MX25L2006E SPI flash. Signed-off-by: Luka Perkov <luka@openwrt.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * sf: probe: Hex values are in lower caseLuka Perkov2013-12-18-1/+1
| | | | | | | | | | | | | | | | All other hex values in sf_probe.c are in lower case so we should fix this one too. Signed-off-by: Luka Perkov <luka@openwrt.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-nand-flashTom Rini2013-12-18-48/+62
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| * | mtd: nand: omap: fix ecc ops assignment when changing eccNikita Kiryanov2013-12-17-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we change to software ecc and then back to hardware ecc, the nand ecc ops pointers are populated with incorrect function pointers. This is related to the way nand_scan_tail() handles assigning functions to ecc ops: If we are switching to software ecc/no ecc, it assigns default functions to the ecc ops pointers unconditionally, but if we are switching to hardware ecc, the default hardware ecc functions are assigned to ops pointers only if these pointers are NULL (so that drivers could set their own functions). In the case of omap_gpmc.c driver, when we switch to sw ecc, sw ecc functions are assigned to ecc ops by nand_scan_tail(), and when we later switch to hw ecc, the ecc ops pointers are not NULL, so nand_scan_tail() does not overwrite them with hw ecc functions. The result: sw ecc functions used to write hw ecc data. Clear the ecc ops pointers in omap_gpmc.c when switching ecc types, so that ops which were not assigned by the driver will get the correct default values from nand_scan_tail(). Cc: Scott Wood <scottwood@freescale.com> Cc: Pekon Gupta <pekon@ti.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| * | mtd: nand: omap: fix sw->hw->sw ecc switchNikita Kiryanov2013-12-17-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When switching ecc mode, omap_select_ecc_scheme() assigns the appropriate values into the current nand chip's ecc.layout struct. This is done under the assumption that the struct exists only to store values, so it is OK to overwrite it, but there is at least one situation where this assumption is incorrect: When switching to 1 bit hamming code sw ecc, the job of assigning layout data is outsourced to nand_scan_tail(), which simply assigns into ecc.layout a pointer to an existing struct prefilled with the appropriate values. This struct doubles as both data and layout definition, and therefore shouldn't be overwritten, but on the next switch to hardware ecc, this is exactly what's going to happen. The next time the user switches to software ecc, they're going to get a messed up ecc layout. Prevent this and possible similar bugs by explicitly using the private-to-omap_gpmc.c omap_ecclayout struct when switching ecc mode. Cc: Scott Wood <scottwood@freescale.com> Cc: Pekon Gupta <pekon@ti.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| * | nand_util.c: Use '%zd' for length in nand_unlock debug printTom Rini2013-12-17-1/+1
| | | | | | | | | | | | | | | | | | | | | length is size_t so needs to be '%zd' not '%d' to avoid warnings. Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Tom Rini <trini@ti.com>
| * | mtd: nand: omap: fix HAM1_SW ecc using default value for ecc.sizeNikita Kiryanov2013-12-17-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit "mtd: nand: omap: enable BCH ECC scheme using ELM for generic platform" (d016dc42cedbf6102e100fa9ecb58462edfb14f8) changed the way software ECC is configured, both during boot, and during ecc switch, in a way that is not backwards compatible with older systems: Older version of omap_gpmc.c always assigned ecc.size = 0 when configuring for software ecc, relying on nand_scan_tail() to select a default for ecc.size (256), while the new version of omap_gpmc.c assigns ecc.size = pagesize, which is likely to not be 256. Since 1 bit hamming sw ecc is only meant to be used by legacy devices, revert to the original behavior. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Tom Rini <trini@ti.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Pekon Gupta <pekon@ti.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Pekon Gupta <pekon@ti.com>
| * | mtd: nand: omap_gpmc: cosmetic: Fix indentationStefan Roese2013-12-17-43/+45
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Cc: Pekon Gupta <pekon@ti.com> Cc: Scott Wood <scottwood@freescale.com> [scottwood@freescale.com: wrap some long lines] Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | mtd: nand: omap: fix ecc-layout for HAM1 ecc-schemepekon gupta2013-12-17-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per OMAP3530 TRM referenced below [1] For large-page NAND, ROM code expects following ecc-layout for HAM1 ecc-scheme - OOB[1] (offset of 1 *byte* from start of OOB) for x8 NAND device - OOB[2] (offset of 1 *word* from start of OOB) for x16 NAND device Thus ecc-layout expected by ROM code for HAM1 ecc-scheme is: *for x8 NAND Device* +--------+---------+---------+---------+---------+---------+---------+ | xxxx | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] | ... +--------+---------+---------+---------+---------+---------+---------+ *for x16 NAND Device* +--------+--------+---------+---------+---------+---------+---------+---------+ | xxxxx | xxxxx | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] | +--------+--------+---------+---------+---------+---------+---------+---------+ This patch fixes ecc-layout *only* for HAM1, as required by ROM-code For other ecc-schemes like (BCH8) ecc-layout is same for x8 or x16 devices. [1] OMAP3530: http://www.ti.com/product/omap3530 TRM: http://www.ti.com/litv/pdf/spruf98x Chapter-25: Initialization Sub-topic: Memory Booting Section: 25.4.7.4 NAND Figure 25-19. ECC Locations in NAND Spare Areas Reported-by: Stefan Roese <sr@denx.de> Signed-off-by: Pekon Gupta <pekon@ti.com> Tested-by: Stefan Roese <sr@denx.de>
* | | usb: ehci: Fix register accessMarek Vasut2013-12-18-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Fix the register access in EHCI HCD. We need to use address of the register as an ehci_writel() argument. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org>
* | | usb: ehci: Do not de-init uninited controllersMarek Vasut2013-12-18-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | In case the controller is not initialized, we shall not de-initialize it. As the control structure will not be filled, we will produce a null ptr dereference if the controller is not inited. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org>
* | | usb: ehci-pci: Clarify and cleanup the EHCI controller detectionMarek Vasut2013-12-18-3/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | The detection function of the EHCI PCI controller was really cryptic, add a beefy comment and clean the portion of the code up a bit. No change in the logic of the code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org>
* | | usb: f_dfu: cosmetic: Code cleanupLukasz Majewski2013-12-18-2/+2
| | | | | | | | | | | | | | | | | | Code cleanup for dfu_bind_config function Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
* | | usb: dfu: f_dfu: Provide infrastructure to adjust DFU's Poll Timeout valueLukasz Majewski2013-12-18-3/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is necessary to deter the host from sending subsequent DFU_GETSTATUS request in the case of e.g. writing the buffer to medium. Here the timeout is increased when we fill up the whole buffer. This delay allows eMMC memory to perform its internal operations. Otherwise we end up with HOST's error regarding GET_STATUS receive timeout. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
* | | dfu: Export allocated dfu buffer sizeLukasz Majewski2013-12-18-0/+5
| |/ |/| | | | | | | | | | | The method for exporting size of allocated buffer is provided. It is afterwards used by USB's dfu function code. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
* | serial_sh: add support for SH7753Yoshihiro Shimoda2013-12-18-1/+3
| | | | | | | | | | Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | net: sh-eth: add support for SH7753Yoshihiro Shimoda2013-12-18-2/+6
|/ | | | | | | | SH7753 has two fast ethernet controllers and two gigabit ethernet controllers. It is similar to SH7757. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini2013-12-16-1/+1
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| * video: ipu_disp: Return a negative value on errorFabio Estevam2013-12-04-1/+1
| | | | | | | | | | | | We should return a negative error number (-EINVAL) on error. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | drivers/mtd: descend into sub directories only when it is necessaryMasahiro Yamada2013-12-13-6/+0
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | drivers/usb/gadget: select objects by obj-$(CONFIG-...)Masahiro Yamada2013-12-13-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | Before switching to the real Kbuild, drivers/usb/gadget/Makefile must be fixed. If none of CONFIG_USB_GADGET, CONFIG_USB_ETHER, CONFIG_USB_DEVICE is defined, both obj- and obj-y get empty. We need non-empty obj- or obj-y on each Makefile to generate built-in.o on the real Kbuild. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | serial: lpc32xx: send CR before LFVladimir Zapolskiy2013-12-13-0/+3
| | | | | | | | | | | | | | | | | | | | For LPC32XX high-speed UART it is required to send a carriage return symbol along with line feed. The problem was introduced in e503f90a commit. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de>
* | net/fman: add ft_fixup_xgec to support 3rd and 4th 10GECShengzhou Liu2013-12-11-1/+52
| | | | | | | | | | | | | | | | | | As mEMAC1 and mEMAC2 are dual-role MACs, which are used as 1G or 10G MAC. So we update dynamically 'cell-index' to '2' and '3' for 10GEC3 and 10GEC4. Also change 'fsl,fman-port-1g-rx' to 'fsl,fman-port-10g-rx', ditto for Tx. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-12-10-72/+193
|\ \ | | | | | | | | | | | | | | | | | | | | | Conflicts: board/samsung/trats2/trats2.c include/configs/exynos5250-dt.h Signed-off-by: Tom Rini <trini@ti.com>
| * \ Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-12-10-1240/+10471
| |\ \ | | |/ | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/cpu/armv7/rmobile/Makefile doc/README.scrapyard Needed manual fix: arch/arm/cpu/armv7/omap-common/Makefile board/compulab/cm_t335/u-boot.lds
| * | serial: zynq: Remove unused #definesSoren Brinkmann2013-12-10-4/+0
| | | | | | | | | | | | | | | Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | at91: nand: switch atmel_nand to generic GPIO APIAndreas Bießmann2013-12-09-5/+3
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Jens Scharsig (BuS Elektronik)<esw@bus-elektronik.de> Tested-by: Jens Scharsig (BuS Elektronik)<esw@bus-elektronik.de> Acked-by: Scott Wood <scottwood@freescale.com>
| * | at91: add new gpio pin definitionsAndreas Bießmann2013-12-09-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | This patch define new names for GPIO pins on at91 devices. Follow up patches will convert the whole infrastructure to use these new definitions. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Tested-by: Bo Shen <voice.shen@atmel.com>
| * | Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2013-12-06-2/+12
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| | * | driver:usb:s3c_udc: add support for Exynos4x12Piotr Wilczek2013-12-02-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add new defines for usb phy for Exynos4x12. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | usb: ehci-omap: Reset the USB Host OMAP moduleRoger Quadros2013-12-06-15/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit bb1f327 we removed the UHH reset to fix NFS root (over usb ethernet) problems with Beagleboard (3530 ES1.0). However, this seems to cause USB detection problems for Pandaboard, about (3/8). On further investigation, it seems that doing the UHH reset is not the cause of the original Beagleboard problem, but in the way the reset was done. This patch adds proper UHH RESET mechanism for OMAP3 and OMAP4/5 based on the UHH_REVISION register. This should fix the Beagleboard NFS problem as well as the Pandaboard USB detection problem. Reported-by: Tomi Valkeinen <tomi.valkeinen@ti.com> CC: Stefan Roese <sr@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Roger Quadros <rogerq@ti.com>
| * | | am335x: cpsw: optimize cpsw_recv to increase network performanceVladimir Koutny2013-12-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In 48ec5291, only TX path was optimized; this does the same also for RX path. This results in huge increase of TFTP throughput on custom am3352 board (from 312KiB/s to 1.8MiB/s) and eliminates occasional transfer timeouts. Signed-off-by: Vladimir Koutny <vladimir.koutny@streamunlimited.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Tom Rini <trini@ti.com>
| * | | ahci: Fix cache align error messagesRoger Quadros2013-12-04-7/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Align the ATA ID buffer to the cache-line boundary. This gets rid of the below error mesages on ARM v7 platforms. scanning bus for devices... ERROR: v7_dcache_inval_range - start address is not aligned - 0xfee48618 ERROR: v7_dcache_inval_range - stop address is not aligned - 0xfee48818 CC: Aneesh V <aneesh@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com>
| * | | ahci: Error out with message on malloc() failureRoger Quadros2013-12-04-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If malloc() fails, we don't want to continue in ahci_init() and ahci_init_one(). Also print a more informative error message on malloc() failures. CC: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Roger Quadros <rogerq@ti.com>
| * | | ARMV7: OMAP4: Add twl6032 supportOleg Kosheliev2013-12-04-6/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added chip type detection and twl6032 support in the battery control and charge functions. Based on Balaji T K <balajitk@ti.com> patches for TI u-boot. Signed-off-by: Oleg Kosheliev <oleg.kosheliev@ti.com>
| * | | ARMV7: OMAP4: Add struct for twl603x dataOleg Kosheliev2013-12-04-5/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The data struct is used to support different PMIC chip types. It contains the chip type and the data (e.g. registers addresses, adc multiplier) which is different for twl6030 and twl6032. Replaced some hardcoded values with the structure vars. Based on Balaji T K <balajitk@ti.com> patches for TI u-boot. Signed-off-by: Oleg Kosheliev <oleg.kosheliev@ti.com>
| * | | net: remove unused CONFIG_AT91_LEGACYAndreas Bießmann2013-11-13-9/+0
| | | | | | | | | | | | | | | | Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | | i2c: switch from AT91 legacy to ATMEL legacyAndreas Bießmann2013-11-13-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the required API is gpio which is enclosed with CONFIG_ATMEL_LEGACY use that switch here. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Heiko Schocher <hs@denx.de>
| * | | video: remove AT91 legacy API from bus_vcxkAndreas Bießmann2013-11-13-15/+0
| |/ / | | | | | | | | | | | | | | | Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de> Acked-by: Anatolij Gustschin <agust@denx.de>
| * | usb, g_dnl: make bcdDevice value configurableHeiko Schocher2013-11-12-4/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add the possibility to set the bcdDevice number board specific. Therefore the weak function g_dnl_get_board_bcd_device_number() is introduced. Used on the siemens boards. Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Kyungmin Park <kyungmin.park@samsung.com>
| * | am33xx: Make SoC bootcount driver have its own symbolTom Rini2013-11-11-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some am33xx boards may not use the RTC block for bootcount (as it may not be wired up for the board) and use some other facility. So add another symbol for the bootcount driver for the IP block. Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Rini <trini@ti.com>
| * | bootcount: store bootcount var in environmentHeiko Schocher2013-11-11-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If no softreset save registers are found on the hardware "bootcount" is stored in the environment. To prevent a saveenv on all reboots, the environment variable "upgrade_available" is introduced. If "upgrade_available" is 0, "bootcount" is always 0 therefore no need to save the environment on u-boot boot, if "upgrade_available" is 1 "bootcount" is incremented in the environment and environment gets written on u-boot start. So the Userspace Applikation must set the "upgrade_available" and "bootcount" variable to 0 (for example with fw_setenv), if a boot was successfully. Signed-off-by: Heiko Schocher <hs@denx.de>
* | | Merge branch 'spi' of git://git.denx.de/u-boot-x86Tom Rini2013-12-10-12/+738
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