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* arm: vf610: Add QSPI driver supportAlison Wang2014-06-09-0/+610
| | | | | | | Add Freescale QSPI driver support for VF610. Signed-off-by: Alison Wang <Huan.Wang@freescale.com> Signed-off-by: Chao Fu <b44548@freescale.com>
* power: Add support for the TPS65218 PMICTom Rini2014-06-06-0/+98
| | | | | | | Add a driver for the TPS65218 PMIC which is used by TI AM43xx SoCs and may be used by TI AM335x SoCs. Signed-off-by: Tom Rini <trini@ti.com>
* ti: qspi: populate slave device to set flash quad bit.Sourav Poddar2014-06-06-0/+1
| | | | | | | The patch populates the slave data which will be used by flash driver to set the flash quad enable bit. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
* mtd: nand: omap: add support for BCH16_ECC - NAND driver updatespekon gupta2014-06-06-1/+78
| | | | | | | | | | | | | | | | | | This patch add support for BCH16_ECC to omap_gpmc driver. *need to BCH16 ECC scheme* With newer SLC Flash technologies and MLC NAND, and large densities, pagesizes Flash devices have become more suspectible to bit-flips. Thus stronger ECC schemes are required for protecting the data. But stronger ECC schemes have come with larger-sized ECC syndromes which require more space in OOB/Spare. This puts constrains like; (a) BCH16_ECC can correct 16 bit-flips per 512Bytes of data. (b) BCH16_ECC generates 26-bytes of ECC syndrome / 512B. Due to (b) this scheme can only be used with NAND devices which have enough OOB to satisfy following equation: OOBsize per page >= 26 * (page-size / 512) Signed-off-by: Pekon Gupta <pekon@ti.com>
* mtd: nand: omap: add CONFIG_SYS_NAND_BUSWIDTH_16BIT to indicate NAND device ↵pekon gupta2014-06-06-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | bus-width GPMC controller needs to be configured based on bus-width of the NAND device connected to it. Also, dynamic detection of NAND bus-width from on-chip ONFI parameters is not possible in following situations: SPL: SPL NAND drivers does not support ONFI parameter reading. U-boot: GPMC controller iniitalization is done in omap_gpmc.c:board_nand_init() which is called before probing for devices, hence any ONFI parameter information is not available during GPMC initialization. Thus, OMAP NAND driver expected board developers to explicitely write GPMC configurations specific to NAND device attached on board in board files itself. But this was troublesome for board manufacturers as they need to dive into lengthy platform & SoC documents to find details of GPMC registers and appropriate configurations to get NAND device working. This patch instead adds existing CONFIG_SYS_NAND_BUSWIDTH_16BIT to board config hich indicates that connected NAND device has x16 bus-width. And then based on this config GPMC driver itself initializes itself based on NAND bus-width. This keeps board developers free from knowing GPMC controller specific internals. Signed-off-by: Pekon Gupta <pekon@ti.com>
* mtd: nand: force NAND_CMD_READID onto 8-bit busBrian Norris2014-06-06-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per following Sections in ONFI Spec, NAND_CMD_READID should use only lower 8-bit for transfering command, address and data even on x16 NAND device. *Section: Target Initialization" "The Read ID and Read Parameter Page commands only use the lower 8-bits of the data bus. The host shall not issue commands that use a word data width on x16 devices until the host determines the device supports a 16-bit data bus width in the parameter page." *Section: Bus Width Requirements* "When the host supports a 16-bit bus width, only data is transferred at the 16-bit width. All address and command line transfers shall use only the lower 8-bits of the data bus. During command transfers, the host may place any value on the upper 8-bits of the data bus. During address transfers, the host shall set the upper 8-bits of the data bus to 00h." Thus porting following commit from linux-kernel to ensure that column address is not altered to align to x16 bus when issuing NAND_CMD_READID command. commit 3dad2344e92c6e1aeae42df1c4824f307c51bcc7 mtd: nand: force NAND_CMD_READID onto 8-bit bus Author: Brian Norris <computersforpeace@gmail.com> (preserving authorship) The NAND command helpers tend to automatically shift the column address for x16 bus devices, since most commands expect a word address, not a byte address. The Read ID command, however, expects an 8-bit address (i.e., 0x00, 0x20, or 0x40 should not be translated to 0x00, 0x10, or 0x20). This fixes the column address for a few drivers which imitate the nand_base defaults. Signed-off-by: Pekon Gupta <pekon@ti.com>
* mtd: nand: don't use read_buf for 8-bit ONFI transfersBrian Norris2014-06-06-2/+3
| | | | | | | | | | | | | | | | | | | | | | Porting below commit from linux-tree, preserving original authorship & commit log commit bd9c6e99b58255b9de1982711ac9487c9a2f18be Author: Brian Norris <computersforpeace@gmail.com> mtd: nand: don't use read_buf for 8-bit ONFI transfers Use a repeated read_byte() instead of read_buf(), since for x16 buswidth devices, we need to avoid the upper I/O[16:9] bits. See the following commit for reference: commit 05f7835975dad6b3b517f9e23415985e648fb875 (from linux-tree) Author: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Date: Thu Dec 5 22:22:04 2013 +0100 mtd: nand: don't use {read,write}_buf for 8-bit transfers Now, I think that all barriers to probing ONFI on x16 devices are removed, so remove the check from nand_flash_detect_onfi(). Signed-off-by: Pekon Gupta <pekon@ti.com>
* mtd: nand: omap: fix error-codes returned from omap-elm driverpekon gupta2014-06-06-6/+9
| | | | | | | | | | | This patch omap-elm.c: replaces -ve integer value returned during errorneous condition, with proper error-codes. omap-gpmc.c: updates omap-gpmc driver to pass error-codes returned from omap-elm driver to upper layers Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
* mtd: nand: omap_gpmc: minor cleanup of omap_correct_data_bchpekon gupta2014-06-06-5/+5
| | | | | | | | This patch tries to avoid some local pointer dereferences, by using common local variables in omap_correct_data_bch() Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
* mtd: nand: omap_gpmc: rename struct nand_bch_priv to struct omap_nand_infopekon gupta2014-06-06-32/+26
| | | | | | | | | This patch renames 'struct nand_bch_priv' which currently holds private data only for BCH ECC schemes, into 'struct omap_nand_info' so that same can be used for all ECC schemes Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
* mtd: nand: omap_gpmc: remove unused members of 'struct nand_bch_priv'pekon gupta2014-06-06-17/+6
| | | | | | | | | | This patch prepares to refactor 'struct nand_bch_priv' -> 'struct omap_nand_info' And thus performs following clean-ups: - remove nand_bch_priv.type: use nand_bch_priv.ecc_scheme instead - remove nand_bch_priv.mode: <unused> Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
* mtd: nand: omap_elm: use bch_type instead of nibble count to differentiate ↵pekon gupta2014-06-06-20/+10
| | | | | | | | | | | | | | | | | | | between BCH4/BCH8/BCH16 ELM hardware engine support ECC error detection for multiple ECC strengths like +------+------------------------+ |Type | ECC syndrome length | +------+------------------------+ |BCH4 | 6.5 bytes = 13 nibbles | |BCH8 | 13 byte = 26 nibbles | |BCH16 | 26 bytes = 52 nibbles | +------+------------------------+ Current implementation of omap_elm driver uses ECC syndrom length (in 'nibbles') to differentiate between BCH4/BCH8/BCH16. This patch replaces it with 'bch_type' Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
* mtd: nand: omap_elm: remove #include omap_gpmc.hpekon gupta2014-06-06-1/+0
| | | | | | | There is no dependency of omap_elm.c on omap_gpmc.h Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
* Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2014-06-02-111/+495
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| * power: Explicitly select pmic device's busAaron Durbin2014-05-28-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | The current pmic i2c code assumes the current i2c bus is the same as the pmic device's bus. There is nothing ensuring that to be true. Therefore, select the proper bus before performing a transaction. Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * power: Add support for TPS65090 PMU chip.Tom Wai-Hong Tam2014-05-28-0/+311
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds driver support for the TPS65090 PMU. Support includes hooking into the pmic infrastructure so that the pmic commands can be used on the console. The TPS65090 supports the following functionality: - fet enable/disable/querying - getting and setting of charge state Even though it is connected to the pmic infrastructure it does not hook into the pmic charging charging infrastructure. The device tree binding is from Linux, but only a small subset of functionality is supported. Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org> Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Katie Roberts-Hoffman <katierh@chromium.org> Signed-off-by: Rong Chang <rongchang@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * power: Add PMIC_ prefix to CHARGER_EN/DISABLESimon Glass2014-05-28-5/+5
| | | | | | | | | | | | | | | | This enum should be common across all PMICs rather than having it independently defined with the same name in multiple places. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * power: Rename CONFIG_PMIC_... to CONFIG_POWER_...Simon Glass2014-05-28-3/+3
| | | | | | | | | | | | | | | | | | Commit be3b51aa did this mostly, but several have been added since. Do the job again. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * mmc: s5p_sdhci: add the s5p_sdhci_core_init functionJaehoon Chung2014-05-16-25/+17
| | | | | | | | | | | | | | | | | | | | | | To reuse the code, added the s5p_sdhci_core_init function. Before applied this patch, didn't use the 8-bit mode at exynos baord. Because it didn't set "MMC_MODE_8BIT". Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * mmc: exynos_dw_mmc: enable the DDR modeJaehoon Chung2014-05-16-0/+1
| | | | | | | | | | | | | | | | | | Set the ddr mode capability by default. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * mmc: dw_mmc: support the DDR modeJaehoon Chung2014-05-16-2/+10
| | | | | | | | | | | | | | | | | | Support the DDR mode at dw-mmc controller Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * mmc: support the DDR mode for eMMCJaehoon Chung2014-05-16-3/+13
| | | | | | | | | | | | | | Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * mmc: remove the unnecessary define and fix the wrong bit controlJaehoon Chung2014-05-16-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Lukasz Majeski <l.majewski@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * mmc: exynos_dw_mmc: restore the property into hostJaehoon Chung2014-05-16-73/+131
| | | | | | | | | | | | | | | | | | | | Restore the platdata(property of dt) into host struct. Then data's information is maintained and reused anywhere. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | mmc: atmel_mci: fix print incorrect buffer content for debugWu, Josh2014-05-27-2/+3
| | | | | | | | | | | | Signed-off-by: Josh Wu <josh.wu@atmel.com> [fix checkpatch line length warning] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | gpio: at91: add sanity check for the NULL pointerWu, Josh2014-05-27-1/+2
| | | | | | | | | | | | | | | | | | | | We need check the NULL pointer as at91_pio_get_port() may return NULL. Also print a error message when at91_pio_get_port() failed otherwise we cannot notice the failure. Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | net/designware: Make DMA burst length configurable and reduce by defaultIan Campbell2014-05-25-7/+7
| | | | | | | | | | | | | | | | | | | | | | The correct value for this setting can vary across SoCs and boards, so make it configurable. Also reduce the default value to 8, which is the same default as used in the Linux driver. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Cc: Alexey Brodkin <abrodkin@synopsys.com>
* | net/designware: reorder struct dw_eth_dev to pack more efficiently.Ian Campbell2014-05-25-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Thu, 2014-05-08 at 22:26 +0100, Ian Campbell wrote: > The {r,t}xbuffs fields also need to be aligned. Previously this was done > implicitly because they immediately followed the descriptor tables. Make this > explicit and also move to the head of the struct. Looks like I managed to not actually commit the move of the field to the head of the struct! v3.1 follows.... Ian. 8<------------ >From 2937ba01841887317f6792709ed57cb86b5fc0cd Mon Sep 17 00:00:00 2001 From: Ian Campbell <ijc@hellion.org.uk> Date: Thu, 1 May 2014 19:45:15 +0100 Subject: [PATCH] net/designware: reorder struct dw_eth_dev to pack more efficiently. The {tx,rx}_mac_descrtable fields are aligned to ARCH_DMA_MINALIGN, which could be 256 or even larger. That means there is a potentially huge hole in the struct before those fields, so move them to the front where they are better packed. Moving them to the front also helps ensure that so long as dw_eth_dev is properly aligned (which it is since "net/designware: ensure device private data is DMA aligned.") the {tx,rx}_mac_descrtable will be too, or at least avoids having to worry too much about compiler specifics. The {r,t}xbuffs fields also need to be aligned. Previously this was done implicitly because they immediately followed the descriptor tables. Make this explicit and also move to the head of the struct. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Cc: Alexey Brodkin <abrodkin@synopsys.com> Tested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
* | net/designware: ensure cache invalidations are aligned to ARCH_DMA_MINALIGNIan Campbell2014-05-25-5/+13
| | | | | | | | | | | | | | | | | | | | | | This is required at least on ARM. When sending instead of simply invalidating the entire descriptor, flush as little as possible while still respecting ARCH_DMA_MINALIGN, as requested by Alexey. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Cc: Alexey Brodkin <abrodkin@synopsys.com>
* | net/designware: ensure device private data is DMA aligned.Ian Campbell2014-05-25-1/+2
| | | | | | | | | | | | | | | | | | | | struct dw_eth_dev contains fields which are accessed via DMA, so make sure it is aligned to a dma boundary. Without this I see: ERROR: v7_dcache_inval_range - start address is not aligned - 0x7fb677e0 Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Alexey Brodkin <abrodkin@synopsys.com> Acked-by: Marek Vasut <marex@denx.de>
* | sunxi: mmc supportIan Campbell2014-05-25-0/+504
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Mon, 2014-05-05 at 14:18 +0200, Stefan Roese wrote: > > + case 1: > > +#if CONFIG_MMC1_PG > Are you sure that this is correct and shouldn't be: > > +#ifdef CONFIG_MMC1_PG > > ? It's "correct" in so far as it works (the boards.cfg config stuff #defines things to 1), but I think you are right that it isn't the preferred style. But... > A quick scan through this patch series shows that this define > is not set at all. Perhaps its outdated? Or is it used to support > some other sunxi SoC? Not sure, perhaps it should be removed for > now. ...I had thought that it was to support some other board which wasn't being upstreamed right now, so eventually useful and harmless for now, but I've just checked and it isn't actually used by any of the boards in u-boot-sunxi.git. So rather than fix it to use #ifdef lets drop it. Rather than resend the entire series, here is v5.1 of this patch. > Other than this please add my: > > Reviewed-by: Stefan Roese <sr@denx.de> Thanks! 8<--------------------------------- >From 20704e35a41664de5f516ed0e02981ac06085102 Mon Sep 17 00:00:00 2001 From: Ian Campbell <ijc@hellion.org.uk> Date: Fri, 7 Mar 2014 04:29:39 +0000 Subject: [PATCH v5.1 7/8] sunxi: mmc support This adds support for the MMC controller on the Allwinner A20 (sun7i) processor. Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net> Signed-off-by: Luke Leighton <lkcl@lkcl.net> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Wills Wang <wills.wang.open@gmail.com> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Tom Cubie <Mr.hipboi@gmail.com> Cc: Aaron Maoye <leafy.myeh@allwinnertech.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Reviewed-by: Tom Rini <trini@ti.com>
* | Merge branch 'u-boot-microblaze/zynq' into 'u-boot-arm/master'Albert ARIBAUD2014-05-23-0/+105
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| * | ARM: zynq: ehci: Added USB host driver supportMichal Simek2014-05-14-0/+105
| | | | | | | | | | | | | | | | | | | | | Added USB host driver for zynq. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | esdhc/usdhc: Fix warning when CONFIG_SYS_FSL_ESDHC_USE_PIO is not setTom Rini2014-05-23-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | In 7168977 we made calls to check_and_invalidate_dcache_range() conditional on !CONFIG_SYS_FSL_ESDHC_USE_PIO. Only define this function in this case as well. Signed-off-by: Tom Rini <trini@ti.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mmcTom Rini2014-05-23-16/+366
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| * | | mmc: provide a select_hwpart implementation for get_device()Stephen Warren2014-05-23-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This enables specifying which eMMC HW partition to target for any U-Boot command that uses the generic get_partition() function to parse its command-line arguments. Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | eMMC: add support for operations in RPMB partitionPierre Aubert2014-05-23-0/+324
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds functions for read, write and authentication key programming for the Replay Protected Memory Block partition in the eMMC. Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Signed-off-by: Pierre Aubert <p.aubert@staubli.com>
| * | | mmc: Handle switch error status bit in MMC card statusAndrew Gabbasov2014-05-23-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MMC switch command for unsupported feature (e.g. bus width) sets a switch error bit in card status. This bit should be checked, and, if it's set, no access with new controller settings should be performed. Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
| * | | mmc: postponed needless timer initializationMateusz Zalega2014-05-23-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mmc_init() doesn't call get_timer() anymore if MMC is already initialized. <panto> Minor formatting fix. Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Signed-off-by: Mateusz Zalega <m.zalega@samsung.com>
| * | | esdhc/usdhc: Fix PIO mode bug in fsl_esdhc driverYe.Li2014-05-22-14/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When configure the fsl_esdhc driver to PIO mode by defining "CONFIG_SYS_FSL_ESDHC_USE_PIO", the SD/MMC read and write will fail. Two bugs in the driver to cause the issue: 1. The read buffer was invalidated after reading from DATAPORT register, which should be only applied to DMA mode. The valid data in cache was overwritten by physical memory. 2. The watermarks are not set in PIO mode, will cause according state not be set. Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* | | | Merge branch 'fpga' of git://www.denx.de/git/u-boot-microblazeTom Rini2014-05-22-23/+153
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| * | | | fpga: Added support to load bit stream from SD/MMCSiva Durga Prasad Paladugu2014-05-20-0/+129
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added support to load a bitstream image in chunks by reading it in chunks from SD/MMC. Command format: loadfs [dev] [address] [image size] [blocksize] <interface> [<dev[:part]>] <filename> Example: fpga loadfs 0 1000000 3dbafc 4000 mmc 0 fpga.bin Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | fpga: zynqpl: Clean partial bitstream handlingMichal Simek2014-05-20-12/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not do partial bitstream detection based on bitstream size and use bitstream_type argument which is passed from the fpga core. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | fpga: Define bitstream type based on command selectionMichal Simek2014-05-20-12/+19
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clean up partial, full and compressed bitstream handling. U-Boot supports full bitstream loading and partial based on detection which is not 100% correct. Extending fpga_load/fpga_loadbitstream() with one more argument which stores bitstream type. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-05-22-40/+356
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| * \ \ \ Merge remote-tracking branch 'u-boot/master'Albert ARIBAUD2014-05-20-369/+344
| |\ \ \ \ | | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: boards.cfg Conflicts were trivial once u-boot-arm/master boards.cfg was reformatted (commit 6130c146) to match u-boot/master's own reformatting (commit 1b37fa83).
| * | | | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-05-16-1/+156
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| | * \ \ \ Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic2014-05-15-3159/+2638
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| | * | | | | video: Add support for imx25 lcd controllerThomas Diener2014-05-09-0/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the imx25 lcd display controller. Signed-off-by: Thomas Diener <dietho@gmx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
| | * | | | | power: Add support for LTC3676 PMICTim Harvey2014-05-09-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LTC3676 PMIC includes four DC/DC converters, and three 300mA LDO Regulators (two Adjustable). The DC/DC converters are adjustable based on a resistor devider (board-specific). This adds support for the LTC3676 by creating a namespace unique init function that uses the PMIC API to allocate a pmic and defines the registers. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Acked-by: Stefano Babic <sbabic@denx.de>
generated by cgit v1.1 at 2024-07-17 05:11:40 +0000