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* usb: eth: add ASIX AX88179 DRIVERRene Griessl2014-12-31-0/+708
| | | | | | | | | | This patch adds driver support for the ASIX AX88179 USB3.0 to GbE network adapter. Driver has been tested on the RECS5250 COM module (similar to ARDALE5250). Testcase was DHCP and PXE boot. Signed-off-by: Rene Griessl <rgriessl@cit-ec.uni-bielefeld.de>
* Merge git://git.denx.de/u-boot-x86Tom Rini2014-12-19-15/+19
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| * x86: Rename coreboot-serial to x86-serialBin Meng2014-12-18-7/+7
| | | | | | | | | | Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: ich6-gpio: Add Intel Tunnel Creek GPIO supportBin Meng2014-12-18-8/+12
| | | | | | | | | | | | | | | | | | | | | | | | Intel Tunnel Creek GPIO register block is compatible with current ich6-gpio driver, except the offset and content of GPIO block base address register in the LPC PCI configuration space are different. Use u16 instead of u32 to store the 16-bit I/O address of the GPIO registers so that it could support both Ivybridge and Tunnel Creek. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2014-12-18-23/+59
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| * dfu: dfu_get_buf: check the value of env dfu_bufsiz before usePrzemyslaw Marczak2014-12-18-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In function dfu_get_buf(), the size of allocated buffer could be defined by the env variable. The size from this variable was passed for memalign() without checking its value. And the the memalign will return non null pointer for size 0. This could possibly cause data abort, so now the value of var is checked before use. And if this variable is set to 0 then the default size will be used. This commit also changes the base passed to simple_strtoul() to 0. Now decimal and hex values can be used for the variable dfu_bufsiz. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [TestHW: Exynos4412-Trats2]
| * gadget: f_thor: check pointers before use in download_tail()Przemyslaw Marczak2014-12-18-2/+14
| | | | | | | | | | | | | | | | | | | | Some pointers in function download_tail() were not checked before the use. This could possibly cause the data abort. To avoid this, check if the pointers are not null is added. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [TestHW: Exynos4412-Trats2]
| * dfu: mmc: check if mmc device exists in mmc_block_op()Przemyslaw Marczak2014-12-18-1/+7
| | | | | | | | | | | | | | | | | | | | | | The function mmc_block_op() is the last function before the physicall data write, but the mmc device pointer is not checked. If mmc device not exists, then data abort will occur. To avoid this, first the mmc device pointer is checked. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [TestHW: Exynos4412-Trats2]
| * fastboot: add support for continue commandRob Herring2014-12-18-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | The fastboot continue command is defined to exit fastboot and continue autoboot. This commit implements the continue command and the exiting of fastboot only. Subsequent u-boot commands can be processed after exiting fastboot. Autoboot should implement a boot script such as "fastboot; mmc read <...>; bootm" to fully implement the fastboot continue function. Signed-off-by: Rob Herring <robh@kernel.org> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [TestHW: Exynos4412-Trats2]
| * usb, g_dnl: generalize DFU detach functionsRob Herring2014-12-18-17/+18
| | | | | | | | | | | | | | | | | | In order to add detach functions for fastboot, make the DFU detach related functions common so they can be shared. Signed-off-by: Rob Herring <robh@kernel.org> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [TestHW: Exynos4412-Trats2]
| * USB: gadget: atmel_usba_udc: fix transfer hang issueBo Shen2014-12-16-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | When receive data, the RXRDY in status register set by hardware after a new packet has been stored in the endpoint FIFO. After, we copy from FIFO, we clear it, make the FIFO can be accessed again. In the receive_data() function, this bit RXRDY has been cleared. So, after the receive_data() function return, this bit should not be cleared again, or else it will cause the accessing FIFO corrupt, which will make the data loss. Signed-off-by: Bo Shen <voice.shen@atmel.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-12-16-7/+48
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| * | qe/deep-sleep: modify qe deep-sleep for generic boardZhao Qiang2014-12-15-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | Deep sleep for generic board is supported now, modify qe deep-sleep code to adapt it. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | crypto/fsl: Fix RNG instantiation failure.gaurav rana2014-12-15-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Corrected the order of arguments in memset in run_descriptor function. Wrong order of argumnets led to improper initialization of members of struct type result. This resulted in RNG instantiation error. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | net/fm: update ft_fixup_port to differentiate dual-role macShengzhou Liu2014-12-15-5/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | we need to differentiate dual-role MACs into two types: MACs with 10GEC enumeration consistent with DTSEC enumeration(defined by CONFIG_FSL_FM_10GEC_REGULAR_NOTATION) and other MACs without CONFIG_FSL_FM_10GEC_REGULAR_NOTATION defined. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | driver/ddr/fsl: Fix MRC_CYC calculation for DDR3York Sun2014-12-15-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For DDR controller version 4.7 or newer, MRC_CYC (mode register set cycle time) is max(tMRD, tMOD). tMRD is 4nCK, or 8nCK (RDIMM). tMOD is max(12nCK, 15ns) according to JEDEC spec. DDR4 is not affected by this change. Signed-off-by: York Sun <yorksun@freescale.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2014-12-16-0/+1747
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| * | spi: designware_spi: Some fixes / changesStefan Roese2014-12-06-19/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As suggested by Pavel, here some fixes to the designware SPI driver: - Spelling fixes - Comment for timeout added - Removed n_bytes completely (bits_per_word is enough for this) - Unput clock now not defined via macro. The function to get the clock value is now called directly from within the driver Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | spi: Add designware master SPI DM driver used on SoCFPGAStefan Roese2014-12-06-0/+426
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the driver for the Designware master SPI controller. This IP core is integrated on the Altera SoCFPGA. This implementation is a driver model (DM) implementation. So multiple SPI drivers can be used. Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller used to connect the SPI NOR flashes. Without DM, using multiple SPI drivers is not possible. This driver is very loosely based on the Linux driver. Most of the Linux driver is removed. Only the polling loop for the transfer is really used from this driver, as we don't support interrupts and DMA right now. This is tested on the SoCrates SoCFPGA board using the SPI pins on the P14 header. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | spi: Add Cadence QSPI DM driver used by SoCFPGAStefan Roese2014-12-06-0/+1320
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver is cloned from the Altera Rockerboard.org U-Boot repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some modification to support the U-Boot driver model (DM). As mentioned above, in this new version I ported this driver to the new driver model (DM). One big advantage of this move is that now multiple SPI drivers can be enabled on one platform. And since the SoCFPGA also has the Designware SPI master controller integrated, this feature is really needed to support both controllers. Because of this, this series needs the DT support for SoCFPGA to be applied. For DT based probing in the SPI DM. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | | Merge git://git.denx.de/u-boot-x86Tom Rini2014-12-15-129/+157
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| * | | x86: ich-spi: Add Intel Tunnel Creek SPI controller supportBin Meng2014-12-13-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Intel Tunnel Creek SPI controller support which is an ICH7 compatible device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | x86: Add a simple superio driver for SMSC LPC47MBin Meng2014-12-13-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8) are provided by a superio chip connected to the LPC bus. We must program the superio chip so that serial ports are available for us. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | x86: ich6-gpio: Move setup_pch_gpios() to board support codesBin Meng2014-12-13-51/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Movie setup_pch_gpios() in the ich6-gpio driver to the board support codes, so that the driver does not need to know any platform specific stuff (ie: include the platform specifc chipset header file). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | x86: ich-spi: Set the tx operation mode for ich 7Bin Meng2014-12-13-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ICH 7 SPI controller only supports byte program (02h) for SST flash. Word program (ADh) is not supported. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | | x86: ich-spi: Set the rx operation mode for ich 7Bin Meng2014-12-13-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ICH 7 SPI controller only supports array read command (03h). Fast array read command (0Bh) is not supported. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | | sf: Enable byte program supportJagannadha Sutradharudu Teki2014-12-13-12/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enabled byte program support for sst flashes in sf. Few controllers will only support BP, so this patch gives a tx transfer flag to set the BP so-that sf will operate on byte program transfer. A new TX operation mode SPI_OPM_TX_BP is introduced for such SPI controller to use byte program op for SST flash. Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * | | spi: sf: Support byte program for sst spi flashBin Meng2014-12-13-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently if SST flash advertises SST_WP flag in the params table the word program command (ADh) with auto address increment will be used for the flash write op. However some SPI controllers do not support the word program command (like the Intel ICH 7), the byte programm command (02h) has to be used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | | spi: Fix flag collision for SST_WPSimon Glass2014-12-13-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present SECT_4K is the same as SST_WP so we cannot tell these apart. Fix this so that the table in sf_params.c can be used correctly. Reported-by: Jens Rottmann <Jens.Rottmann@adlinktech.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | | sf: Fix look for the fastest read commandJagannadha Sutradharudu Teki2014-12-13-56/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Few of the spi controllers are only supports array slow read which is quite different behaviour compared to others. So this fix on sf will correctly handle the slow read supported controllers. Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * | | bios_emulator: Correct ordering of includesSimon Glass2014-12-13-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We should include common.h before other includes. This actually causes a build error on chromebook_link. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | gpio: intel_ich6: Set correct gpio output value in ich6_gpio_direction_output()Axel Lin2014-12-13-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current code does not set gpio output value in ich6_gpio_direction_output(), fix it. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | x86: ich-spi: Fix a bug of reading from a non-64 bytes aligned addressBin Meng2014-12-13-15/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ich spi controller driver spi_xfer() tries to align reading address to 64 bytes when doing spi data in, which causes a bug of either infinite loop or a huge size memcpy(). Actually the ich spi controller does not have such requirement of 64 bytes alignment when reading data from spi slave devices. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-mmcTom Rini2014-12-12-35/+74
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| * | | mmc: dw_mmc: Use active DDR mode flagAndrew Gabbasov2014-12-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The card_caps bit should denote the card capability to use DDR mode, but we need the flag indicating that the DDR mode is active. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
| * | | mmc: Fix block length for DDR modeAndrew Gabbasov2014-12-12-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Block length for write and read commands is fixed to 512 bytes when the card is in Dual Data Rate mode. If block length read from CSD is different, make sure the driver will use correct length in all further calculations and settings. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
| * | | mmc: Fix Dual Data Rate capability recognitionAndrew Gabbasov2014-12-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the driver doesn't work in 1.2V or 1.8V signaling level modes, Dual Data Rate mode can be supported by the driver only if it is supported by the card in regular 3.3V mode. So, check for a particular single bit in card type field. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
| * | | mmc: Fix handling of bus widths and DDR card capabilitiesAndrew Gabbasov2014-12-12-21/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the MMC_MODE_DDR_52MHz flag is set in card capabilities bitmask, it is never cleared, even if switching to DDR mode fails, and if the controller driver uses this flag to check the DDR mode, it can take incorrect actions. Also, DDR related checks in mmc_startup() incorrectly handle the case when the host controller does not support some bus widths (e.g. can't support 8 bits), since the host_caps is checked for DDR bit, but not bus width bits. This fix clearly separates using of card_caps bitmask, having there the flags for the capabilities, that the card can support, and actual operation mode, described outside of card_caps (i.e. bus_width and ddr_mode fields in mmc structure). Separate host controller drivers may need to be updated to use the actual flags. Respectively, the capabilities checks in mmc_startup are made more correct and clear. Also, some clean up is made with errors handling and code syntax layout. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
| * | | mmc: exynos_dw-mmc: change debug messageJaehoon Chung2014-12-12-10/+12
| | | | | | | | | | | | | | | | | | | | | | | | To debug more exactly, add the index for device. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | | MMC: add MMC_VERSION_5_0Markus Niebel2014-12-12-0/+3
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | | MMC: fix user capacity for partitioned eMMC cardMarkus Niebel2014-12-12-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | if the card claims to be high capacity and the card is partitioned the capacity shall still be read from ext_csd SEC_COUNT even if the resulting capacity is smaller than 2 GiB Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | | mmc: Cosmetic fix for nicer, aligned device list printoutLubomir Popov2014-12-12-2/+5
| | |/ | |/| | | | | | | | | | | | | | | | | | | If print_mmc_devices() was called with a '\n' separator (as done for example by the "mmc list" command), it offset the 2-nd and all subsequent lines by one space. Fixing this. Signed-off-by: Lubomir Popov <l-popov@ti.com>
* | | Merge git://git.denx.de/u-boot-dmTom Rini2014-12-11-294/+946
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| * | dm: i2c: tegra: Convert to driver modelSimon Glass2014-12-11-267/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This converts all Tegra boards over to use driver model for I2C. The driver is adjusted to use driver model and the following obsolete CONFIGs are removed: - CONFIG_SYS_I2C_INIT_BOARD - CONFIG_I2C_MULTI_BUS - CONFIG_SYS_MAX_I2C_BUS - CONFIG_SYS_I2C_SPEED - CONFIG_SYS_I2C This has been tested on: - trimslice (no I2C) - beaver - Jetson-TK1 It has not been tested on Tegra 114 as I don't have that board. Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: device: Add newline to debug() messagesSimon Glass2014-12-11-3/+3
| | | | | | | | | | | | | | | | | | Some of these are missing a newline. Add it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: Add a simple EEPROM driverSimon Glass2014-12-11-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There seem to be a few EEPROM drivers around - perhaps we should have a single standard one? This simple driver is used for sandbox testing, but could be pressed into more active service. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | dm: i2c: Add an I2C EEPROM simulatorSimon Glass2014-12-11-0/+171
| | | | | | | | | | | | | | | | | | | | | | | | | | | To enable testing of I2C, add a simple I2C EEPROM simulator for sandbox. It supports reading and writing from a small data store. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | dm: i2c: Add a sandbox I2C driverSimon Glass2014-12-11-1/+112
| | | | | | | | | | | | | | | | | | | | | | | | | | | This driver includes some test features such as only supporting certain bus speeds. It passes its I2C traffic through to an emulator. Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | dm: i2c: Add I2C emulation driver for sandboxSimon Glass2014-12-11-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | In order to test I2C we need some sort of emulation interface. Add hooks to allow a driver to emulate an I2C device for sandbox. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | dm: i2c: Add a uclass for I2CSimon Glass2014-12-11-0/+467
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The uclass implements the same operations as the current I2C framework but makes some changes to make it fit driver model better: - Remove the chip address from API calls - Remove the address length from API calls - Remove concept of 'current' I2C bus - Drop all existing init functions Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-05 21:01:08 +0000