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* cfi_flash: fix bug introduced while recent change to flash_get_size()Anatolij Gustschin2010-11-28-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit ec50a8e389863ac35bfd9d9a2e8b30187318e59e "cfi_flash: handle 'chip size exceeds address window' situation" added 3rd argument to flash_get_size() but didn't fix all the function calls from the board specific code. Many boards have their own flash_get_size() definitions in the board code and use them there, but some boards (e.g. tqm834x, tqm85xx, pdm360ng) use flash_get_size() from the cfi_flash.c driver. The bug shows up if the value of the "max_size" argument (which is not defined when calling the function with two arguments) happens to be less than "info->size". In this case on the affected boards we end up with a bank of reduced size and in the worst case might even be not able to update U-Boot or to boot the kernel from flash: => fli Bank # 1: CFI conformant FLASH (32 x 16) Size: 0 kB in 1 Sectors AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x227E Erase timeout: 4096 ms, write timeout: 1 ms Buffer write timeout: 3 ms, buffer size: 64 bytes Sector Start Addresses: F0000000 RO Bank # 2: CFI conformant FLASH (32 x 16) Size: 128 MB in 512 Sectors AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x227E Erase timeout: 4096 ms, write timeout: 1 ms Buffer write timeout: 3 ms, buffer size: 64 bytes Sector Start Addresses: F8000000 F8040000 F8080000 F80C0000 F8100000 F8140000 F8180000 F81C0000 F8200000 F8240000 ... E.g., updating U-Boot is not possible now: => protect off ${u-boot_addr} +${u-boot_size} Error: end address (0xf007ffff) not in flash! Bad address format => era ${u-boot_addr} +${u-boot_size} Error: end address (0xf007ffff) not in flash! Bad address format This patch removes the 3rd argument of flash_get_size() again and sets "max_size" in the function itself instead of passing it as a function argument. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* 74xx_7xx: Cleanup for partial linking and --gc-sectionsWolfgang Denk2010-11-27-1/+2
| | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Stefan Roese <sr@denx.de>
* 824x: Cleanup for partial linking and --gc-sectionsWolfgang Denk2010-11-27-3/+7
| | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Stefan Roese <sr@denx.de>
* ppc4xx/NAND: Reduce size of NAND SPL imageStefan Roese2010-11-27-2/+2
| | | | | | | | | | This is needed for the canyonlands_nand build target. Without it the resulting image won't fit into 4k. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Scott Wood <scottwood@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Acked-by: Stefan Roese <sr@denx.de>
* e1000: fix compile warningWolfgang Denk2010-11-26-1/+2
| | | | | | | | | Get rid of compiler warning: e1000.c: In function 'e1000_transmit': e1000.c:5028: warning: passing argument 1 of 'virt_to_phys' discards qualifiers from pointer target type Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-usbWolfgang Denk2010-11-26-2/+5
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| * usb: Remove usb_dev_init() from ehci-ppc4xx.cStefan Roese2010-11-26-1/+0
| | | | | | | | | | | | | | | | | | Calling usb_dev_init() from within the EHCI host driver is wrong. The EHCI host driver should have no dependency/interconnection to the USB device driver. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Remy Bohmer <linux@bohmer.net>
| * usb: Clear CMD_RUN while issuing CMD_RESET in ehci_reset()Stefan Roese2010-11-26-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a problem noticed on lwmon5 (PPC440EPx) using the common EHCI driver, when "usb reset" is issued multiple times. Upon the 2nd (and further) "usb reset" command, the command fails with the following messages: => usb reset (Re)start USB... USB: Register 1111 NbrPorts 1 USB EHCI 1.00 scanning bus for devices... 5 USB Device(s) found scanning bus for storage devices... 2 Storage Device(s) found => usb reset (Re)start USB... USB: EHCI fail to reset Error, couldn't init Lowlevel part This patch fixes this problem. Now "usb reset" can be called multiple times. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Remy Bohmer <linux@bohmer.net>
| * usb: Add WATCHDOG_RESET call to polling loopStefan Roese2010-11-26-0/+2
| | | | | | | | | | | | | | | | This watchdog reset call is needed here, otherwise the lwmon5 board (PPC440EPx based) will reset upon the "usb reset" command. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Remy Bohmer <linux@bohmer.net>
| * usb: fix for USB_ST_STALLED status reporting in ehci_submit_async()Anatolij Gustschin2010-11-26-0/+2
| | | | | | | | | | | | | | | | | | | | | | Checking the status field of the qTD token in the current code do not take into acount cases where endpoint stall (halted) bit is set together with XactErr status bit. As a result clearing stall on an endpoint won't be done if this status bit was also set. Check for halted bit and report USB_ST_STALLED status if the host controller also indicates endpoit stall condition. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2010-11-26-25/+82
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| * mmc: omap: timeout counter fixNishanth Menon2010-11-19-25/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Having a loop with a counter is no timing guarentee for timing accuracy or compiler optimizations. For e.g. the same loop counter which runs when the MPU is running at 600MHz will timeout in around half the time when running at 1GHz. or the example where GCC 4.5 compiles with different optimization compared to GCC 4.4. use timer to keep track of time elapse and we use an emperical number - 1sec for a worst case timeout. This should never happen, and is adequate imaginary condition for us to fail with timeout. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2010-11-19-70/+94
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| * | GRETH: removed space in network driver device name.Daniel Hellstrom2010-11-18-2/+2
| | | | | | | | | | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
| * | GRETH: fixed 2 decriptor table typosDaniel Hellstrom2010-11-18-2/+2
| | | | | | | | | | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
| * | GRETH: Added extra RESET, this is needed if GRETH was stopped during an ↵Daniel Hellstrom2010-11-18-0/+10
| | | | | | | | | | | | | | | | | | ethernet frame reception. Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
| * | GRETH: Added autodetection of PHY address, or let BSP hardcode it.Daniel Hellstrom2010-11-18-23/+55
| | | | | | | | | | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
| * | GRETH: made debug printouts use common debug() macro.Daniel Hellstrom2010-11-18-41/+25
| | | | | | | | | | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
| * | GRETH: removed unneccesary register write and one clean up.Daniel Hellstrom2010-11-18-3/+1
| |/ | | | | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
* | Exclude drivers/qe/fdt.c without CONFIG_QESebastien Carlier2010-11-18-3/+1
|/ | | | | | | | | | | Previously with archive libraries fdt.o was compiled and included in qe.a and then discarded by the linker. With partial linking this results in unresolved symbols, which this commit fixes. This commit also cleans up a now-useless conditional in fdt.c. Signed-off-by: Sebastien Carlier <sebastien.carlier@gmail.com> Tested-by: Wolfgang Denk <wd@denx.de>
* net: e1000: typo using wrong argument to sizeofMatthew McClintock2010-11-17-1/+1
| | | | | | Typo from 4b29bdb0ed08412d225a8be94f61fc6c37a59dd5 Signed-off-by: Matthew McClintock <msm@freescale.com>
* Switch from archive libraries to partial linkingSebastien Carlier2010-11-17-62/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, weak symbols were not overridden by non-weak symbols found in archive libraries when linking with recent versions of binutils. As stated in the System V ABI, "the link editor does not extract archive members to resolve undefined weak symbols". This commit changes all Makefiles to use partial linking (ld -r) instead of creating library archives, which forces all symbols to participate in linking, allowing non-weak symbols to override weak symbols as intended. This approach is also used by Linux, from which the gmake function cmd_link_o_target (defined in config.mk and used in all Makefiles) is inspired. The name of each former library archive is preserved except for extensions which change from ".a" to ".o". This commit updates references accordingly where needed, in particular in some linker scripts. This commit reveals board configurations that exclude some features but include source files that depend these disabled features in the build, resulting in undefined symbols. Known such cases include: - disabling CMD_NET but not CMD_NFS; - enabling CONFIG_OF_LIBFDT but not CONFIG_QE. Signed-off-by: Sebastien Carlier <sebastien.carlier@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2010-11-17-95/+53
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| * mmc: Add multi-block read support to the generic mmc driverAlagu Sankar2010-11-04-71/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds multi-block read support for the generic MMC driver. Large reads are broken into chunks of 65535 blocks to ensure that the code works with controllers having a 16 bit block counter. This patch results in a significant performance improvement. Time to read a 45 MB file went from 36 seconds to 9 seconds on Overo Signed-off-by: Steve Sakoman <steve.sakoman@linaro.org> Tested-by: Steve Sakoman <steve.sakoman@linaro.org> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * mmc: Clean up generic mmc driver multi-block write functionsSteve Sakoman2010-11-04-24/+14
| | | | | | | | | | | | | | | | | | | | | | The current mmc write implementation is type ulong, but returns int values. Some of the printf's are terminated with /n/r, one has none. This patch fixes these issues and also removes some unnecessary local variables. Signed-off-by: Steve Sakoman <steve.sakoman@linaro.org> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | pci: Use intelligent indentation for CONFIG_PCI_SCAN_SHOWPeter Tyser2010-11-14-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_PCI_SCAN_SHOW is defined U-Boot prints out PCI devices as they are found during bootup, eg: PCIE1: connected as Root Complex 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 03:00.0 - 10b5:8112 - Bridge device 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 07:00.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:01.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:02.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d:00.0 - 1957:0040 - Processor PCIE2: Bus 0c - 0d This information is useful, but its difficult to determine the PCI bus topology. To things clearer, we can use indention to make it more obvious how the PCI bus is organized. For the example above, the updated output with this change is: PCIE1: connected as Root Complex 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 03:00.0 - 10b5:8112 - Bridge device 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 07:00.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:01.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:02.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d:00.0 - 1957:0040 - Processor PCIE2: Bus 0c - 0d In the examples above, an MPC8640 is connected to a PEX8518 PCIe switch (01:00 and 02:0x), which is connected to another PEX8518 PCIe switch (06:00 and 07:0x), which then connects to a MPC8572 processor (08:00). Also, the MPC8640's PEX8518 PCIe switch is connected to a PCI ethernet card (04:01) via a PEX8112 PCIe-to-PCI bridge (03:00). Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | pci: Fix ordering of devices when CONFIG_PCI_SCAN_SHOWPeter Tyser2010-11-14-8/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the printing of PCI device information to before the PCI device is configured. This prevents the case where recursive scanning results in the deepest devices being printed first. This change also makes PCI lockups during enumeration easier to diagnose since the device that is being configured is printed out prior to configuration. Previously, it was not possible to determine which device caused the PCI lockup. Original example: PCIE1: connected as Root Complex 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 03:00.0 - 10b5:8112 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:00.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:01.0 - 10b5:8518 - Bridge device 07:02.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 01:00.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b Updated example: PCIE1: connected as Root Complex 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 03:00.0 - 10b5:8112 - Bridge device 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 07:00.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:01.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:02.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | pci: Clean up PCI info when CONFIG_PCI_SCAN_SHOWPeter Tyser2010-11-14-28/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change does the following: - Removes the printing of the PCI interrupt line value. This is normally set to 0 by U-Boot on bootup and is rarely used during everyday operation. - Prints out the PCI function number of a device. Previously a device with multiple functions would be printed identically 2 times, which is generally confusing. For example, on an Intel 2 port gigabit Ethernet card the following was displayed: ... 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 ... - Prints a text description of each device's PCI class instead of the raw PCI class code. The textual description makes it much easier to determine what devices are installed on a PCI bus. - Changes the general formatting of the PCI device output. Previous output: PCIE1: connected as Root Complex 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d Updated output: PCIE1: connected as Root Complex 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 03:00.0 - 10b5:8112 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:00.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:01.0 - 10b5:8518 - Bridge device 07:02.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 01:00.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d:00.0 - 1957:0040 - Processor PCIE2: Bus 0c - 0d Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | fsl_pci_init: Quiet scanning printf()Peter Tyser2010-11-14-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "Scanning PCI bus X" message doesn't provide any real useful information, so remove it. Original output: PCIE1: connected as Root Complex Scanning PCI bus 01 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex Scanning PCI bus 0d 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d Updated output: PCIE1: connected as Root Complex 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d Signed-off-by: Peter Tyser <ptyser@xes-inc.com> CC: galak@kernel.crashing.org
* | fsl: Clean up printing of PCI boot infoPeter Tyser2010-11-14-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously boards used a variety of indentations, newline styles, and colon styles for the PCI information that is printed on bootup. This patch unifies the style to look like: ... NAND: 1024 MiB PCIE1: connected as Root Complex Scanning PCI bus 01 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex Scanning PCI bus 0d 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d In: serial ... Signed-off-by: Peter Tyser <ptyser@xes-inc.com> CC: wd@denx.de CC: sr@denx.de CC: galak@kernel.crashing.org
* | fsl_pci_init: Make fsl_pci_init_port() PCI/PCIe awarePeter Tyser2010-11-14-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously fsl_pci_init_port() always assumed that a port was a PCIe port and would incorrectly print messages for a PCI port such as the following on bootup: PCI1: 32 bit, 33 MHz, sync, host, arbiter Scanning PCI bus 00 PCIE1 on bus 00 - 00 This change corrects the output of fsl_pci_init_port(): PCI1: 32 bit, 33 MHz, sync, host, arbiter Scanning PCI bus 00 PCI1 on bus 00 - 00 Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | net: e1000: Add initialized eth_device & e1000_hw structureKumar Gala2010-11-14-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | nic and hw structures are allocated via malloc i.e. return memory is not zero initialized. Because of this few structure member like "function pointers" are initialized with garbage values. It may cause problem. for eg. during eth_initialize, dev->write_hwaddr is used. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Fixed typo. Signed-off-by: Wolfgang Denk <wd@denx.de>
* | net: uli526x: Add initialized eth_device structureNobuhiro Iwamatsu2010-11-14-0/+5
| | | | | | | | | | | | | | | | | | uli526x driver does not have write_hwaddr function. However, eth stuff executes write_hwaddr function because eth_device structure has not been initialized. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Ben Warren <biggerbadderben@gmail.com>
* | net: tsi108_eth: Add initialized eth_device structureNobuhiro Iwamatsu2010-11-14-1/+5
| | | | | | | | | | | | | | | | | | tsi108_eth driver does not have write_hwaddr function. However, eth stuff executes write_hwaddr function because eth_device structure has not been initialized. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Ben Warren <biggerbadderben@gmail.com>
* | net: pcnet: Add initialized eth_device structureNobuhiro Iwamatsu2010-11-14-0/+5
| | | | | | | | | | | | | | | | | | pcnet driver does not have write_hwaddr function. However, eth stuff executes write_hwaddr function because eth_device structure has not been initialized. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Ben Warren <biggerbadderben@gmail.com>
* | net: ns8382x: Add initialized eth_device structureNobuhiro Iwamatsu2010-11-14-0/+5
| | | | | | | | | | | | | | | | | | ns8382x driver does not have write_hwaddr function. However, eth stuff executes write_hwaddr function because eth_device structure has not been initialized. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Ben Warren <biggerbadderben@gmail.com>
* | net: natsemi: Add initialized eth_device structureNobuhiro Iwamatsu2010-11-14-0/+5
| | | | | | | | | | | | | | | | | | natsemi driver does not have write_hwaddr function. However, eth stuff executes write_hwaddr function because eth_device structure has not been initialized. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Ben Warren <biggerbadderben@gmail.com>
* | net: fec_mxc: Add initialized eth_device structureNobuhiro Iwamatsu2010-11-14-0/+1
| | | | | | | | | | | | | | This prevents access to the member of eth_device which is not initialized. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Ben Warren <biggerbadderben@gmail.com>
* | net: eepro100: Add initialized eth_device structureNobuhiro Iwamatsu2010-11-14-0/+5
| | | | | | | | | | | | | | | | | | eepro100 driver does not have write_hwaddr function. However, eth stuff executes write_hwaddr function because eth_device structure has not been initialized. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Ben Warren <biggerbadderben@gmail.com>
* | net: dc2114x: Add initialized eth_device structureNobuhiro Iwamatsu2010-11-14-0/+6
| | | | | | | | | | | | | | | | | | dc2114x driver does not have write_hwaddr function. However, eth stuff executes write_hwaddr function because eth_device structure has not been initialized. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Ben Warren <biggerbadderben@gmail.com>
* | net: rtl8139: Add initialized eth_device structureNobuhiro Iwamatsu2010-11-14-0/+5
| | | | | | | | | | | | | | | | | | rtl8139 driver does not have write_hwaddr function. However, eth stuff executes write_hwaddr function because eth_device structure has not been initialized. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Ben Warren <biggerbadderben@gmail.com>
* | net: rtl8169: Add initialized eth_device structureNobuhiro Iwamatsu2010-11-14-0/+5
| | | | | | | | | | | | | | | | | | rtl8169 does not have write_hwaddr function. However, eth stuff executes write_hwaddr function because eth_device structure has not been initialized. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Ben Warren <biggerbadderben@gmail.com>
* | sf: ramtron: new spi fram driverReinhard Meyer2010-11-10-0/+329
|/ | | | | | | Supports most types that support Read-Id and the FM25H20. Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Merge branch 'master' of git://git.denx.de/u-boot-samsungWolfgang Denk2010-10-29-108/+122
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| * Add generic support for samsung s3c2440C Nauman2010-10-28-102/+103
| | | | | | | | | | | | | | | | | | | | | | This patch adds generic support for the Samsung s3c2440 processor. Global s3c24x0 changes to struct members converting from upper case to lower case. Signed-off-by: Craig Nauman <cnauman@diagraph.com> Cc: kevin.morfitt@fearnside-systems.co.uk Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * ARMV7: S5P: serial: support the s5pc210Minkyu Kang2010-10-19-1/+5
| | | | | | | | | | | | | | | | | | This patch is for s5pc210 support. Due to the resigter of baudrate is changed from slot to value, add both of them to uart structure. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
| * s5p_mmc: support 8-bit bus widthJaehoon Chung2010-10-19-5/+14
| | | | | | | | | | | | | | | | | | | | This Patch do support 8-bit bus width for s5p So we add parameter for bus_width (in s5p_mmc_init(), s5p_mmc_initialize()) If want to use 8-bit bus width, only change (0, 8) instead of (0, 4). Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
* | Replace CONFIG_RELOC_FIXUP_WORKS by CONFIG_NEEDS_MANUAL_RELOCWolfgang Denk2010-10-29-2/+2
| | | | | | | | | | | | | | | | | | | | | | By now, the majority of architectures have working relocation support, so the few remaining architectures have become exceptions. To make this more obvious, we make working relocation now the default case, and flag the remaining cases with CONFIG_NEEDS_MANUAL_RELOC. Signed-off-by: Wolfgang Denk <wd@denx.de> Tested-by: Heiko Schocher <hs@denx.de> Tested-by: Reinhard Meyer <u-boot@emk-elektronik.de>
* | Coding Style cleanupWolfgang Denk2010-10-27-8/+1
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | mmc: seperate block number into small parts for multi-write cmdLei Wen2010-10-27-15/+39
| | | | | | | | | | | | | | | | | | | | Constraint the mmc framework to only send no more than 65535 blocks in one go during the multi-write command. This constraint comes due to the limitation of 16bit width block counter register at some hardware. Signed-off-by: Lei Wen <leiwen@marvell.com> Cc: Reinhard Meyer <u-boot@emk-elektronik.de>
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