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* sf: Enable byte program supportJagannadha Sutradharudu Teki2014-12-13-12/+19
| | | | | | | | | | | | | | Enabled byte program support for sst flashes in sf. Few controllers will only support BP, so this patch gives a tx transfer flag to set the BP so-that sf will operate on byte program transfer. A new TX operation mode SPI_OPM_TX_BP is introduced for such SPI controller to use byte program op for SST flash. Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* spi: sf: Support byte program for sst spi flashBin Meng2014-12-13-0/+33
| | | | | | | | | | | | | Currently if SST flash advertises SST_WP flag in the params table the word program command (ADh) with auto address increment will be used for the flash write op. However some SPI controllers do not support the word program command (like the Intel ICH 7), the byte programm command (02h) has to be used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: Fix flag collision for SST_WPSimon Glass2014-12-13-1/+1
| | | | | | | | | At present SECT_4K is the same as SST_WP so we cannot tell these apart. Fix this so that the table in sf_params.c can be used correctly. Reported-by: Jens Rottmann <Jens.Rottmann@adlinktech.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* sf: Fix look for the fastest read commandJagannadha Sutradharudu Teki2014-12-13-56/+60
| | | | | | | | | | | Few of the spi controllers are only supports array slow read which is quite different behaviour compared to others. So this fix on sf will correctly handle the slow read supported controllers. Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* bios_emulator: Correct ordering of includesSimon Glass2014-12-13-2/+2
| | | | | | | We should include common.h before other includes. This actually causes a build error on chromebook_link. Signed-off-by: Simon Glass <sjg@chromium.org>
* gpio: intel_ich6: Set correct gpio output value in ich6_gpio_direction_output()Axel Lin2014-12-13-0/+2
| | | | | | | | Current code does not set gpio output value in ich6_gpio_direction_output(), fix it. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: ich-spi: Fix a bug of reading from a non-64 bytes aligned addressBin Meng2014-12-13-15/+2
| | | | | | | | | | | | | The ich spi controller driver spi_xfer() tries to align reading address to 64 bytes when doing spi data in, which causes a bug of either infinite loop or a huge size memcpy(). Actually the ich spi controller does not have such requirement of 64 bytes alignment when reading data from spi slave devices. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-dmTom Rini2014-12-11-294/+946
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| * dm: i2c: tegra: Convert to driver modelSimon Glass2014-12-11-267/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This converts all Tegra boards over to use driver model for I2C. The driver is adjusted to use driver model and the following obsolete CONFIGs are removed: - CONFIG_SYS_I2C_INIT_BOARD - CONFIG_I2C_MULTI_BUS - CONFIG_SYS_MAX_I2C_BUS - CONFIG_SYS_I2C_SPEED - CONFIG_SYS_I2C This has been tested on: - trimslice (no I2C) - beaver - Jetson-TK1 It has not been tested on Tegra 114 as I don't have that board. Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: device: Add newline to debug() messagesSimon Glass2014-12-11-3/+3
| | | | | | | | | | | | Some of these are missing a newline. Add it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: Add a simple EEPROM driverSimon Glass2014-12-11-0/+52
| | | | | | | | | | | | | | | | | | | | There seem to be a few EEPROM drivers around - perhaps we should have a single standard one? This simple driver is used for sandbox testing, but could be pressed into more active service. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * dm: i2c: Add an I2C EEPROM simulatorSimon Glass2014-12-11-0/+171
| | | | | | | | | | | | | | | | | | To enable testing of I2C, add a simple I2C EEPROM simulator for sandbox. It supports reading and writing from a small data store. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * dm: i2c: Add a sandbox I2C driverSimon Glass2014-12-11-1/+112
| | | | | | | | | | | | | | | | | | This driver includes some test features such as only supporting certain bus speeds. It passes its I2C traffic through to an emulator. Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * dm: i2c: Add I2C emulation driver for sandboxSimon Glass2014-12-11-0/+15
| | | | | | | | | | | | | | | | | | In order to test I2C we need some sort of emulation interface. Add hooks to allow a driver to emulate an I2C device for sandbox. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * dm: i2c: Add a uclass for I2CSimon Glass2014-12-11-0/+467
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The uclass implements the same operations as the current I2C framework but makes some changes to make it fit driver model better: - Remove the chip address from API calls - Remove the address length from API calls - Remove concept of 'current' I2C bus - Drop all existing init functions Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: serial_pl01x: Add missing private data sizeSimon Glass2014-12-11-0/+1
| | | | | | | | | | | | | | | | | | | | | | The private data size is missing from the driver, so we store it at 0, which causes problems when something overwrites memory at 0. Fix this. Change-Id: I6f551ee905b0064ae8343e41e46450c37c8c8c1a Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org>
| * lib: string: move strlcpy() to a common placeMasahiro Yamada2014-12-11-24/+0
| | | | | | | | | | | | | | | | | | Move strlcpy() definition from drivers/usb/gadget/ether.c to lib/string.c because it is a very useful function. Let's add the prototype to include/linux/string.h too. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2014-12-11-5/+52
|\ \ | | | | | | | | | | | | | | | | | | Conflicts: board/freescale/mx6sxsabresd/mx6sxsabresd.c Signed-off-by: Tom Rini <trini@ti.com>
| * | usb: ehci: do not set the LSB of Current qTD pointerMasahiro Yamada2014-11-19-1/+0
| | | | | | | | | | | | | | | | | | | | | According to EHCI specification, the LSB of DWORD 3 of Queue Head (Current qTD Pointer) is not T-bit, but always zero. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | dfu: thor: fix: Modify dfu_get_alt() function to support absolute pathsLukasz Majewski2014-11-14-2/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recently the ext4 file system imposed passing absolute path with its file name parameter. As a result dfu_alt_info env variable has been modified to provide absolute path when ext4 file system is accessed (e.g. /uImage ext4 0 2;). Unfortunately, lthor flashing program provides plain file name (like uImage) and hence those two file names do not match anymore. Presented commit also allows lthor to write files to sub directories (like /boot/bin/uImage). Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Reviewed-by: Marek Vasut <marex@denx.de>
| * | usb:ehci-mx6 add phy mode query functionPeng Fan2014-11-14-2/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | usb_phy_enable should return status bit, but not phy mode bit, thus add a new function usb_phy_mode to query the PHY for it's mode and make usb_phy_enable just return 0 but not 'phy_ctrl & USBPHY_CTRL_OTG_ID'. Include a new board weak function board_usb_phy_mode. If board code does not reimplement this function, it just call usb_phy_mode and return usb_phy_mode's return value. The reason to include such a weak function is: " SOC OTG core <--connect--> board HOST port, but no pin id for the board host port, so board can not use usb_phy_mode to return the phy mode, but define it's own rule." Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye Li <B37916@freescale.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2014-12-11-54/+352
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| * | driver/mtd: Fix IFC compilation warningsJaiprakash Singh2014-12-11-1/+1
| | | | | | | | | | | | | | | | | | | | | 'eccstat' array elements might be used uninitialized Signed-off-by: Jaiprakash Singh <b44839@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | fsl/sleep: updated the deep sleep framework for QorIQ platformsTang Yuantian2014-12-11-53/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the introducing of generic board and ARM-based cores, current deep sleep framework doesn't work anymore. This patch will convert the current framework to adapt this change. Basically it does: 1. Converts all the Freescale's DDR driver to support deep sleep. 2. Added basic framework support for ARM-based and PPC-based cores separately. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers: usb: fsl: Check USB Erratum A007792 applicabilityNikhil Badola2014-12-11-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | Check USB Erratum A007792 applicability. If applicable, add corresponding property in the device tree via device tree fixup Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers: usb: fsl: Add USB device-tree errata frameworkNikhil Badola2014-12-11-0/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new framework for fsl usb erratum handling to standardize erratum checking only inside Uboot. Information to kernel is passed via a boolean property corresponding to erratum, hence eliminating need for code duplication inside kernel Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers: usb: Make usb device-tree fixup code architecture independentNikhil Badola2014-12-11-0/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | move usb device tree fixup code from "arch/powerpc/" to "drivers/usb/" so that it works independent of architecture it is running on Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls102xa: Add NAND boot support for LS1021AQDS boardAlison Wang2014-12-11-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds NAND boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from NAND flash to DDR, finally SPL transfer control to u-boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls102xa: Update PCIe dts node statusMinghuan Lian2014-12-11-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | The patch changes PCIe dts node status to 'disabled' if the corresponding controller is disabled according to serdes protocol. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-12-10-14/+18
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| * | sata: fix reset_sata for dwc_ahsataSoeren Moch2014-12-01-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - fix crash when sata device is not initialized - remove disable_sata_clock() since it is not clear which clock for which device should be disabled here - call disable_sata_clock() for mx6 in preboot_os instead Signed-off-by: Soeren Moch <smoch@web.de> Acked-by: Nikita Kiryanov <nikita@compulab.co.il> Tested-by: Nikita Kiryanov <nikita@compulab.co.il>
| * | mxc_ocotp: Do not disable the OCOTP clock after every accessFabio Estevam2014-12-01-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Leave the OCOTP turned on, so that we subsequent access do not fail. After enabling the thermal driver on a mx6sxsabresd board: U-Boot 2015.01-rc1-18267-g99d4189-dirty (Nov 24 2014 - 12:59:01) CPU: Freescale i.MX6SX rev1.0 at 792 MHz CPU: Temperature 48 C Reset cause: POR Board: MX6SX SABRE SDB I2C: ready DRAM: 1 GiB PMIC: PFUZE100 ID=0x10 MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 00:01.0 - 16c3:abcd - Bridge device 01:00.0 - 8086:08b1 - Network controller In: serial Out: serial Err: serial Net: (hang) As the thermal driver accesses the ocotp registers, its clock will be disabled afterwards. Then when the MAC address is read (also from ocotp registers) it will cause a hang. Do not disable the ocotp clock to prevent this problem. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
| * | thermal: imx_thermal: Do not display calibration dataFabio Estevam2014-12-01-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Printing the calibration data on every boot does not provide really useful information: U-Boot 2015.01-rc1-18266-ge7eb277 (Nov 24 2014 - 11:29:51) CPU: Freescale i.MX6Q rev1.2 at 792 MHz CPU: Thermal calibration data: 0x5d85067d CPU: Temperature 33 C Reset cause: POR Board: MX6-SabreSD Do not display the calibration data in order to have a cleaner boot log. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | mxs_ocotp: clear the error flag before initiating write operationHector Palacios2014-12-01-0/+2
| | | | | | | | | | | | | | | | | | | | | A previous operation may have set the error flag, which must be cleared before a new write operation can be issued. Signed-off-by: Hector Palacios <hector.palacios@digi.com>
| * | mxs_ocotp: check for errors from the OTP controller after writingHector Palacios2014-12-01-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | The write operation may fail when trying to write to a locked area. In this case the ERROR bit is set in the CTRL register. Check for that condition and return an error. Signed-off-by: Hector Palacios <hector.palacios@digi.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | mxs_ocotp: prevent error path from returning successHector Palacios2014-12-01-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code may goto 'fail' upon error with 'ret' variable set to an error code, but this variable was being overwritten by a final preparation function to restore the HCLK, so success was (in general) returned even after an error was hit previously. With this change, the function may now return success even if the final preparation function fails, but it's probably enough to print a message because (if successful) the real programming of the fuses has already completed. Signed-off-by: Hector Palacios <hector.palacios@digi.com>
* | | Merge git://git.denx.de/u-boot-mpc85xxTom Rini2014-12-08-15/+555
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| * | | net/phy: enable serdes auto-negotiation for vsc8514 phyShengzhou Liu2014-12-05-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | VSC8514 QSGMII PHY requires enabling auto-negotiation, otherwise it wouldn't work. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | net/fman: update 10GEC to fit new SoCShengzhou Liu2014-12-05-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fm_standard_init() initializes each 10G port by FM_TGEC_INFO_INITIALIZER. but it needs different implementation of FM_TGEC_INFO_INITIALIZER on different SoCs. on SoCs earlier(e.g. T4240, T2080), the notation between 10GEC and MAC as below: 10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2 on SoCs later(e.g. T1024, etc), the notation between 10GEC and MAC as below: 10GEC1->MAC1, 10GEC2->MAC2 so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to fit the new SoCs on which 10GEC enumeration is consistent with MAC enumeration. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | powerpc/mpc85xx: Add T1024/T1023 SoC supportShengzhou Liu2014-12-05-0/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Freescale T1024/T1023 SoC. The T1024 SoC includes the following function and features: - Two 64-bit Power architecture e5500 cores, up to 1.4GHz - private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC) - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration - Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI) - High-speed peripheral interfaces - Three PCI Express 2.0 controllers - Additional peripheral interfaces - One SATA 2.0 controller - Two USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/eSDHC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Two 8-channel DMA engines - Multicore programmable interrupt controller (PIC) - LCD interface (DIU) with 12 bit dual data rate - QUICC Engine block supporting TDM, HDLC, and UART - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T1024 and T1023: Feature T1024 T1023 QUICC Engine: yes no DIU: yes no Deep Sleep: yes no I2C controller: 4 3 DDR: 64-bit 32-bit IFC: 32-bit 28-bit Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | driver/ddr/fsl: Add workaround for faulty SPDYork Sun2014-12-05-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Some UDIMMs have faulty SPD with wrong mapping for DQ[36-39]. Using raw card spec in case this error is detected. Signed-off-by: York Sun <yorksun@freescale.com>
| * | | B4860QDS: Enable enet port as per fsl_b4860_serdes2 string in hwconfigSuresh Gupta2014-12-05-2/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In B4860QDS board SerDes2 lanes EFGH either go to SFP or AMC riser card slot2 so either DTSEC3/DTSEC4 or TGEC1/TGEC2 should be accessible. This Patch enables DTSEC3/DTSEC4 or TGEC1/TGEC2 on bases of user specified string fsl_b4860_serdes2:sfp_amc=amc or fsl_b4860_serdes2:sfp_amc=sfp respectively in hwconfig. Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | powerpc/b4860qds: add xfi supportShaohui Xie2014-12-05-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need following changes to make xfi work on B4: 1. set cross-point switch VSC3308 to use sfp config when running xfi; 2. add 10G interface check for xfi; 3. set phy address for xfi so the 10G ports can be registered by mdio; Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | net/phy: Add support for CS4315/CS4340 PHYShengzhou Liu2014-12-05-0/+337
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Cortina CS4315/CS4340 10G PHY. - This driver loads CS43xx firmware from NOR/NAND/SPI/SD device to initialize Cortina PHY. - Cortina PHY has non-standard offset of PHY ID registers, thus we define own get_phy_id() to override default get_phy_id(). - To define macro CONFIG_PHY_CORTINA will enable this driver. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | driver/ddr/fsl: Adjust timing_cfg_0 to better support two DDR slotsYork Sun2014-12-05-6/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Increase write-to-write and read-to-read turnaround time for two-slot DDR configurations. Previously only quad-rank and two dual-rank configurations have this additional turnaround time. A recent test on two single-rank DIMMs shows the shorter additional turnaround time is also needed. Signed-off-by: York Sun <yorksun@freescale.com>
| * | | Freescale t104x: Do not exclude SGMIIJoakim Tjernlund2014-12-05-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fman_port_enet_if() tests if FM1_DTSEC2 or FM1_DTSEC4 uses RGMII or MII and if not returns PHY_INTERFACE_MODE_NONE. This excludes testing for SGMII further down. Remove the unconditional "else return PHY_INTERFACE_MODE_NONE" so SGMII can be tested too. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Reviewed-by: York Sun <yorksun@freescale.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-tiTom Rini2014-12-08-35/+42
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| * | | | ns16550.c: Fix for ns16550 driver hanging on OMAP4Gregoire Gentil2014-12-04-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The same problem that is seen on some OMAP3 is also seen on some OMAP4 so include them in the test in order to prevent some hangs during SPL. [trini: Re-word commit message, make apply cleanly] Signed-off-by: Tom Rini <trini@ti.com>
| * | | | mtd: nand: omap_gpmc: Always use ready/busy pinStefan Roese2014-12-04-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The functions to detect the state of the ready / busy signal is already available but only used in the SPL case. Lets use it always, also for the main U-Boot. As all boards should have this HW connection. Testing on Siemens Draco (am335x) showed a small perfomance gain by using this ready pin to detect the NAND chip state. Here the values tested on Draco with Hynix 4GBit NAND: Without NAND ready pin: U-Boot# time nand read 80400000 0 400000 NAND read: device 0 offset 0x0, size 0x400000 4194304 bytes read: OK time: 2.947 seconds, 2947 ticks With NAND ready pin: U-Boot# time nand read 80400000 0 400000 NAND read: device 0 offset 0x0, size 0x400000 4194304 bytes read: OK time: 2.795 seconds, 2795 ticks So an increase of approx. 5%. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Roger Meier <r.meier@siemens.com> Cc: Samuel Egli <samuel.egli@siemens.com>
| * | | | omap_hsmmc: Board-specific TWL4030 MMC power initializationsPaul Kocialkowski2014-12-04-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boards using the TWL4030 regulator may not all use the LDOs the same way (e.g. MMC2 power can be controlled by another LDO than VMMC2). This delegates TWL4030 MMC power initializations to board-specific functions, that may still call twl4030_power_mmc_init for the default behavior. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@ti.com> [trini: Fix omap3_evm warning, add twl4030.h] Signed-off-by: Tom Rini <trini@ti.com>
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