summaryrefslogtreecommitdiff
path: root/drivers
Commit message (Collapse)AuthorAgeLines
* altera_tse: Fix return of eth_device's recv() callbackJoachim Foerster2011-10-26-0/+2
| | | | | | | It seems to be good practice to return the number of received bytes in the eth_device's recv() callback, here: tse_eth_rx(). Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
* altera_tse: m88e1111s: Honor device flags regarding PHY interface modeJoachim Foerster2011-10-26-2/+8
| | | | | | | | | Note: This is kind of guess work. The current code is preserved for all RGMII related modes. It is different for flags=0 (GMII) and flags=5 (SGMII). The last case, SGMII, is successfully tested on Altera's Terasic DE4. Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
* altera_tse: Add support for dedicated descriptor memoryJoachim Foerster2011-10-26-3/+16
| | | | Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
* altera_tse: Fix SGDMA reset triggeringJoachim Foerster2011-10-26-4/+4
| | | | | | The SW_RESET needs to be set instead of being masked out! Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
* altera_tse: Clear SGDMA's RUN bit in async transfer, like in sync caseJoachim Foerster2011-10-26-0/+6
| | | | Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
* mmc: dcache: allocate cache aligned buffers for ext_csdAnton staaf2011-10-25-2/+2
| | | | | | | | | | | | | | | Currently the mmc_change_freq and mmc_startup functions allocates buffers on the stack that are passed down to the MMC device driver. These buffers could be unaligned to the L1 dcache line size. This causes problems when using DMA and with caches enabled. This patch correctly cache alignes the buffers used for reading the ext_csd data from an MMC device. Signed-off-by: Anton Staaf <robotboy@chromium.org> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
* mmc: dcache: allocate cache aligned buffer for scr and switch_statusAnton staaf2011-10-25-5/+5
| | | | | | | | | | | | | | | | | Currently the sd_change_freq function allocates two buffers on the stack that it passes down to the MMC device driver. These buffers could be unaligned to the L1 dcache line size. This causes problems when using DMA and with caches enabled. This patch correctly cache alignes the buffers used for reading the scr register and switch status values from an MMC device. Change-Id: Ifa8414f572ef907681bd2d5ff3950285a215357d Signed-off-by: Anton Staaf <robotboy@chromium.org> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Mike Frysinger <vapier@gentoo.org>
* net: sc589: drop unused !NET_MULTI driverMike Frysinger2011-10-23-953/+0
| | | | | | | No boards appear to use this driver, and it doesn't support NET_MULTI, so punt the old driver. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* net: s3c4510b_eth: drop unused !NET_MULTI driverMike Frysinger2011-10-23-544/+0
| | | | | | | No boards appear to use this driver, and it doesn't support NET_MULTI, so punt the old driver. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* net: ns9750: drop !NET_MULTI driverMike Frysinger2011-10-23-790/+0
| | | | | | | | Only one board uses this driver (ns9750dev), but the board doesn't seem to have an entry to actually build it in the Makefile/boards.cfg, so just delete net support from its board config. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* net: enc28j60_lpc2292: drop unused !NET_MULTI driverMike Frysinger2011-10-23-984/+0
| | | | | | | Everyone seems to have converted to the new enc28j60 driver, so drop this older one which isn't used and doesn't support NET_MULTI. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* net: emaclite: Move RX/TX ping pong initialization toMichal Simek2011-10-23-7/+4
| | | | | | Init RX/TX ping pong directly from board not in the driver. Signed-off-by: Michal Simek <monstr@monstr.eu>
* net: emaclite: Use unsigned long for baseaddrMichal Simek2011-10-23-2/+2
| | | | | | Baseaddr should be unsigned long. Signed-off-by: Michal Simek <monstr@monstr.eu>
* spi/eon: add support for new EON spi flash EN25Q32BShaohui Xie2011-10-23-0/+8
| | | | Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
* NS16550: trivial code clean for checkpatchSimon Glass2011-10-23-17/+20
| | | | | | | This removes most checkpatch warnings from the ns16550 driver and its header. Signed-off-by: Simon Glass <sjg@chromium.org>
* serial: uartlite: Fix compilation warningsMichal Simek2011-10-23-1/+1
| | | | | | | | | | | | | | | | Do not setup userial_ports array as const because in uartlite_serial_putc is out_be32 which can't write to tx_fifo if is const. Warning log: serial_xuartlite.c: In function 'uartlite_serial_putc': serial_xuartlite.c:60: warning: initialization discards qualifiers from pointer target type serial_xuartlite.c: In function 'uartlite_serial_getc': serial_xuartlite.c:78: warning: initialization discards qualifiers from pointer target type serial_xuartlite.c: In function 'uartlite_serial_tstc': serial_xuartlite.c:87: warning: initialization discards qualifiers from pointer target type Signed-off-by: Michal Simek <monstr@monstr.eu>
* consolidate mdelay by providing a common function for all usersAnatolij Gustschin2011-10-22-19/+0
| | | | | | | | | There are several mdelay() definitions in the driver and board code. Remove them all and provide a common mdelay() in lib/time.c. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Mike Frysinger <vapier@gentoo.org>
* drivers: add the support for Silicon Image SATA controllerTang Yuantian2011-10-22-0/+952
| | | | | | | | | | | | | | | | | Add the Silicon Image series PCI Express to Serial ATA controller support, including Sil3132, Sil3131 and Sil3124. The SATA controller can be used to load kernel. The features list: - Supports 1-lane 2.5 Gbit/s PCI Express - Supports one/two/four independent Serial ATA channels - Supports Serial ATA Generation 2 transfer rate of 3.0 Gbit/s - Supports LBA28 and LBA48 Signed-off-by: Tang Yuantian <b29983@freescale.com> Signed-off-by: Aaron Williams <Aaron.Williams@cavium.com> Tested-by: Lan Chunhe <b25806@freescale.com>
* gpio: Add PCA9698 40-bit I2C I/O portDirk Eibach2011-10-22-0/+124
| | | | Signed-off-by: Dirk Eibach <eibach@gdsys.de>
* serial: pl01x: drain PL01x FIFO before baudrate changeLinus Walleij2011-10-22-0/+10
| | | | | | | | | Not draining the FIFO and waiting for the UART to be non-busy before changing baudrate results in crap characters on the console, so let's wait for the FIFO to drain and the last character to be clocked out before we do that. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* net: dc2114x: check for apropriate commandLinus Walleij2011-10-22-3/+5
| | | | | | | | | The code had two paths depending on whether the card was to be accessed from plain memory or the IO region. However the error path checks whether IO region was obtained - twice. Fix up the error path according to the probable intention. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ftgmac100: reset fix when supports wake on lanMacpaul Lin2011-10-22-2/+2
| | | | | | | | | | | | | | | | | | | | | This patch move the reset function from initialization to driver register procedure. Some embedded system supports wake on lan nowadays. On this kind of system, the ftgmac100 will be still supplied power after the system has been shut-down by Linux. Hence the register used by linux won't be clear when the system has been powered-off. The origin ftgmac100 driver in u-boot will only register driver and functions to network stack and won't reset the ftgmac100 hardware if the network won't be used during boot-up. This will lead ftgmac100 continue receiving packets and then might corrupt linux kernel when booting up. So we reorder the hardware reset function earlier to force the hardware to be reset whether it will be used or not. Signed-off-by: Macpaul Lin <macpaul@andestech.com>
* powerpc/85xx: wait for alignment before resetting SERDES RX lanes (SERDES9)Timur Tabi2011-10-20-1/+1
| | | | | | | | The work-around for P4080 erratum SERDES9 says that the SERDES receiver lanes should be reset after the XAUI starts tranmitting alignment signals. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fm: Don't allow disabling of FM1-DTSEC1Kumar Gala2011-10-18-0/+20
| | | | | | | | The MDIO controller to talk to external PHYs is on FM1-DTSEC1 so don't allow disabling. If we disable it we end up powering the block down in the SoC and thus can't communicate to any external PHYs. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fm-eth: Don't mark the MAC we use for MDIO as disabled in device treeKumar Gala2011-10-18-2/+8
| | | | | | | | FM1-DTSEC1's MAC was being marked as disabled if the port was not configured based on the SoC configuration. However we utilize the MAC interface for MDIO and thus should NOT mark it disabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Move timestamp and version files into 'generated' subdirSimon Glass2011-10-17-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a rather subtle build problem where the build time stamp is not updated for out-of-tree builds if there exists an in-tree build which has a valid timestamp file. So if you do an in-tree build, then an out-of-tree build your timestamp will not change. The correct timestamp_autogenerated.h lives in the object tree, but it is not always found there. The source still lives in the source tree and when compiling version.h, it includes timestamp_autogenerated.h. Since the current directory is always searched first, this will come from the source tree rather than the object tree if it exists there. This affects dependency generation also, which means that common/cmd_version.o will not even be rebuilt if you have ever done an in-tree build. A similar problem exists with the version file. This change moves both files into the 'generated' subdir, which is already used for asm-offsets.h. Then timestamp.h and version.h are updated to include the files from there. There are other places where these generated files are included, but I cannot see why these don't just use the timestamp.h and version.h headers. So this change also tidies that up. I have tested this with in- and out-of-tree builds, but not SPL. I have looked at various other options for fixing this, including sed on the dep files, -I- and -include flags to gcc, but I don't think they can be made to work. Comments welcome. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Mike Frysinger <vapier@gentoo.org>
* sandbox: Add serial uartSimon Glass2011-10-17-0/+64
| | | | | | | | This uart simply writes to stdout and reads from stdin. We might imagine instead buffering the data so that a test interface can check output and inject input. Signed-off-by: Simon Glass <sjg@chromium.org>
* Replace space and tab checks with isblankJason Hobbs2011-10-17-3/+4
| | | | | | | These are various places I found that checked for conditions equivalent to isblank. Signed-off-by: Jason Hobbs <jason.hobbs@calxeda.com>
* DM9000:Add a byte swap macro for dm9000 io operation.Jason Jin2011-10-17-1/+9
| | | | | | | | | | | | | commit a45dde2293c816138e53c26eca6fd0322583f9a6 changed the dm9000 direct register access to standard IO. This should work on the ColdFire platform as there are corresponding macros for the LE devices. But the hardware settings on some ColdFire boards had swapped the byte order which make the original macros such as out_le16 cannot work. To avoid changing the common io access code on ColdFire platform, the DM9000_BYTE_SWAPPED define was added to make the dm9000 use __raw* IO access on some ColdFire boards. Signed-off-by: Jason Jin <Jason.jin@freescale.com>
* kw_gpio: fix error in kw_gpio_direction_inputHolger Brunck2011-10-17-1/+1
| | | | | | | | | The function kw_gpio_is_valid returns zero on success, so adapt the error check accordingly. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> cc: Dieter Kiermaier <dk-arm-linux@gmx.de>
* Blackfin: bfin_spi: fix build error when DEBUG is definedMike Frysinger2011-10-17-1/+1
| | | | | | The new debug() changes pointed out debug code that rotted a little. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* video: Moving mx3fb.c to CONFIG_VIDEOHelmut Raiger2011-10-17-193/+275
| | | | | | | | | | | | | | | | | | | | | | | | | mx3fb.c was based on CONFIG_LCD and is moved by this patch to CONFIG_VIDEO, which has greater freedom in selecting videomodes even at runtime. This renders the accumulating list of display defines (CONFIG_DISPLAY_VBEST..., CONFIG_DISPLAY_C057...) obsolete as these may be setup through env variables: uboot> setenv mydisplay 'video=ctfb:x:240,y:320,depth:16,mode:0,pclk:185925, le:9,ri:17,up:7,lo:10,hs:1,vs:1,sync:100663296,vmode:0' uboot> setenv videomode ${mydisplay} This commit also fixes the board config files for qong and imx31_phycore boards as needed. The videomode settings of previously supported displays are added to CONFIG_EXTRA_ENV_SETTINGS now. CONFIG_SYS_MALLOC_LEN for imx31_phycore board is increased to make the frame buffer allocation working with the changed driver. Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* MX5: Make IPU display output and pixel format configurableMarek Vasut2011-10-17-5/+10
| | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Stefano Babic <sbabic@denx.de> Tested-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Anatolij Gustschin <agust@denx.de>
* VIDEO: MX5: export pix formatStefano Babic2011-10-17-45/+1
| | | | | | | | | | | Pixel format defines must be available for boards to set up the right display. Move them and export in a new file. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Anatolij Gustschin <agust@denx.de> CC: Marek Vasut <marek.vasut@gmail.com> Tested-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Anatolij Gustschin <agust@denx.de>
* VIDEO: MX5: Switch MX5 to CONFIG_VIDEOStefano Babic2011-10-17-74/+36
| | | | | | | | | | | | | | | | | The framebuffer driver for MX5 is based on CONFIG_LCD. In the current implementation, there is a serious bug because the required memory is allocated before relocation, but the driver knows only later which is the resolution of the display. The patch switches the driver to CONFIG_VIDEO and the memory is allocated by the driver itself. We also need to switch the vision2 board code and config file in the same commit so that this commit will be bisectable. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Anatolij Gustschin <agust@denx.de> Tested-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Anatolij Gustschin <agust@denx.de>
* video: update the Freescale DIU driver to use linux/fb.hTimur Tabi2011-10-17-49/+5
| | | | | | | | Update the Freescale DIU video driver (fsl_diu_fb.c) to use linux/fb.h. Some data structures from this header file were just copied into fsl_diu_fb.c. Signed-off-by: Timur Tabi <timur@freescale.com>
* pci: move pcidelay code to new location just before PCI bus scanAnatolij Gustschin2011-10-15-13/+17
| | | | | | | | | | | | | | | | | | | | PCI cards might need some time after reset to respond. On some boards (mpc5200 or mpc8260 based) the PCI bus reset is deasserted at pci_init_board() time, so we currently can not use available "pcidelay" option for waiting before PCI bus scan since this waiting takes place before calling pci_init_board(). By moving the pcidelay code to the new location using of the "pcidelay" option is possible on mpc5200 or mpc8260 based boards, too. Since pci_hose_scan() could be called multiple times, restrict the function to wait only during its first call and to ignore pcidelay for any further call (as pointed out by Matthias). Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Matthias Fuchs <matthias.fuchs@esd.eu> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu> Tested-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* net: axi_ethernet: Add driver to u-bootMichal Simek2011-10-15-0/+665
| | | | | | | | | | Add axi_ethernet driver for little-endian Microblaze. RX/TX BDs and rxframe buffer are shared among all axi_ethernet MACs. Only one MAC can work in one time. Signed-off-by: Michal Simek <monstr@monstr.eu> Acked-by: Mike Frysinger <vapier@gentoo.org>
* net: emaclite: Fix coding styleMichal Simek2011-10-15-30/+27
| | | | | | Coding style should follow linux coding style. Signed-off-by: Michal Simek <monstr@monstr.eu>
* net: emaclite: Use PKTSIZE directlyMichal Simek2011-10-15-6/+4
| | | | | | Do not setup additional ENET_MAX_MTU macro. Signed-off-by: Michal Simek <monstr@monstr.eu>
* net: emaclite: Setup RX/TX ping pong for every instanceMichal Simek2011-10-15-55/+68
| | | | | | | Setup RX/TX ping-pong buffer for every emaclite IP separately. The next patch move initialization directly to board code. Signed-off-by: Michal Simek <monstr@monstr.eu>
* phylib: wait for TN2020 to achieve SERDES lane alignment at startupTimur Tabi2011-10-13-0/+33
| | | | | | | | | | Before the Teranetics TN2020 PHY can be used, the SERDES lanes need to be aligned, so wait for lane alignment before completing the startup sequence. Note that this process can take up to three seconds. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/p3060: remove all references to RCW bits EC1_EXT, EC2_EXT, and EC3Timur Tabi2011-10-13-17/+0
| | | | | | | | The EC1_EXT, EC2_EXT, and EC3 bits in the RCW don't officially exist on the P3060 and should always be set to zero. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of git://git.denx.de/u-boot-mipsWolfgang Denk2011-10-12-0/+262
|\ | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-mips: MIPS: Jz4740: Add qi_lb60 board support MIPS: Jz4740: Add NAND driver MIPS: Ingenic XBurst Jz4740 processor support
| * MIPS: Jz4740: Add NAND driverXiangfu Liu2011-10-12-0/+262
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Jz4740 NAND flash controller can support: * MLC NAND as well as SLC NAND * all 8-bit/16-bit NAND flash devices * HAMMING and RS hardware ECC * automatic boot up from NAND flash devices nand_ecclayout is set up for 2GiB NAND chip mounted in Qi LB60. We'll bring up boot-from-NAND support in nand_spl/ in the future. Signed-off-by: Xiangfu Liu <xiangfu@openmobilefree.net> Acked-by: Daniel <zpxu@ingenic.cn> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-ubiWolfgang Denk2011-10-12-6/+6
|\ \ | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-ubi: UBI: init eba tables before wl when attaching a device ubifs bad superblock bug
| * | UBI: init eba tables before wl when attaching a deviceHolger Brunck2011-10-12-6/+6
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes that u-boot gets stuck when a bitflip was detected during "ubi part <ubi_device>". If a bitflip was detected UBI tries to copy the PEB to a different place. This needs that the eba table are initialized, but this was done after the wear levelling worker detects the bitflip. So changes the initialisation of these two tasks in u-boot. This is a u-boot specific patch and not needed in the linux layer, because due to commit 1b1f9a9d00447d UBI: Ensure that "background thread" operations are really executed we schedule these tasks in place and not as in linux after the inital task which schedule this new task is finished. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-nand-flashWolfgang Denk2011-10-12-13/+13
|\ \ | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-nand-flash: NAND: davinci: choose correct 1-bit h/w ECC reg
| * | NAND: davinci: choose correct 1-bit h/w ECC regLaurence Withers2011-10-10-13/+13
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In nand_davinci_readecc(), select the correct NANDF<n>ECC register based on CONFIG_SYS_NAND_CS rather than hardcoding the choice of NANDF1ECC. This allows 1-bit hardware ECC to work with chip select other than CS2. Note this now matches the usage in nand_davinci_enable_hwecc(), which already had the correct handling, and allows refactoring to a single function encapsulating the register read. Without this fix, writing NAND pages to a chip not wired to CS2 would result in in the ECC calculation always returning FFFFFF for each 512-byte segment, and reading back a correctly written page (one with ECC intact) would always fail. With this fix, the ECC is written and verified correctly. Signed-off-by: Laurence Withers <lwithers@guralp.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | fsl_sata: Fix compile error when CONFIG_LBA48 is not definedTang Yuantian2011-10-09-5/+10
| | | | | | | | | | | | | | | | If CONFIG_LBA48 is not defined, the element lba48 of struct sata_dev_desc is not avaible, and can't be used. Signed-off-by: Tang Yuantian <b29983@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
generated by cgit v1.1 at 2024-10-30 00:06:16 +0000