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* sunxi: video: Enable video on sun8i, which supports LCD but not HDMIHans de Goede2015-01-14-4/+26
| | | | | | | | | | | | | | The A23 (sun8i) only has lcd output support, so allow building the video code without HDMI support for use with the A23. Also the A23 has the same reset bits (and necessity to enable the DRC block) as the sun6i, so enable those bits for sun8i too. Note building without HDMI support is useful for the A13 (sun5i variant) too, as that one does not have HDMI either. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: video: Add lcd output supportHans de Goede2015-01-14-9/+171
| | | | | | | | Add lcd output support, see the new Kconfig entries and doc/README.video for how to enable / configure this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: video: Move sunxi_drc_initHans de Goede2015-01-14-14/+12
| | | | | | | | Move sunxi_drc_init to directly above sunxi_engines_init, to avoid unnecessary #ifdef-ery in later patches. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: video: Modify sunxi_lcdc_pll_set to work with both tcon0 and tcon1Hans de Goede2015-01-14-7/+24
| | | | | | | | | | | | | Modify sunxi_lcdc_pll_set to work with both tcon0 and tcon1, this is a preparation patch for adding lcd support. While at it also swap the divider search order, searching from low to high, as the comment above the code says we should do. In cases where there are multiple solutions this will result in picking a lower pll clock and divider, which is more stable and saves power. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: video: Prepare for lcd supportHans de Goede2015-01-14-32/+70
| | | | | | | | | | | | Refactor sunxi_mode_set into a bunch of helpers, and make it do a switch case on sunxi_display.monitor to decide what to do. Also rename sunxi_lcdc_mode_set to sunxi_lcdc_tcon1_mode_set, as it sets the timings for tcon1, and for lcd support we need a similar function operating on tcon0. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: video: Improve monitor video-mode option handlingHans de Goede2015-01-14-16/+47
| | | | | | | | | | | Add a sunxi_monitor enum and parse the monitor option string into this enum once, rather then doing strcmp-s on it in various places. This also adds checking for it being a valid value. This also adds new "none" and "lcd" values in preparation for lcd support. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: gpio: Add support for gpio pins on the AXP209 pmicHans de Goede2015-01-14-0/+102
| | | | | | | | | | | | | | | | | | | | | | Some boards use GPIO-s on the pmic, one example of this is the A13-OLinuXino board, which uses gpio0 of the axp209 for the lcd-power signal. This commit adds support for gpio pins on the AXP209 pmic, the sunxi_gpio.c changes are universal, adding gpio support for the other AXP pmics (when necessary) should be a matter of adding the necessary axp_gpio_foo functions to their resp. drivers, and add "#define AXP_GPIO" to their header file. Note this commit only adds support for the non device-model version of the gpio code, patches for adding support to the device-model version are very welcome. The string representation for these gpio-s is AXP0-#, the 0 in the AXP0 prefix is there in case we need to support gpio-s on more then 1 pmic in the future. At least A80 boards have 2 pmics, and we may end up needing to support gpio-s on both. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: video: Set input sync enableHans de Goede2015-01-14-23/+4
| | | | | | | | | | | | | | | | | | | Add a write to the "unknown" (*) register to enable auto input sync, when initially adding sunxi hdmi output support this magic write from the android kernel code was missed, causing lcdc -> hdmi encoder sync problems. With this write added, we can drop the modesetting retries and the extra delays added to work around these sync problems. With the retries dropped there also is no need to 0 all the enable flags at the beginning of the modeset, as they are initialized to 0 already by engines_init. *) "unknown" is the actual name of this register in the android kernel sources Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Anatolij Gustschin <agust@denx.de>
* sunxi: video: Give hotplug-detect (hpd) signal some time to show upHans de Goede2015-01-14-2/+6
| | | | | | | | | | | | | When using a hdmi powered hdmi to vga dongle, and cold booting a sunxi device, the hpd detect code would not see the dongle (until a warm reboot), because the dongle needs some time to boot. Testing has shown that this dongle needs 213ms to respond on a cold boot, so wait up to 300ms for a hpd signal to show up before giving up. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Anatolij Gustschin <agust@denx.de>
* sunxi: video: When using edid use CEA681 extension blocks to select hdmi outputHans de Goede2015-01-14-9/+34
| | | | | | | | | When using edid use CEA681 edid extension blocks to select between dvi and hdmi output formats, so that u-boot will automatically do the right thing. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Anatolij Gustschin <agust@denx.de>
* sunxi: video: Add sunxi_hdmi_edid_get_block helper functionHans de Goede2015-01-14-11/+20
| | | | | | | | | Add a sunxi_hdmi_edid_get_block helper function, this is a preparation patch for adding support for parsing EDID extension blocks. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Anatolij Gustschin <agust@denx.de>
* sunxi: video: Add hdmi supportHans de Goede2015-01-14-5/+61
| | | | | | | | | | | | | | | | | So far we've been programming the hdmi-encoder to send out dvi data over the hdmi connector. This works well for most devices, including hdmi devices, but not all devices accept dvi data on a hdmi input. Add support for sending proper hdmi data over the hdmi output found on most sunxi boards. This can be turned on by adding monitor=hdmi as option to the video-mode env. variable. A follow up patch will determine whether to send dvi or hdmi automatically when EDID is used. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Anatolij Gustschin <agust@denx.de>
* sunxi: video: Add DDC & EDID supportHans de Goede2015-01-14-1/+153
| | | | | | | | | | Add DDC & EDID support and use it to automatically select the native mode of the attached monitor. This can be disabled by adding edid=0 as option to the video-mode env. variable. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Anatolij Gustschin <agust@denx.de>
* sunxi: video: Add hpd optionHans de Goede2015-01-14-9/+17
| | | | | | | | | | Allow the user to specify hpd=0 as option in the video-mode env. variable, if hpd is set to 0 then the hdmi output will be brought up even if no cable is connected. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Anatolij Gustschin <agust@denx.de>
* sunxi: video: Add support for video-mode environment variableHans de Goede2015-01-14-3/+13
| | | | | | | | | | | | | | | | Add support for the standard video-mode environment variable using the videomodes.c video_get_ctfb_res_modes() helper function. This will allow users to specify the resolution e.g. : setenv video-mode sunxi:video-mode=1280x1024-24@60 saveenv Also make the reserved fb mem slightly larger to allow 1920x1200 to work. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Anatolij Gustschin <agust@denx.de>
* sunxi: video: Use video-mode/-timing from videomodesHans de Goede2015-01-14-31/+12
| | | | | | | | | Switch from fb_videomode to ctfb_res_modes and use the predefined videotimings from videomodes.c, rather then defining our own. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Anatolij Gustschin <agust@denx.de>
* videomodes: Add video_edid_dtd_to_ctfb_res_modes helper functionHans de Goede2015-01-14-0/+76
| | | | | | | | Add a video_edid_dtd_to_ctfb_res_modes helper function to convert an EDID detailed timing to a struct ctfb_res_modes. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Anatolij Gustschin <agust@denx.de>
* videomodes: Add helper functions to parse video-mode env-var extra optionsHans de Goede2015-01-14-1/+64
| | | | | | | | Add 2 helper functions to get strings, respectively integers from the options value returned by video_get_video_mode() / video_get_ctfb_res_modes(). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Anatolij Gustschin <agust@denx.de>
* videomodes: Add video_get_ctfb_res_modes helper functionHans de Goede2015-01-14-0/+45
| | | | | | | | | Add a video_get_ctfb_res_modes() helper function, which uses video_get_video_mode() to parse the 'video-mode' environment variable and then looks up the matching mode in res_mode_init and returns the matching mode. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Anatolij Gustschin <agust@denx.de>
* videomodes: Add a bunch of high res modesHans de Goede2015-01-14-1/+9
| | | | | | | Add modes useful for hd-tvs and modern monitors. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Anatolij Gustschin <agust@denx.de>
* videomodes: Add (vesa) standard timingsHans de Goede2015-01-14-0/+9
| | | | | | | | | | | | | | | | The timings for the modes defined in videomodes.c differ (significantly) from vesa standard timings for these modes. This commit adds a version with the proper std timings for these modes, since I do not want to cause regressions, boards which want to use the standard timings need to define CONFIG_VIDEO_STD_TIMINGS to get the new correct timings. Since there is no std timing for 960x720 this commit uses the timing used by the nvidia video drivers for 960x720, which uses a standard pixelclock of 74.25 MHz rather then the weird 76.335... clock used by the old modes. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Anatolij Gustschin <agust@denx.de>
* videomodes: Add pixelclock_khz and refresh fields to ctfb_res_modesHans de Goede2015-01-14-7/+11
| | | | | | | | | | | | | | | | | | Add pixelclock_khz and refresh fields to ctfb_res_modes: 1) pixelclocks are usually referred to in hz, not picoseconds, and e.g pll-s are also typically programmed in hz, not ps. Converting between the 2 leads to rounding differences, add a pixelclock_khz field to directly store the *exact* pixelclock for a mode, so that drivers do not need to resort to rounding tricks to try and guess the exact pixelclock; 2) The video-mode environment variable, as parsed by video_get_video_mode also contains the vertical refresh rate, add a refresh field, so that the refresh-rate can be matched when parsing the video-mode environment variable. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Anatolij Gustschin <agust@denx.de>
* sunxi: axp221: Explicitly turn off unused voltagesHans de Goede2015-01-14-14/+104
| | | | | | | | | Explicitly turn off unused voltages, rather then leaving them as is. Likewise explictly enabled the dcdc convertors, rather then assuming they are already enabled at boot. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: axp221: Make dcdc1 voltage configurableHans de Goede2015-01-14-0/+10
| | | | | | | | | | The dcdc1 voltage is typically used as generic 3.3V IO voltage for things like GPIO-s, sdcard interfaces, etc. On most boards this is undervolted to 3.0V to safe battery, but not on all, make it configurable so that we can use the same settings as the original firmware on all boards. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: axp221: Add Kconfig help and sane defaults for typical ldo usageHans de Goede2015-01-14-6/+14
| | | | | | | | | Some of the ldo-s of the axp221 are used in the same way on most boards, add comments to the Kconfig help text to reflect this, and give them defaults matching their typical usage. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: axp221: Add axp223 supportHans de Goede2015-01-14-25/+71
| | | | | | | | | The axp223 appears to be the same as the axp221, except that it uses the rsb to communicate rather then the p2wi. At least all the registers we use are 100% the same. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* mmc: sunxi: Fix misuse of gpio_direction_input()Axel Lin2015-01-14-3/+6
| | | | | | | | | | | | It does not make sense to make gpio_direction_input() return the gpio input status. The return value of gpio_direction_input() is inconsistent if CONFIG_DM_GPIO is defined. And we don't need to call gpio_direction_input() int sunxi_mmc_getcd(). Just init the gpio once in mmc_resource_init() is enough. Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
* sun6i: axp221: Add axp221_get_sid functionHans de Goede2015-01-14-0/+27
| | | | | | | | For sun6i the SID is stored in the pmic, rather then in the SoC itself, add a function to retreive the sid. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: mmc: Properly setup mod-clk and clock sampling phasesHans de Goede2015-01-14-27/+68
| | | | | | | | | | | | | | | | | | | | | | | The sunxi mmc controller has both an internal clock divider, as well as the divider in the mod0-clk for the mmc controller. The internal divider cannot be used, as it conflicts with the setting of clock sampling phases which is done in the mod0-clk, so it must be set to 0 (divide by 1). For some reason while the kernel has had this correct from day one, the u-boot sunxi mmc code has been using a fixed mod0-clk and setting its internal divider depending on the desired speed. This is something which we've inherited from the original Allwinner u-boot sources, but while this has been fixed in Allwinner's own u-boot code at least for the A23 and later upstream u-boot was still doing this wrong. This commit fixes this, thereby also fixing mmc support not working reliable on the A23 (which seems more sensitive to this) and possible also fixes some other sunxi mmc issues. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* x86: Make chromebook_link the default board for corebootBin Meng2015-01-13-0/+8
| | | | | | | | | | | | | | | Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link which is currently the only real board officially supported to run U-Boot loaded by coreboot. Note the symbolic link file chromebook_link.dts is deleted and link.dts is renamed to chromebook_link.dts. To avoid multiple definition of video_hw_init, the CONFIG_VIDEO_X86 define needs to be moved to arch/x86/cpu/ivybridge/Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: pci: Display vesa modes in hexSimon Glass2015-01-13-2/+2
| | | | | | | | The hex value is more commonly understood, so use that instead of decimal. Add a 0x prefix to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: video: Add debug option to time the BIOS copySimon Glass2015-01-13-0/+3
| | | | | | | | This can be very slow - typically 80ms even on a fast machine since it uses the SPI flash to read the data. Add an option to display the time taken. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: pci: Don't return a vesa mode when there is not videoSimon Glass2015-01-13-1/+1
| | | | | | | If the video has not been set up, we should not return a success code. This can be detected by seeing if any of the variables are non-zero. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: video: Add a debug() to display the frame buffer addressSimon Glass2015-01-13-0/+1
| | | | | | Provide a way to display this address when booting. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Use ePAPR defined properties for x86-uartBin Meng2015-01-13-1/+7
| | | | | | | | | Use ePAPR defined properties for x86-uart: clock-frequency and current-speed. Assign the value of clock-frequency in device tree to plat->clock of x86-uart instead of using hardcoded number. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* serial: ns16550: Support ns16550 compatible pci uart devicesBin Meng2015-01-13-0/+31
| | | | | | | | | | | | | | There are many pci uart devices which are ns16550 compatible. We can describe them in the board dts file and use it as the U-Boot serial console as specified in the chosen node 'stdout-path' property. Those pci uart devices can have their register be memory-mapped, or i/o-mapped. The driver will try to use the memory-mapped register if the reg property in the node has an entry to describe the memory-mapped register, otherwise i/o-mapped register will be used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* fdt: Add several apis to decode pci device nodeBin Meng2015-01-13-1/+2
| | | | | | | | | | | | | | This commit adds several APIs to decode PCI device node according to the Open Firmware PCI bus bindings, including: - fdtdec_get_pci_addr() for encoded pci address - fdtdec_get_pci_vendev() for vendor id and device id - fdtdec_get_pci_bdf() for pci device bdf triplet - fdtdec_get_pci_bar32() for pci device register bar Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> (Include <pci.h> in fdtdec.h and adjust tegra to fix build error)
* pci: Make pci apis usable before relocationBin Meng2015-01-12-8/+17
| | | | | | | | | | | | | | Introduce a gd->hose to save the pci hose in the early phase so that apis in drivers/pci/pci.c can be used before relocation. Architecture codes need assign a valid gd->hose in the early phase. Some variables are declared as static so change them to be either stack variable or global data member so that they can be used before relocation, except the 'indent' used by CONFIG_PCI_SCAN_SHOW which just affects some print format. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* mtd: nand: do not scan BBT after scrubMasahiro Yamada2015-01-09-8/+3
| | | | | | | | | | | | | | | | | Currently, "nand scrub" runs chip->scan_bbt at the end of nand_erase_opts() even if NAND_SKIP_BBTSCAN flag is set. It violates the intention of NAND_SKIP_BBTSCAN. Move NAND_SKIP_BBTSCAN flag check to nand_block_checkbad() so that chip->scan_bbt() is never run if NAND_SKIP_BBTSCAN is set. Also, unset NAND_BBT_SCANNED flag instead of running chip->scan_bbt() right after scrub. We can be lazier here because the BBT is scanned at the next call of nand_block_checkbad(). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Scott Wood <scottwood@freescale.com>
* mtd: nand: Mark the BBT as scanned prior to calling scan_bbt againMasahiro Yamada2015-01-09-1/+1
| | | | | | | | | | | | | | | | | | | | | Commit 35c204d8a9d0 (nand: reinstate lazy bad block scanning) broke NAND_BBT_USE_FLASH feature. Its git-log claimed that it reinstated the change as by commit fb49454b1b6c ("nand: reinstate lazy bad block scanning"), but it moved "chip->options |= NAND_BBT_SCANNED" below "chip->scan_bbt(mtd);". It causes recursion if scan_bbt does not find a flash based BBT and tries to write one, and the attempt to erase the BBT area causes a bad block check. Reinstate commit ff49ea8977b5 (NAND: Mark the BBT as scanned prior to calling scan_bbt.). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Rostislav Lisovy <lisovy@merica.cz> Cc: Heiko Schocher <hs@denx.de> Cc: Scott Wood <scottwood@freescale.com>
* mtd: nand: revive "nand scrub" commandMasahiro Yamada2015-01-09-1/+1
| | | | | | | | | Since commit ff94bc40af34 (mtd, ubi, ubifs: resync with Linux-3.14), the "nand scrub" command has not been working. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Heiko Schocher <hs@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-01-08-53/+303
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| * qspi:fsl implement AHB readPeng Fan2015-01-09-10/+142
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The QSPI controller in i.MX 6SoloX and Vybrid supports reading data using IP register and AHB bus. The original driver only supports reading data from IP interface. The IC team suggests to use AHB read which is faster then IP read. Using AHB read, we can directly memcpy, a "missed" access to the buffer will cause the controller to clear the buffer and use the SEQID stored in bfgencr register to initiate a read from flash device. Since AHB bus is 64 bit width, we can not set MCR register using 32bit. In order to minimize code change, redefine QSPI_MCR_END_CFD_LE to 64bit Little endian but not 32bit Little endia. Introduce a new configuration option CONFIG_SYS_FSL_QSPI_AHB. If want to use AHB read, just define CONFIG_SYS_FSL_QSPI_AHB. If not, just ignore it. Actually if Vybrid is migrated to use AHB read, this option can be removed and IP read function can be discared. The reason to introduce this option is that only i.MX SOC is tested in my side, no Vybrid platform for me. In spi_setup_slave, the original piece code to set AHB is deleted, since Vybrid platform does not use this to intiate AHB read. Instead, add qspi_init_ahb_read function if defined CONFIG_SYS_FSL_QSPI_AHB. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * spi: ftssp010_spi: Simplify code flow in ftssp010_[wait|wait_tx|wait_rx]Axel Lin2015-01-08-24/+12
| | | | | | | | | | | | | | No functional change, just simplify the code a bit. Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * spi: cadence_qspi: Fix checking return value of fdt_first_subnode()Axel Lin2015-01-07-1/+1
| | | | | | | | | | | | | | | | fdt_first_subnode() returns -FDT_ERR_NOTFOUND if no subnode found. 0 is supposed to be a valid offset returns from fdt_first_subnode(). Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * spi:fsl-quadspi support bank register read writePeng Fan2015-01-07-15/+145
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To support bigger than 16MB size qspi flashes, spi framework uses bank switch to access higher bank or lower bank. In this patch, QSPI_CMD_BRRD, QSPI_CMD_BRWR, QSPI_CMD_WREAR, QSPI_CMD_RDEAR is initialized in LUT register with related pad and length configuration. qspi_op_pp is originally for page programming, this patch reuses this function for bank register switch and renamed it with qspi_op_write. Since bank or EAR register is only 1 byte length, however original qspi_op_pp or now renamed qspi_op_write only support 4 bytes lenght as the access unit, this will trigger data abort exception when access EAR or bank register. This is because upper framework passes a 1 bytes pointer to qspi_op_write, however qspi_op_write treat it as an int pointer. This patch fixes this for accessing EAR or bank register. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * dt: socfpga: Rename snps, dw-spi-mmio to snps, dw-apb-ssiMarek Vasut2015-01-06-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux now also contains SPI driver, yet the name is 'snps,dw-apb-ssi'. Fix the naming before we have to support both names. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * spi: designware_spi: Fix detecting FIFO depthAxel Lin2015-01-06-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current code tries to find the highest valid fifo depth by checking the value it wrote to DW_SPI_TXFLTR. There are a few problems in current code: 1) There is an off-by-one in dws->fifo_len setting because it assumes the latest register write fails so the latest valid value should be fifo - 1. 2) We know the depth could be from 2 to 256 from HW spec, so it is not necessary to test fifo == 257. In the case fifo is 257, it means the latest valid setting is fifo = 256. So after the for loop iteration, we should check fifo == 2 case instead of fifo == 257 if detecting the FIFO depth fails. This patch fixes above issues. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | i2c:mxc fix array size of i2c_dataPeng Fan2015-01-08-11/+11
| | | | | | | | | | | | | | | | | | | | | | We should not hardcode array size of i2c_data to 3. To CONFIG_FSL_LSCH3, there are 4 i2c interface, but not 3. So the size of i2c_data array should be calculated using "ARRAY_SIZE(i2c_bases)". To avoid compile error, move i2c_bases before sram_data structure which contains i2c_data array. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mmcTom Rini2015-01-06-43/+60
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