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* ENGR00161852: remove u-boot build warnings for mx6qTerry Lv2011-11-10-1/+5
| | | | | | Remove u-boot build warnings for mx6q. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00161277 Add fuse access capability for MX6 Sabre-liteMahesh Mahadevan2011-11-02-1/+1
| | | | | | Add support to read and program fuses in the MX6 Sabre-lite Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
* ENGR00139215 iMX61 Uboot support blow fuseRyan QIAN2011-11-02-0/+257
| | | | | | | | 1. add force option to blow operation 2. add blown value check 3. add simple validation for zeros returned by 'simple_strtoul' call Signed-off-by: Ryan QIAN <b32804@freescale.com>
* ENGR00161004 MX6Q Uboot Rename sabreauto to arm2 boardAnish Trivedi2011-10-28-2/+2
| | | | | | | | | Sabreauto is an inaccurate name for the Armadillo2 board that this code is actually meant for. So, replaced "sabreauto" in folder names, file names, configs, and code with "arm2". Created a new machine id for ARM2 board. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00139221 USDHC Add SDXC UHS-I supportAnish Trivedi2011-10-27-19/+288
| | | | | | | Modified MMC library for UHS-I command sequence Added support to USDHC driver for UHS-I Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00160399 Added support for the MX6Q Sabre-lite boardMahesh Mahadevan2011-10-25-29/+36
| | | | | | Includes support for uSDHC read, write, FEC, SPI-NOR etc. Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
* ENGR00160725 fastboot: fix the serial number display errorXinyu Chen2011-10-25-1/+1
| | | | | | Incorrect usb string package size assign. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
* ENGR00156670-2 MMC: Fixed some bugs in common codeAnish Trivedi2011-09-13-1/+1
| | | | | | | | | | | | | Need to send RCA when sending CMD13. Cannot use print_size function when displaying card capacity because it expects a 32 bit integer as input, while mmc->capacity is a 64 bit integer. There is loss of information leading to incorrect capacities being displayed for "mmcinfo" cmd. Changed it to simply print the entire 64 bit integer, which is the number of bytes. Signed-off-by: Tony Lin <tony.lin@freescale.com> Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00156670-1 ESDHC/USDHC: Remove delay before each cmd and some bug fixesAnish Trivedi2011-09-13-8/+13
| | | | | | | | | | | | Removed delay of 10 ms before each command. There should not be a need to have this delay after the ENGR00156405 patch that polls until card is not busy anymore before proceeding to next cmd. Added poll on reset bits of controller after the bits are set to wait until they clear before proceeding further. Signed-off-by: Tony Lin <tony.lin@freescale.com> Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00156405 ESDHC: Add workaround for auto-clock gate errata ENGcm03648Anish Trivedi2011-09-13-2/+33
| | | | | | | | | | | | The errata, not applicable to USDHC, causes ESDHC to shut off clock to the card when auto-clock gating is enabled for commands with busy signalling and no data phase. The card might require the clock to exit the busy state, so the workaround is to disable the auto-clock gate bits in SYSCTL register for such commands. The workaround also entails polling on DAT0 bit in the PRSSTAT register to learn when busy state is complete. Auto-clock gating is re-enabled at the end of busy state. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00156304 eMMC: Need to update partition config after changing boot partitionAnish Trivedi2011-09-08-32/+33
| | | | | | | | | | | | | | | | After enabling boot partition on an eMMC using "mmc bootpart" command, the partition configuration variable that is supposed to track this value on the eMMC is not updated. This leads to stale and possibly inaccurate boot partition number being printed when "mmcinfo" command is used, thereby confusing the user. The fix is to update the part_config variable of mmc struct with the new value that was just written to the eMMC. Also removed condition that restricted boot_bus_width programming (for fastboot) to eMMC with DDR support only. Now, even non-DDR capable eMMCs can be programmed for fastboot (in SDR mode). Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00139254: Enable MX6Q Uboot Splash ScreenSandor Yu2011-09-02-30/+68
| | | | | | | | | | | | | | Only support LVDS0 splash screen. Enable splash process: 1.define CONFIG_SPLASH_SCREEN in mx6q_sabreauto.h 2.Config U-boot with followed command:() setenv splashimage '0x30000000' #Set splash position as Center setenv splashpos 'm,m' #Set LVDS via LVDS bridge 0 setenv lvds_num 0 Signed-off-by: Sandor Yu <r01008@freescale.com>
* ENGR00154666-4: Align u-boot mmc command with communityTerry Lv2011-09-01-3/+1
| | | | | | | Change fastboot code for that fastboot uses mmc command to access card. Thus the code need to be modified to new mmc command. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00154666-3: Align u-boot mmc command with communityTerry Lv2011-09-01-326/+552
| | | | | | | | | | | This patch will enhance mmc command. 1. Add erase command. 2. Abandon dev_no in mmc command. User need to switch slot with "mmc dev" command. 3. Add mmc part switch command. Enhance partition switch support. 4. Add mmc bootpart. Boot partition support is more flexible. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00153759 mx51: fix fastboot build failed without boot partition macroXinyu Chen2011-07-27-0/+2
| | | | | | | In mx51 configuration, CONFIG_BOOT_PARTITION_ACCESS is not defined. This cause build error to fastboot.c Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
* ENGR00153605 fastboot: uboot cannot be burned to boot partitionSammy He2011-07-26-1/+6
| | | | | | | uboot image cannot be burned to boot partition for eMMC 4.3. This patch will fix it. Signed-off-by: Sammy He <r62914@freescale.com>
* ENGR00152755 MX6 Switch DRAM init script from plugin to DCD for emmc fastbootAnish Trivedi2011-07-06-2/+6
| | | | | | | | | | | | | | | | | ROM requires DCD table instead of plugin to initialize DRAM if emmc fastboot mode is to be used. Therefore, switched the DRAM script from plugin to DCD table. The DCD table created is based on the following RVD script: Arik_init_DDR3_528MHz_002.inc found at http://compass.freescale.net/livelink/livelink?func=ll&objId=222928845 When fastboot mode is used by ROM, the MMC_BOOT register of USDHC does not get reset when RSTA bit is set by uboot driver. Therefore, need to write 0 to it manually during driver init. This brings USDHC out of fastboot mode, allowing normal communication with emmc to proceed in uboot. Changed comments for DLL delay to be more accurate. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00139206 MX6 USDHC eMMC 4.4 supportAnish Trivedi2011-07-05-14/+42
| | | | | | | | | | | New bit definitions in USDHC. Added is_usdhc variable to fsl_esdhc_cfg to distinguish between ESDHC and USDHC. Enabled DDR mode support in USDHC. Created a config to customize target delay for DDR mode. Modified USDHC pad settings to make DDR mode work for all emmcs at 50 MHz. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00152241 MX6: enable 1G speed mode for PHY and ENETZeng Zhaoming2011-06-29-10/+41
| | | | | | | | | | | | | In precode, PHY forced to work at 100M even connect to 1G switch. In this commit, let PHY auto negotiate it working speed. Enet tx work at store-and-forward mode. BTW, AR8031 take quite a long time, about 1.6s from negotiation to link up. we have to wait and then set ENET correctly. Signed-off-by: Zeng Zhaoming <b32542@freescale.com>
* ENGR00139198: iMX61 uBoot add ENET supportZeng Zhaoming2011-06-27-5/+69
| | | | | | | | | | | | | | | | Add ENET and AR8031 PHY support to uboot. To make it works on sabreauto, need do following changes: 1. rework phy to output 125M clock from CLK_25M signal, and the 125M clock input to SoC as reference clock to generate RGMII_TXC clock. 2. Enable TXC delay in PHY debug register. 3. set ENET working in RMII mode. 4. set ENET working at 1000M or 100M/10M. 5. set ENET TX fifo to maximum to avoid underrun error. 6. force AR8031 PHY working at 100M Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Zeng Zhaoming <b32542@freescale.com>
* ENGR00144424 MX6: enable uboot for ARM2(SABREAUTO) CPU boardAnson Huang2011-06-24-7/+14
| | | | | | | | | | | | | Use 528M DDR script Disable L2 cache because rom enable L2 cache when use plug-in Fix usdhc pad settings Remove mac address hardcode Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Richard Zhu <r65037@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com> Signed-off-by: Anish Trivedi <anish@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00143704: U_BOOT: Nand oobsize is wrong in some nand chipsTerry Lv2011-05-20-7/+11
| | | | | | Nand oobsize is wrong in some nand chips. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00142995 MX50: Enable uSDHC instead of eSDHC for SDR modeAnish Trivedi2011-05-10-6/+30
| | | | | | | | | | | | | | | | | | On SD3 on MX50, there is an option to choose eSDHC or uSDHC controller. By default eSDHC is selected. However, eSDHC shows some borderline timing in SDR mode at 50 MHz, whereas uSDHC shows borderline timing in DDR mode at 50 MHz. Therefore, add a compile time option to uboot for MX50 to select uSDHC in SDR mode or eSDHC in DDR mode on SD3 port. By default the compile time option, CONFIG_MX50_ENABLE_USDHC_SDR, is commented out in the include/configs/mx50_<board>.h file to select eSDHC with DDR mode enabled. Uncomment the define to select uSDHC with only SDR mode enabled. Also increased max frequency supported by ESDHC to 52 MHz instead of 50 MHz. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00142322: mx53-smd: spi nor: can't erase 0x200000 sizeTerry Lv2011-04-20-13/+13
| | | | | | | | | | | | | Spi nor can't erase 0x200000 size. There are two issues in this CR. 1. Spi nor can't erase 0x200000 size. 2. Whole chip erase don't work. The solution will be: 1. Delay more time for WIP check. 2. Use normal erase for whole chip erase. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00141335-1: Use bypass way to set ddr dll in mx53Terry Lv2011-04-11-1/+1
| | | | | | | | Usually dll setup for eMMC4.4 DDR is required to polling SLV_LOCK status bit. However the system hangs when polling for SLV_LOCK bit. The temporary workaround is to force slave override mode to bypass it. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00141556: Fix copyright issueTerry Lv2011-04-08-28/+11
| | | | | | | | | | | We're following the following rules: 1. FSL copyright should be added for freescale added and modified files. 2. FSL copyright should go after existing copyrights. 3. For Duplicate FSL copyright, Our copyright will go after that also. 4. FSL copyright should not include personal names as part. 5. For only FSL copyright, "All rights reserved" is not mattered. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00140873: MMC may wrongly regconize 2GB eMMC as high capacityTerry Lv2011-03-21-2/+4
| | | | | | | | | | | | MMC driver may wrongly regconize some 2GB eMMC as high capacity card. This patch is picked from community. A non-zero value of SEC_COUNT does not indicate that the card is sector addressed. According to the MMC specification, cards with a densitygreater than 2GiB are sector addressed. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00140486 Add SPI NOR Flash M25P32 driverRobby Cai2011-03-18-0/+549
| | | | | | | So far, it's supposed to be on MX50 RD3 and MX53 SMD Signed-off-by: Robby Cai <R63905@freescale.com> (cherry picked from commit 0e3d67cd1a2dc30af80e5119b626d997be254991)
* ENGR00138533: Fix sata write operation random failure issueTerry Lv2011-03-02-1/+3
| | | | | | | Parameter of calling to memalign is wrong. Thus need to modify it. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00138549 Android fastboot: Support eMMC4.4 on imx53_smdrel_imx_2.6.35_11.01.00Sammy He2011-01-28-13/+45
| | | | | | | | Support eMMC4.4 storage on imx53_smd android fastboot, using environment to control it, the command is: > setenv fastboot_dev mmc1 Signed-off-by: Sammy He <r62914@freescale.com>
* ENGR00138422-3 Android fastboot: Pass block offset to cmd_fastbootSammy He2011-01-27-16/+18
| | | | | | Pass mmc/sata block offset from fastboot driver to cmd_fastboot, not byte. Signed-off-by: Sammy He <r62914@freescale.com>
* ENGR00138422-2 Add SATA storage support for android fastbootSammy He2011-01-26-39/+72
| | | | | | Add SATA storage support for android fastboot. Signed-off-by: Sammy He <r62914@freescale.com>
* ENGR00138422-1 Fix usb connection failure if do sata initSammy He2011-01-26-8/+19
| | | | | | | Increase memory alignment to fix usb connection failure issue if do sata init, and support MMU disable case in imx_udc driver. Signed-off-by: Sammy He <r62914@freescale.com>
* ENGR00138359 Change uramdisk from 6M byte offset of android fastbootSammy He2011-01-22-5/+5
| | | | | | | Change uramdisk from 6M byte offset of android fastboot due to kernel image size more than 3M now. Signed-off-by: Sammy He <r62914@freescale.com>
* ENGR00137894-4 IPUv3 FB: IPUv3 FB driver enhancementLiu Ying2011-01-14-4/+4
| | | | | | | | 1) Change MX51 related function names to IPUv3 related names. 2) Change MX51 related comments to IPUv3 related comments. 3) Do not set panel_info.cmap to be NULL pointer. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00137894-3 IPU driver enhancementLiu Ying2011-01-14-27/+49
| | | | | | | | 1) Remove MX51 related comments in ipu drivers. 2) Add di clocks. 3) Support pixel clock being deprived from external clock. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00137894-1 Add imx pwm driver supportLiu Ying2011-01-13-0/+121
| | | | | | | This patch adds imx pwm driver support as a misc device. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00136869: SATA device can't init and a typo in sata helpTerry2011-01-11-2/+2
| | | | | | | | | | | | | | | | | | SATA device can't init and a typo in sata help. Add delay in sata detect proceduce. Currently, I have met 3 problems for this issue. 1. Seagate HD. It needs 1000 for timeout. 2. Hitachi HD. It needs 10000 for timeout. 3. In sata env case, it needs 100000 for timeout. 10000000 for timeout is just to avoid a dead loop, And suppose this timeout should be enough for all normal case. It doesn't mean all HD need to wait this long time, If tfd is ok, the loop will be breaked immediately. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00137767 IPUv3 video:Support splashimage with MMU disabledLiu Ying2011-01-10-2/+6
| | | | | | | | This patch corrects the fbi->screen_base value and fbi->fix.smem_start value when MMU is disabled. Reported-by: Terry Lv <r65388@freescale.com> Signed-off-by: Liu Ying <b17645@freescale.com>
* ENGR00137713 MX53 Uboot SMSC Fix order in which mac addr bytes are read from IIMAnish Trivedi2011-01-07-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Given that an example mac addr is 00-11-22-33-44-55, it should be fused into the IIM at the following locations: 0xC24 - 00 0xC28 - 11 0xC2C - 22 0xC30 - 33 0xC34 - 44 0xC38 - 55 Then, when reading the bytes into a mac array, it should be read as follows: mac[0] - 00 mac[1] - 11 mac[2] - 22 mac[3] - 33 mac[4] - 44 mac[5] - 55 Previously, it was read into the array in reverse order. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00137603 Add mx53_smd_android config for androidSammy He2011-01-08-2/+1
| | | | | | Add mx53_smd_android config for android build. Signed-off-by: Sammy He <r62914@freescale.com>
* ENGR00137596 MX53 Uboot SMC911X driver needs to get mac addr from IIMAnish Trivedi2011-01-05-0/+25
| | | | | | | If the MAC addr read from the controller's ADDRH and ADDRL registers is invalid, then try to read MAC address programmed in MX53's IIM. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00136863-2: Fix mx53 CMD12 issue.Terry Lv2010-12-29-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | As in mx53 and lster socs, when using CMD12, cmdtype need to be set to ABORT, otherwise, next read command will hang. This is a software Software Restrictions in spec 29.7.8. For pre-defined multi-block read operation, i.e., The number of blocks to read has been defined by previous CMD23 for MMC, or pre-defined number of blocks in CMD53 for SDIO/SDCombo, or whatever multi-block read without abort command at card side, an abort command, either automatic or manual CMD12/CMD52, is still required by ESDHCV2 after the pre-defined number of blocks are done, to drive the internal state machine to idle mode. In this case, the card may not respond to this extra abort command and ESDHCV2 gets Response Timeout. It is recommended to manually send an abort command with RSPTYP[1:0] both bits cleared. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00136863-1: Change mmc framework architecture.Terry Lv2010-12-29-200/+134
| | | | | | | | | | Change mmc framework architecture. Mainly for code clean and restructure. Mainly merge our code with community code. Based on commit 17b4c8e9eb30e3eb305baef98eb23325e61db592. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00137390 UBOOT:NAND: BBT not found on MX53 boardJason Liu2010-12-27-0/+7
| | | | | | | | | | BBT table can't be found on MX53 board, which is due to that the BBT table flag has been written to the ECC area which cause the BBT flag lost. This patch also fix the BBT version not correct issue. Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00134068 MX51 BBG:Support CLAA WVGA splashimageLiu Ying2010-12-16-18/+49
| | | | | | | | | | | 1) IOMUX/backlight support for CLAA WVGA LCD panel. 2) Add video mode for CLAA WVGA LCD panel. 3) Support IPU di1 interface for framebuffer. 4) Enhance IPU driver. 5) Add freescale 600x400 8BPP BMP logo. Signed-off-by: Terry Lv <R65388@freescale.com> Signed-off-by: Liu Ying <b17645@freescale.com>
* ENGR00136038: Remove config CONFIG_EMMC_DDR_MODETerry Lv2010-12-10-21/+13
| | | | | | | | | 1. As we can check DDR dynamically, remove CONFIG_EMMC_DDR_MODE in mmc.c. 2. Add config CONFIG_EMMC_DDR_PORT_DETECT config for some boards that only some board support DDR. Signed-off-by: Terry Lv <r65388@freescale.com>
* MX51: Add video supportStefano Babic2010-12-10-0/+643
| | | | | | | | | | | | | | Add framebuffer driver for the MX51 processor working on the IPUv3 internal graphic processor. The port is based on the driver found in the kernel delivered by Freescale as part of i.MX BSP: [kernel 2.6.31 commit cc4fe714041805997b601fe8e5dd585d8a99297f] [agust@denx.de: some style fixes and dead code removal] Signed-off-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Anatolij Gustschin <agust@denx.de> (cherry picked from commit 5dda7945d18077db81eb0cfdc2f9d4525e6b77b1)
* MX51: Add IPU driver for video supportStefano Babic2010-12-10-0/+2916
| | | | | | | | | | | | | The patch is a porting of the IPU Linux driver developed by Freescale to have framebuffer functionalities in u-boot. The port is based on kernel 2.6.31 commit cc4fe714041805997b601fe8e5dd585d8a99297f, as delivered by Freescale [i.MX BSP]. Most features are dropped from the original driver and only LCD support is the goal of this porting. Signed-off-by: Stefano Babic <sbabic@denx.de> (cherry picked from commit 575001e40c9d10e63f2924649098e7c07d3985c7)
* ENGR00134220-1 NAND: fix up the chip select handlingJason Liu2010-12-07-10/+16
| | | | | | | | When the NAND has multi-cs, the chip select other than cs0 is not handled correctly which will lead to NAND not function as expected Signed-off-by: Jason Liu <r64343@freescale.com>
generated by cgit v1.1 at 2024-11-26 09:12:15 +0000