summaryrefslogtreecommitdiff
path: root/drivers
Commit message (Collapse)AuthorAgeLines
* mmc: Enabled quirk SDHCI_QUIRK_BROKEN_R1BSiva Durga Prasad Paladugu2014-02-07-1/+2
| | | | | | | | | | | | | As per the below commit "mmc: sdhci: add the quirk for broken r1b response" (sha1: 3a6383207be3f71b39004e64464a6e99290b16fa) need to add quirk SDHCI_QUIRK_BROKEN_R1B, when the response type is R1b. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* MMC: DWMMC: Correct the CLKDIV register valueRajeshwari S Shinde2014-02-07-3/+16
| | | | | | | | | | | | | | | | | | This patch corrects the divider value written to CLKDIV register. Since SDCLKIN is divided inside controller by the DIVRATIO value set in the CLKSEL register, we need to use the same output clock value to calculate the CLKDIV value. as per user manual: cclk_in = SDCLKIN / (DIVRATIO + 1) Input parameter to mmc_clk is changed to dwmci_host, since we need the same to read DWMCI_CLKSEL register. This improves the read timing values for channel 0 on SMDK5250 from 0.288sec to 0.144sec Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* mmc: set rca to 1 for MMC cardsStephen Warren2014-02-07-1/+1
| | | | | | | | | | U-Boot currently sets MMC cards' RCA register to 0. This value is reserved according to the specification. Use a value of 1 instead, just like the Linux kernel. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* Merge branch 'fpga' of git://www.denx.de/git/u-boot-microblazeTom Rini2014-02-06-0/+10
|\
| * fpga: zynq: Correct fpga load when buf is not alignedNovasys Ingenierie2014-02-06-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | When ARCH_DMA_MINALIGN is greater than header size of the bit file, and buf is not aligned, new_buf address became greater then buf_start address and the load_word loop corrupts bit file data. A work around is to decrease new_buf of ARCH_DMA_MINALIGN, it might corrupt data before buf but permits to load correctly. Signed-off-by: Stany MARCEL <smarcel@novasys-ingenierie.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | usb: mv_udc: Rename to ci_udcMarek Vasut2014-02-06-104/+104
| | | | | | | | | | | | | | | | | | | | The mv_udc is not marvell-specific anymore. The mv_udc is used to drive generic ChipIdea CI13xxx series OTG cores, so rename the driver to ci_udc instead. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Stefano Babic <sbabic@denx.de>
* | usb:gadget:f_thor: cosmetic: Remove debug memsetLukasz Majewski2014-02-06-2/+0
| | | | | | | | | | | | | | | | Apparently debug memset (with a 0x55 value) has been overlooked in the f_thor code. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
* | usb:gadget:f_thor: Allocate request up to THOR_PACKET_SIZE not ep->maxpacketLukasz Majewski2014-02-06-1/+1
| | | | | | | | | | | | | | | | Now it is possible to allocate static request - which receives data from the host (OUT transaction) to the size of THOR packet. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
* | usb:udc:samsung: Zero copy approach for data passed to Samsung's UDC driverLukasz Majewski2014-02-06-40/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Samsung's UDC driver is not anymore copying data from USB requests to aligned internal buffers. Now it works directly in data allocated in the upper layers like UMS, DFU, THOR. This change is possible since those gadgets now must take care to allocate buffers aligned to cache line (CONFIG_SYS_CACHELINE_SIZE). This can be achieved by using DEFINE_CACHE_ALIGN_BUFFER() or ALLOC_CACHE_ALIGN_BUFFER() macros. Those take care to allocate buffer aligned to cache line in both starting address and its size. Sometimes it is enough to just use memalign() with size being a multiplication of cache line size. Test condition - test HW + measurement: Trats - Exynos4210 rev.1 - test HW Trats2 - Exynos4412 rev.1 400 MiB compressed rootfs image download with `thor 0 mmc 0` Measurement: Transmission speed: 27.04 MiB/s Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
* | usb:udc:samsung: Allow burst transfers for non EP0 endpintsLukasz Majewski2014-02-06-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removed obscure restriction on the HW setting of DMA transfers. Before this change each transaction sent up to 512 bytes (with packet count equal to 1) for non EP0 transfer. Now it is possible to setup DMA transaction up to DMA_BUFFER_SIZE. Test condition - test HW + measurement: Trats - Exynos4210 rev.1 - test HW Trats2 - Exynos4412 rev.1 400 MiB compressed rootfs image download with `thor 0 mmc 0` Measurement: Transmission speed: 20.74 MiB/s Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
* | usb:udc:samsung: Remove redundant cache operation from Samsung UDC driverLukasz Majewski2014-02-06-17/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A set of cache operations (both invalidation and flush) were redundant in the S3C HS OTG Samsung driver: 1. s3c_udc_ep0_zlp - to transmit EP0's ZLP packets one don't need to flush the cache (since it is the zero length transmission) 2. s3c_udc_pre_setup and s3c_ep0_complete_out - cache invalidation is not needed when the buffer for OUT EP0 transmission is setup, since no data has yet arrived. Cache cleanups presented above don't contribute much to transmission speed up, hence shall be regarded as cosmetic changes. 3. setdma_rx - here the s3c UDC driver's internal buffers were invalidated. This call is not needed anymore since we reuse the buffers passed from gadgets. This is a key contribution to transmission speed improvement. Test condition - test HW + measurement: Trats - Exynos4210 rev.1 - test HW Trats2 - Exynos4412 rev.1 400 MiB compressed rootfs image download with `thor 0 mmc 0` Measurements: Base values (without improvement): Transmission speed: 9.51 MiB/s After the change: Transmission speed: 10.15 MiB/s Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
* | usb:gadget:ums: Replace malloc calls with memalign to fix cache buffer alignmentLukasz Majewski2014-02-06-2/+2
|/ | | | | | | | Calls to malloc() have been replaced by memalign. It now provides proper buffer alignment. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
* Merge branch 'serial' of git://www.denx.de/git/u-boot-microblazeTom Rini2014-02-04-1/+13
|\
| * serial: uartlite: Reset RX/TX in initMichal Simek2014-02-04-1/+13
| | | | | | | | | | | | Just to be sure that there is no pending data. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge branch 'net' of git://www.denx.de/git/u-boot-microblazeTom Rini2014-02-04-0/+9
|\ \
| * | net: axi_emac: Check if phy was correctly detectedMichal Simek2014-02-04-0/+4
| | | | | | | | | | | | | | | | | | | | | As tsec and fm drivers checking phydev->link ensure that u-boot don't try access device if link is not ready. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | net: gem: Check if phy was correctly detectedMichal Simek2014-01-21-0/+5
| |/ | | | | | | | | | | | | As tsec and fm drivers checking phydev->link ensure that u-boot don't try access device if link is not ready. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | driver/ifc:Change accessor function to take care of endiannessPrabhakar Kushwaha2014-02-03-151/+152
| | | | | | | | | | | | | | | | | | | | | | IFC registers can be of type Little Endian or big Endian depending upon Freescale SoC. Here SoC defines the register type of IFC IP. So update acessor functions with common IFC acessor functions to take care both type of endianness. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* | boards/t1040qds: Adds ethernet support for T1040Prabhakar Kushwaha2014-02-03-0/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable entherent for T1040QDS. It enables FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 Define MDIO related configs Added eth.c file Update t1040.c to support RGMII and SGMII Update t1040qds.c to support ethernet Define the PHY address Signed-off-by: Arpit Goel <B44344@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: remove dash from commit message] Signed-off-by: York Sun <yorksun@freescale.com>
* | driver/fsl_pci:Update print to display PCIe generationPrabhakar Kushwaha2014-02-03-2/+2
| | | | | | | | | | | | | | | | Current print only display width of PCIe device. Add print to display PCIe generation supported by the device. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | drivers: delete unused header filesMasahiro Yamada2014-01-24-1217/+0
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | esdhc: Detecting 8 bit width before mmc initializationHaijun.Zhang2014-01-22-0/+5
| | | | | | | | | | | | | | | | | | | | The upper 4 data signals of esdhc are shared with spi flash. So detect if the upper 4 pins are assigned to esdhc before enable sdhc 8 bit width. Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | esdhc: Workaround for card can't be detected on T4240QDSHaijun.Zhang2014-01-22-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Card detection pin is ineffective on T4240QDS Rev1.0. There are two cards can be connected to board. 1. eMMC card is built-in board, can not be removed. so For eMMC card it is always there. 2. Card detecting pin is functional for SDHC card in Rev2.0. This workaround force sdhc driver scan and initialize the card regardless of whether the card is inserted or not in case Rev1.0. Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | net/fm: revert commit 732dfe090d50af53bb682d0c8971784f8de1f90fShengzhou Liu2014-01-21-52/+1
| | | | | | | | | | | | | | | | This patch reverts patch 'add ft_fixup_xgec to support 3rd and 4th 10GEC'. When dual-role MAC acts as 10G,it still uses fsl,fman-port-1g-rx/tx as before. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* | powerpc:mpc85xx: Add ifc nand boot support for TPL/SPLPo Liu2014-01-21-7/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using the TPL method for nand boot by sram was already supported. Here add some code for mpc85xx ifc nand boot. - For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec. - Use a clear function name for nand spl boot. - Add CONFIG_SPL_DRIVERS_MISC_SUPPORT to compile the fsl_ifc.c in spl/Makefile; Signed-off-by: Po Liu <Po.Liu@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/mpc85xx: Revise workaround for DDR-A003York Sun2014-01-21-2/+67
| | | | | | | | | | | | | | | | | | | | | | | | Existing workaround only handles one RDIMM on reference design. In case of two RDIMMs being used, the workaround requires two separate writes to DDR_SDRAM_MD_CNTL register. This patch also restores two debug registers changed by the workaround. Signed-off-by: York Sun <yorksun@freescale.com> CC: Ben Collins <ben.c@servergy.com> CC: James Yang <James.Yang@freescale.com>
* | powerpc/t2080qds: some update for t2080qdsShengzhou Liu2014-01-21-4/+6
|/ | | | | | | | | | - add more serdes protocols support. - fix some serdes lanes route. - fix SGMII doesn't work and incorrect mdio display for XFI when serdes 0x6d. - correct boot location info for SD/SPI boot. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2014-01-20-5/+45
|\
| * i2c: fti2c010: fix compiler warning on paddr[]Kuo-Jung Su2014-01-13-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | This fixes the following compiler warnings: fti2c010.c: In function 'fti2c010_read': fti2c010.c:204:8: warning: 'paddr' may be used uninitialized in this function [-Wuninitialized] fti2c010.c: In function 'fti2c010_write': fti2c010.c:266:8: warning: 'paddr' may be used uninitialized in this function [-Wuninitialized] Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> Cc: Heiko Schocher <hs@denx.de>
| * drivers/designware_i2c - add suppor of CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOWAlexey Brodkin2014-01-13-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we agreed on legacy implementation of "eeprom_{read|write}" (http://patchwork.ozlabs.org/patch/295825/) I had to fix/make it work again DesignWare I2C driver for cases when 1 EEPROM IC fake I2C with anumber of "built-in" ICs with different chip addresses. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Tom Rini <trini@ti.com> cc: Armando Visconti <armando.visconti@st.com> Cc: Stefan Roese <sr@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Heiko Schocher <hs@denx.de> Cc: Vipin KUMAR <vipin.kumar@st.com> Cc: Tom Rix <Tom.Rix@windriver.com> Cc: Mischa Jonker <mjonker@synopsys.com> Cc: Kuo-Jung Su <dantesu@faraday-tech.com>
| * i2c: Fix i2c speed commandDarwin Rambo2014-01-13-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | This corrects i2c core to interpret the value returned by i2c_set_bus_speed as a success indicator rather than the actual speed that was set. When i2c_set_bus_speed returns a failure code, the speed is unknown so the adapter speed is set to zero. Signed-off-by: Darwin Rambo <drambo@broadcom.com> Reviewed-by: Tim Kryger <tim.kryger@linaro.org> Reviewed-by: Steve Rae <srae@broadcom.com> Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * rcar_i2c: Clear status before start master receiveNobuhiro Iwamatsu2014-01-13-0/+2
| | | | | | | | | | Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * rcar_i2c: Fix receiving wait conditionHisashi Nakamura2014-01-13-2/+2
| | | | | | | | | | Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* | nand, gpmc: fix reading after switching eccJeroen Hofstee2014-01-17-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The omap_gpmc allows switching ecc at runtime. Since the NAND_SUBPAGE_READ flag is only set, it is kept when switching to hw ecc, which is not correct. This leads to calling chip->ecc.read_subpage which is not a valid pointer. Therefore clear the flag when switching ecc so reading in hw mode works again. Cc: Scott Wood <scottwood@freescale.com> Cc: Pekon Gupta <pekon@ti.com> Cc: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-01-16-1/+2
|\ \
| * | spi: sh_qspi: Add header file that defines the address of registersNobuhiro Iwamatsu2014-01-16-1/+2
| |/ | | | | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2014-01-14-2/+2
|\ \
| * | net: phy: atheros: Fix the masks for AR8031/8035Fabio Estevam2014-01-14-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the same masks as used in the kernel: https://git.kernel.org/cgit/linux/kernel/git/stable/linux-stable.git/tree/drivers/net/phy/at803x.c?id=refs/tags/v3.12.6 With such changes Ethernet is functional on hummingboard solo. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Marek Vasut <marex@denx.de> Patch: 306640
* | | mmc: dwmmc: mode change to 0644Minkyu Kang2014-01-14-0/+0
| | | | | | | | | | | | | | | | | | Don't know why but, file permission was changed Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | fuelgauge: max17042: fix i2c read issue which causes infinity loop.Przemyslaw Marczak2014-01-14-34/+86
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issues: - reading i2c data by passing u16 pointer causes errors in read data. - max17042 status register fields have not only Power On Reset meaning so using proper mask is required. Changes: - read i2c data to type u32 instead of u16 - avoids buffer overflow - compare FG status register using mask not just one bit value - add checking return value to functions fg read/write - add model lock and model check count - add debug msg Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2014-01-13-188/+934
|\ \
| * | sf: params: Removed flag SECT_4K for Micron N25Q128Siva Durga Prasad Paladugu2014-01-12-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the flag SECT_4K for device N25Q128 as the 4K-byte sub sector erase granularity is available only for top/bottom 8 sectors in some of the N25Q128 chips. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | sf: Add CONFIG_SF_DUAL_FLASHJagannadha Sutradharudu Teki2014-01-12-5/+14
| | | | | | | | | | | | | | | | | | | | | This config will use for defining greater than single flash support. currently - DUAL_STACKED and DUAL_PARALLEL. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | sf: Add dual memories support - DUAL_PARALLELJagannadha Sutradharudu Teki2014-01-12-7/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch added support for accessing dual memories in parallel connection with single chipselect line from controller. For more info - see doc/SPI/README.dual-flash Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | sf: Add dual memories support - DUAL_STACKEDJagannadha Sutradharudu Teki2014-01-12-11/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch added support for accessing dual memories in stacked connection with single chipselect line from controller. For more info - see doc/SPI/README.dual-flash Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | sf: ops: Unify read_ops bank configurationJagannadha Sutradharudu Teki2014-01-12-8/+5
| | | | | | | | | | | | | | | | | | Unified the bar code from read_ops into a spi_flash_bar() Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | sf: Code cleanupsJagannadha Sutradharudu Teki2014-01-12-13/+8
| | | | | | | | | | | | | | | | | | | | | - comment typo's - func args have a proper names Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | sf: Divide flash register ops from QEB codeJagannadha Sutradharudu Teki2014-01-11-53/+77
| | | | | | | | | | | | | | | | | | | | | QEB code comprises of couple of flash register read/write operations, this patch moved flash register operations on to sf_op Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | sf: probe: Enable macronix quad read/write cmds supportJagannadha Sutradharudu Teki2014-01-11-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Added macronix flash quad read/write commands support and it's up to the respective controller driver usecase to configure the respective commands by defining SPI RX/TX operation modes from include/spi.h on the driver. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | sf: Add macronix set QEB supportJagannadha Sutradharudu Teki2014-01-11-0/+35
| | | | | | | | | | | | | | | | | | | | | This patch adds set QEB support for macronix flash devices which are trying to program/read quad operations. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
generated by cgit v1.1 at 2024-11-11 09:23:58 +0000