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* PPC: Cleanup tqm8xx_pcmcia.cMarek Vasut2011-10-05-73/+81
| | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Tested-by: Wolfgang Denk <wd@denx.de> Acked-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-nand-flashWolfgang Denk2011-10-04-72/+41
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-nand-flash: PPC: Fix socrates NAND problem PPC: Fix fsl_upm.c by renaming nand handling functions NAND: Make page, erase, oob size available via cmd_nand mtd: eLBC NAND: remove elbc_fcm_ctrl->oob_poi NAND: Add -y option to nand scrub command NAND: Add nand read.raw and write.raw commands NAND: Really ignore bad blocks when scrubbing spl, nand: add 4bit HW ecc oob first nand_read_page function mxc_nand: fix a problem writing more than 32MB mxc_nand: fixed some typos (cosmetic) nand: increase chip_delay in mv kirkwood nand driver
| * PPC: Fix fsl_upm.c by renaming nand handling functionsMarek Vasut2011-10-03-8/+8
| | | | | | | | | | | | | | | | This avoids colision with nand subsystem's functions. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * mtd: eLBC NAND: remove elbc_fcm_ctrl->oob_poimhench2011-10-03-30/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | The eLBC NAND driver currently follows up each program/write operation with a read-back of the page, in order to [ostensibly] fill in ECC data for the caller. However, the page address used for this read is always -1, so the read will never work correctly. Remove this useless (and potentially problematic) block of code. v2: fix broken mailer Signed-off-by: mhench <mhench@elutions.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * NAND: Really ignore bad blocks when scrubbingMarek Vasut2011-10-03-22/+9
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> [scottwood@freescale.com: use chip instead of redundant priv_nand] Signed-off-by: Scott Wood <scottwood@freescale.com>
| * mxc_nand: fix a problem writing more than 32MBHelmut Raiger2011-10-03-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When writing 0x4000 to the unlockend_blkaddr register, large writes to a 2k page NAND sometimes fail. The current kernel driver writes 0xFFFF to this register for V2 of the nand controller. However on an i.MX31 this also fixes writes larger than 32MB. The datasheet is very unspecific, but (0x4000=16384)*2000 roughly fits the limits we're encountering with NAND writes. This problem might be NAND chip specific. Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * mxc_nand: fixed some typos (cosmetic)Helmut Raiger2011-10-03-10/+9
| | | | | | | | | | Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * nand: increase chip_delay in mv kirkwood nand driverStefan Bigler2011-10-03-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The new SAMSUNG NAND Flash K9F1G08U0D require a bigger chip_delay. The Data Transfer from Cell to Register is >= 35us. Other Vendors and older chips normally use >= 25us. To have enough margin 40us is selected. Signed-off-by: Stefan Bigler <stefan.bigler@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> cc: Stefan Roese <sr@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2011-10-04-3/+3236
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-mpc85xx: powerpc/p3060: Add SoC related support for P3060 platform powerpc/85xx: Add support for setting up RAID engine liodns on P5020 powerpc/85xx: Refactor some defines out of corenet_ds.h fm-eth: Add ability for board code to disable a port powerpc/mpc8548: Add workaround for erratum NMG_LBC103 powerpc/mpc8548: Add workaround for erratum NMG_DDR120 powerpc/mpc85xxcds: Fix PCI speed powerpc/mpc8548cds: Fix booting message powerpc/p4080: Add support for secure boot flow powerpc/85xx: Add Secure Boot support on P1010RDB for NOR, NAND & SPIFLASH powerpc/85xx: Add PBL & SECUREBOOT support on P3041/P5020DS boards powerpc/p2041rdb: remove watch dog related codes powerpc/p2041rdb: updated description of cpld command powerpc/p2041rdb: add more ddr frequencies support powerpc/p2041rdb: set sysclk according to status of physical switch SW1 powerpc/p2041rdb: update cpld reset command according to CPLD 2.0 powerpc/mpc8349emds: Migrate from spd_sdram to unified DDR driver powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver powerpc/mpc8xxx: Add DDR2 to unified DDR driver powerpc/mpc8xxx: Fix picos_to_mclk() and get_memory_clk_period_ps() powerpc/mpc8xxx: Add SPD EEPROM address for single controller 2 slots powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_en powerpc/85xx: Refactor P2041RDB to use common p_corenet files powerpc/85xx: refactor common P-Series CoreNet files for FSL boards powerpc/85xx: Enable CMD_REGINFO on corenet boards powerpc/85xx: p2041rdb - Remove unused 'execute' perm in TLB entries powerpc/85xx: Fix USB protocol definitions for P1020RDB powerpc/corenet_ds: Use separated speed tables for UDIMM and RDIMM powerpc/mpc8xxx: Move DDR RCW overriding to common code powerpc/mpc8xxx: Extend CWL table powerpc/85xx: Cleanup how SVR_MAJ() is defined on MPC8536 powerpc/85xx: Cleanup extern in corenet_ds board code powerpc/p2041rdb: Add ethernet support on P2041RDB board powerpc/85xx: Add networking support to P1023RDS powerpc/hydra: Add ethernet support on P5020/P3041 DS boards powerpc/85xx: Add FMan ethernet support to P4080DS powerpc/85xx: Add support for FMan ethernet in Independent mode powerpc/mpc8548cds: Cleanup mpc8548cds.c powerpc/mp: add support for discontiguous cores powerpc/85xx: corenet_ds - Remove unused 'execute' perm in TLB entries fdt: Add new fdt_create_phandle helper fdt: Rename fdt_create_phandle to fdt_set_phandle powerpc/85xx: Fix compile warnings/errors if CONFIG_SYS_DPAA_FMAN isn't set fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010) powerpc/P1010: Add workaround for erratum P1010-A003549 (related to IFC) fsl_ifc: Add the workaround for erratum IFC-A002769 (enable on P1010) powerpc/85xx: Expanding the window of CCSRBAR in AS=1 from 4k to 1M powerpc/85xx: Add NAND/NAND_SPL support to P1010RDB nand: Freescale Integrated Flash Controller NAND support powerpc/85xx: Add basic support for P1010RDB powerpc/85xx: Add support for new P102x/P2020 RDB style boards powerpc/85xx: relocate CCSR before creating the initial RAM area powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macros powerpc/85xx: Enable internal USB UTMI PHY on p204x/p3041/p50x0 powerpc/85xx: Add ULPI and UTMI USB Phy support for P1010/P1014
| * | powerpc/p3060: Add SoC related support for P3060 platformShengzhou Liu2011-10-03-0/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add P3060 SoC specific information:cores setup, LIODN setup, etc The P3060 SoC combines six e500mc Power Architecture processor cores with high-performance datapath acceleration architecture(DPAA), CoreNet fabric infrastructure, as well as network and peripheral interfaces. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | fm-eth: Add ability for board code to disable a portKumar Gala2011-10-03-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SoC configuration may have more ports enabled than a given board actually can utilize. Add a routinue that allows the board code to disable a port that it knows isn't being used. fm_disable_port() needs to be called before cpu_eth_init(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Add support for FMan ethernet in Independent modeKumar Gala2011-09-29-0/+2212
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Frame Manager (FMan) on QorIQ SoCs with DPAA (datapath acceleration architecture) is the ethernet contoller block. Normally it is utilized via Queue Manager (Qman) and Buffer Manager (Bman). However for boot usage the FMan supports a mode similar to QE or CPM ethernet collers called Independent mode. Additionally the FMan block supports multiple 1g and 10g interfaces as a single entity in the system rather than each controller being managed uniquely. This means we have to initialize all of Fman regardless of the number of interfaces we utilize. Different SoCs support different combinations of the number of FMan as well as the number of 1g & 10g interfaces support per Fman. We add support for the following SoCs: * P1023 - 1 Fman, 2x1g * P4080 - 2 Fman, each Fman has 4x1g and 1x10g * P204x/P3041/P5020 - 1 Fman, 5x1g, 1x10g Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Dai Haruki <dai.haruki@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | nand: Freescale Integrated Flash Controller NAND supportDipen Dudhat2011-09-29-0/+851
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add NAND support (including spl) on IFC, such as is found on the p1010. Note that using hardware ECC on IFC with small-page NAND (which is what comes on the p1010rdb reference board) means there will be insufficient OOB space for JFFS2, since IFC does not support 1-bit ECC. UBI should work, as it does not use OOB for anything but ECC. When hardware ECC is not enabled in CSOR, software ECC is now used. Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> [scottwood@freescale.com: ECC rework and misc fixes] Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | powerpc/85xx: Add ULPI and UTMI USB Phy support for P1010/P1014Ramneek Mehresh2011-09-29-3/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add UTMI and ULPI PHY support for USB controller on qoriq series of processors with internal UTMI PHY implemented, for example P1010/P1014 - Use both getenv() and hwconfig to get USB phy type till getenv() is depricated - Introduce CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY to specify if soc has internal UTMI phy Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Acked-by: Remy Bohmer <linux@bohmer.net> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-i2cWolfgang Denk2011-10-04-19/+25
|\ \ \ | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-i2c: I2C: mv_i2c: fix multi-bus init issue I2C: mv_i2c: fix build issue when enable debug option
| * | | I2C: mv_i2c: fix multi-bus init issueLei Wen2011-10-03-18/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When enable the multi-bus, the current_bus is not inited in the original implementation, which make the i2c operation unpredicatable. Signed-off-by: Lei Wen <leiwen@marvell.com>
| * | | I2C: mv_i2c: fix build issue when enable debug optionLei Wen2011-10-03-1/+1
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | When DEBUG_I2C is open, the following build issue would shows up. mv_i2c.c: In function 'i2c_transfer': mv_i2c.c:257: error: 'ISR' undeclared (first use in this function) mv_i2c.c:257: error: (Each undeclared identifier is reported only once mv_i2c.c:257: error: for each function it appears in.) Signed-off-by: Lei Wen <leiwen@marvell.com>
* | | net: emaclite: Use dynamic allocationMichal Simek2011-10-03-16/+25
| | | | | | | | | | | | | | | | | | | | | Every emaclite instance use own setting. Signed-off-by: Michal Simek <monstr@monstr.eu> Acked-by: Mike Frysinger <vapier@gentoo.org>
* | | net: emaclite: Remove baseaddress from xemacliteMichal Simek2011-10-03-21/+21
| | | | | | | | | | | | | | | | | | Use dev->iobase instead of baseaddress. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | net: emaclite: Use calloc instead of mallocMichal Simek2011-10-03-2/+1
| | | | | | | | | | | | | | | | | | | | | Simplify driver logic and clear eth_device structure in one command. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | net: emaclite: Remove deviceid propertyMichal Simek2011-10-03-1/+0
| | | | | | | | | | | | | | | | | | Cleanup structure. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | net: emaclite: Change driver name and add addressMichal Simek2011-10-03-1/+1
|/ / | | | | | | | | | | | | | | | | Current xilinx emaclite use net multi registration but doesn't support several emaclites interfaces. Changing driver name with adding address to name is the first step how to distiguish several drivers. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | GCC4.6: Squash warning in vmt.cMarek Vasut2011-10-01-4/+7
| | | | | | | | | | | | | | | | | | vmt.c: In function ‘ubi_free_volume’: vmt.c:681:6: warning: variable ‘err’ set but not used [-Wunused-but-set-variable] Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
* | GCC4.6: Squash warning in nand_bbt.cMarek Vasut2011-10-01-4/+1
| | | | | | | | | | | | | | | | | | nand_bbt.c: In function ‘search_bbt’: nand_bbt.c:465:6: warning: variable ‘bits’ set but not used [-Wunused-but-set-variable] Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Scott Wood <scottwood@freescale.com>
* | GCC4.6: Squash warnings in ipu_disp.cMarek Vasut2011-10-01-57/+48
| | | | | | | | | | | | | | | | | | | | | | | | ipu_disp.c: In function ‘ipu_disp_set_global_alpha’: ipu_disp.c:1237:11: warning: variable ‘flow’ set but not used [-Wunused-but-set-variable] ipu_disp.c: In function ‘ipu_disp_set_color_key’: ipu_disp.c:1302:16: warning: variable ‘flow’ set but not used [-Wunused-but-set-variable] Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
* | console: Squelch pre-console output in console functionsGraeme Russ2011-10-01-5/+1
| | | | | | | | | | | | | | | | | | | | There are some locations in the code which anticipate printf() being called before the console is ready by squelching printf() on gd->have_console. Move this squelching into printf(), vprintf(), puts() and putc(). Also make tstc() and getc() return 0 if console is not yet initialised Signed-off-by: Graeme Russ <graeme.russ@gmail.com> Tested-by: Simon Glass <sjg@chromium.org>
* | ns16550: change to allow 32 bit access to registersDave Aldridge2011-10-01-0/+6
| | | | | | | | | | | | | | | | | | | | If CONFIG_SYS_NS16550_MEM32 is defined then 32 bit memory mapped access will be used to read/write the uart registers. This is especially useful for SoC devices that implement 16550 compatible uarts but that have peripheral access width constraints. Signed-off-by: Dave Aldridge <fovsoft@gmail.com>
* | Merge branch 'sf' of git://git.denx.de/u-boot-blackfinWolfgang Denk2011-10-01-0/+8
|\ \ | | | | | | | | | | | | | | | * 'sf' of git://git.denx.de/u-boot-blackfin: sf: eon: add support for EN25Q32B parts cmd_sf: add "update" subcommand to do smart SPI flash update
| * | sf: eon: add support for EN25Q32B partsShaohui Xie2011-09-29-0/+8
| |/ | | | | | | | | Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | ATA: Squash warnings in mxc_ata.Marek Vasut2011-09-30-13/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | mxc_ata.c: In function ‘set_ata_bus_timing’: mxc_ata.c:118: warning: dereferencing type-punned pointer will break strict-aliasing rules mxc_ata.c:125: warning: dereferencing type-punned pointer will break strict-aliasing rules mxc_ata.c:129: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
* | I2C: mxc_i2c reworkMarek Vasut2011-09-30-133/+289
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rewrite the mxc_i2c driver. * This version is much closer to Linux implementation. * Fixes IPG_PERCLK being incorrectly used as clock source * Fixes behaviour of the driver on iMX51 * Clean up coding style a bit ;-) Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Jason Hui <jason.hui@linaro.org> Acked-by: Jason Liu <jason.hui@linro.org> Acked-by: Heiko Schocher <hs@denx.de> Tested-by: Jason Liu <jason.hui@linro.org>
* | FEC: Move imx_get_mac_from_fuse() definition to fec_mxc.hMarek Vasut2011-09-30-0/+2
| | | | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Ben Warren <biggerbadderben@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
* | FEC: Squish "got MAC from fuse" message, make it debug()Marek Vasut2011-09-30-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Ben Warren <biggerbadderben@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
* | FEC: Add timeout for chip resetMarek Vasut2011-09-30-4/+21
| | | | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Ben Warren <biggerbadderben@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
* | FEC: Allow registering MII postconfiguration callbackMarek Vasut2011-09-30-1/+14
| | | | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Ben Warren <biggerbadderben@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
* | FEC: Allow multiple FECesMarek Vasut2011-09-30-30/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows user to register multiple FEC controllers. To preserve compatibility with older boards, the mxcfec_register() call is still in place. To use multiple controllers, new macro is in place, the mxcfec_register_multi(), which takes more arguments. The syntax is: mxcfec_register_multi(bd, FEC ID, FEC PHY ID on the MII bus, base address); To disable the fecmxc_register() compatibility stuff, define the macro CONFIG_FEC_MXC_MULTI. This will remove the requirement for defining IMX_FEC_BASE and CONFIG_FEC_MXC_PHYADDR. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Ben Warren <biggerbadderben@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
* | FEC: Abstract access to fec->eth in MII operationsMarek Vasut2011-09-30-8/+10
| | | | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Ben Warren <biggerbadderben@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
* | FEC: Allow selection of MII mode via CONFIG_FEC_XCV_TYPEMarek Vasut2011-09-30-1/+5
| | | | | | | | | | | | | | | | | | | | The default is MII100, which was hardcoded previously in the driver. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Ben Warren <biggerbadderben@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
* | FEC: Add RMII mode supportMarek Vasut2011-09-30-1/+5
| | | | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Ben Warren <biggerbadderben@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
* | FEC: Kill mode select FIXME'sMarek Vasut2011-09-30-12/+14
| | | | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Ben Warren <biggerbadderben@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
* | FEC: Use defined constant instead of magic numberMarek Vasut2011-09-30-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Ben Warren <biggerbadderben@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
* | FEC: Use proper accessor to read register in debug callMarek Vasut2011-09-30-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Ben Warren <biggerbadderben@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
* | cosmetic: fsl_pmic: cosmetic for the help messageJason Liu2011-09-30-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This is cosmetic patch for the help message: Before: pmic dump [numregs] dump registers After: pmic dump [numregs] - dump registers Signed-off-by: Jason Liu <jason.hui@linaro.org> Acked-by: Stefano Babic <sbabic@denx.de>
* | rtc, davinci: add support for davinci internal RTCHeiko Schocher2011-09-30-0/+126
| | | | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | net, davinci_emac: let the EMAC detect the PHYsHeiko Schocher2011-09-30-0/+3
| | | | | | | | | | | | | | | | | | | | | | Once the MDIO state machine has been initialized and enabled, it starts polling all 32 PHY addresses on the MDIO bus, looking for an active PHY. Add a 5 ms delay, so all PHYs are for sure detected. This problem was detected on the cmc board with a KSZ8864 switch. Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | net, davinci_emac: make less verbose - turn printf() into debug()Heiko Schocher2011-09-30-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PHY driver was too verbose and corrupted the boot message display like this: ... Net: Ethernet PHY: KSZ8873 @ 0x02 DaVinci-EMAC ... Turn printf() into debug() so we get the expected output again: ... Net: DaVinci-EMAC ... Signed-off-by: Heiko Schocher <hs@denx.de> cc: Paulraj Sandeep <s-paulraj@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | net, davinci_emac: add KSZ8864 switchHeiko Schocher2011-09-30-0/+7
| | | | | | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | i2c, davinci: add i2c set speedHeiko Schocher2011-09-30-0/+5
| | | | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | mmc: omap: config VMMC, MMC1_PBIASBalaji T K2011-09-30-3/+35
| | | | | | | | | | | | | | | | | | | | Config VMMC voltage to 3V for MMC/SD card slot and PBIAS settings needed for OMAP4 Fixes MMC/SD detection on boot from eMMC. Signed-off-by: Balaji T K <balajitk@ti.com> Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | mmc: omap: enable high capacityBalaji T K2011-09-30-1/+2
| | | | | | | | | | | | | | | | | | | | Enable high capacity to host capability. Fixes eMMC detection on boot from MMC/SD card. Signed-off-by: Balaji T K <balajitk@ti.com> Signed-off-by: Aneesh V <aneesh@ti.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
generated by cgit v1.1 at 2024-11-14 07:19:17 +0000