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* usb: Make pollable int support available outside of ehci-hcd.cHans de Goede2014-11-04-1/+1
| | | | Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* usb: ehci: Move cache invalidation to poll_int_queueHans de Goede2014-11-04-3/+7
| | | | | | Preperation patch to use poll_int_queue outside of ehci-hcd.c . Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* usb: ehci: Move interrupt packet length check to create_int_queueHans de Goede2014-11-04-17/+19
| | | | | | Preperation patch to use create_int_queue outside of ehci-hcd.c . Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* usb: ehci: Do not disable an already disabled periodic scheduleHans de Goede2014-11-04-3/+5
| | | | | | | When periodic_schedules == 0, the schedule is disabled and there is no reason to disable it again. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2014-11-03-3/+14
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| * serial: UniPhier: add static to locally used functionsMasahiro Yamada2014-10-29-3/+3
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * serial: UniPhier: add .pending handlerMasahiro Yamada2014-10-29-0/+11
| | | | | | | | | | | | Without .pending handler, tstc() function always returns 1. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2014-11-03-77/+95
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| * | SPI: mxc_spi: delay initialisation until claim busMarkus Niebel2014-10-27-16/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | it is not correct to init for a specific slave in spi_setup_slave. instead buffer the values and delay init until spi_claim_bus. Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com> Acked-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | SPI: mxc_spi: remove second reset from ECSPI config handlerMarkus Niebel2014-10-27-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the second reset prevents other registers to be written. This will prevent to have the correct signal levels for SCLK before writing to the config reg in spi_xchg_single. Tested with GPIO based chipselect and SPI_MODE_3 on i.MX6S Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com> Acked-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | spi: altera: Move the config options to the topMarek Vasut2014-10-27-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Just move the configuration options scattered all over the driver to the top of the source file. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | spi: altera: Clean up the use of variable dMarek Vasut2014-10-27-10/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The variable d is used in rather questionable way. Rework the code a bit so it's clearer what it does. Also, rename the variable from d to data to make it's name less mysterious. Finally, change it's data type to uint32_t , since it's accessed as a 32bit number. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | spi: altera: Zap endless loopMarek Vasut2014-10-27-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver contained an endless loop when waiting for TX completion, this is a bad idea since if the hardware fails, the loop might spin forever. Add timeout and handle it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | spi: altera: Clean up most checkpatch issuesMarek Vasut2014-10-27-10/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch just zaps most of the checkpatch cries present in the driver. There is one more left, which will be addressed separately. There is no functional change. This patch also adds a bunch of newlines all around the place, this is to make the code much more readable. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | spi: altera: Clean up bit definitionsMarek Vasut2014-10-27-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clean up the definitions of bits in the Altera SPI driver, there is no need to put braces around numbers afterall. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | spi: altera: Use struct-based register accessMarek Vasut2014-10-27-24/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Zap the offset-based register access and use the struct-based one as this is the preferred method. No functional change, but there are some line-over-80 problems in the driver, which will be addressed later. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | | i2c: designware: Convert driver to multibus/multiadapter frameworkStefan Roese2014-10-29-167/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation for the SoCFPGA support of the designware I2C driver, convert this driver to the common CONFIG_SYS_I2C framework. This patch converts all users of this driver, this is: - ST spearxxx boards - AXS101 (ARC700 platform) I couldn't test this patch on those boards. Only compile tested for all spear boards. And tested on SoCFPGA. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Tested-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Heiko Schocher <hs@denx.de> Cc: Vipin Kumar <vk.vipin@gmail.com> Cc: Jeroen Hofstee <jeroen@myspectrum.nl>
* | | i2c: mxs: Add support for I2C 1 on i.MX28Marek Vasut2014-10-29-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | Add support for I2C bus 1 on the i.MX28. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Heiko Schocher <hs@denx.de>
* | | i2c: mxs: Pass the i2c_adapter aroundMarek Vasut2014-10-29-67/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch permeates the struct i2c_adapter throughout the driver, so that it can be used to determine which adapter should be used. Note that the driver still supports only one adapter. Note that the patch does shuffle mxs_i2c_set_bus_speed() to the top of the driver, but the function remains unchanged. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Heiko Schocher <hs@denx.de>
* | | i2c: mxs: Add basic support for i2c frameworkMarek Vasut2014-10-29-21/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch just converts the function prototypes used throughout this driver to match those of the i2c framework. There is so far no functional change. This patch does not do the deeper integration of the framework bits. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Heiko Schocher <hs@denx.de>
* | | i2c: mxs: Consolidate hard-coded bus addressMarek Vasut2014-10-29-7/+12
| |/ |/| | | | | | | | | | | | | | | | | This patch prepares the MXS I2C driver for the conversion to the new I2C driver framework by pulling out the hard-coded I2C0 address from all the places. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Heiko Schocher <hs@denx.de>
* | dwc_ahsata: use bitwise operator in sata_port_statusNikita Kiryanov2014-10-28-1/+1
| | | | | | | | | | | | | | | | | | | | The logic of the return statement in sata_port_status() calls for a bitwise 'AND' operator, not logical 'AND'. Fix the typo. Reported-by: Jeroen Hofstee <jeroen@myspectrum.nl> Cc: Jeroen Hofstee <jeroen@myspectrum.nl> Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* | Merge git://git.denx.de/u-boot-dmTom Rini2014-10-28-1/+1
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| * | mmc: s5p: set SD detection pin as inputPrzemyslaw Marczak2014-10-27-1/+1
| | | | | | | | | | | | | | | | | | | | | The SD Card slot detection pin should be configured as input. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | e1000: add i211 and unprogrammed i210/i211 supportMarcel Ziswiler2014-10-28-0/+6
|/ / | | | | | | | | | | | | This patch adds support for i211 as well as unprogrammed aka tools only i210/i211 chip support. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
* | e1000: fix sw fw sync on igb i210/i211Marcel Ziswiler2014-10-27-2/+5
| | | | | | | | | | | | | | | | | | I finally had a look at the datasheet and spotted an additional register address difference between regular E1000 and i210/i211 chips. This patch fixes this and now successfully works on programmed i210/i211 as well as unprogrammed i211. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
* | net/e1000: Fix EEPROM access errorYork Sun2014-10-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Commit 951860634fdb557bbb58e0f99215391bc0c29779 may have changed the logic unintentially from "if (!(swfw_sync & (fwmask | swmask)))" to "if ((swfw_sync & swmask) && !(swfw_sync & fwmask))". This change breaks some e1000 NIC with a message "ERROR: Unable to read EEPROM!". Signed-off-by: York Sun <yorksun@freescale.com> CC: Marek Vasut <marex@denx.de> CC: Tim Harvey <tharvey@gateworks.com> Acked-by: Marcel Ziswiler <marcel@ziswiler.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxxTom Rini2014-10-27-1/+1
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| * PowerPC: drop some 74xx_7xx boards and related codeWolfgang Denk2014-10-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The file board/Marvell/include/mv_gen_reg.h is incompatible with the GPL (see for example the "MARVELL RESERVES THE RIGHT AT ITS SOLE DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL" clause). As this cannot be fixed, we remove the file and all code that depends on it. Fortunately this only affects some very old boards that have long reached EOL: CPCI750 DB64360 DB64460 p3m750 p3m7448 Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com> Cc: Stefan Roese <sr@denx.de> Cc: Roger Meier <r.meier@siemens.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-imxTom Rini2014-10-27-0/+1
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| * | ARM: i.MX: provide declaration for board_spi_cs_gpioEric Nelson2014-10-21-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Provide a public declaration of the board_spi_cs_gpio() callback for i.MX SPI chip selects to prevent the warning "Should it be static?" when compiling with "make C=1". Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-tiTom Rini2014-10-27-268/+1443
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| * | dma: ti-edma3: introduce edma3 driverKhoronzhuk, Ivan2014-10-23-0/+385
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The EDMA3 controller’s primary purpose is to service data transfers that you program between two memory-mapped slave endpoints on the device. Typical usage includes, but is not limited to the following: - Servicing software-driven paging transfers (e.g., transfers from external memory, such as SDRAM to internal device memory, such as DSP L2 SRAM) - Servicing event-driven peripherals, such as a serial port - Performing sorting or sub-frame extraction of various data structures - Offloading data transfers from the main device DSP(s) - See the device-specific data manual for specific peripherals that are accessible via the EDMA3 controller Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | net: keystone_net: increase PHY auto negotiate timeKhoronzhuk, Ivan2014-10-23-5/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new Marvel PHY (88E1514) used on K2L/K2E EVM requires longer time to auto negotiate with SoC's SGMII port. It can take about 3 sec to up the PHY after reset, so add code to expose sgmii auto negotiation waiting process. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | net: keystone_net: add Keystone2 K2E SoC supportKhoronzhuk, Ivan2014-10-23-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | The Keystone2 Edison SoC uses the same keystone net driver. This patch adds opportunity to use it by K2E SoCs. Acked-by: Vitaly Andrianov <vitalya@ti.com> Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | net: keystone_serdes: add keystone K2E SoC supportKhoronzhuk, Ivan2014-10-23-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Keystone2 Edison SoC uses the same keystone SerDes driver. This patch adds support for K2E SoCs. Acked-by: Vitaly Andrianov <vitalya@ti.com> Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | net: keystone_net: use general get link functionKhoronzhuk, Ivan2014-10-23-45/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The phy framework has function to get link, so use it instead of own implementation. There is no reason to check SGMII link while sending each packet, phy link is enough. Check SGMII link only while ethernet open. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | net: keystone_net: register eth PHYs on MDIO busKhoronzhuk, Ivan2014-10-23-3/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As MDIO bus has been added we can register PHYs with it. After registration, the PHY driver will be probed according to the hardware on board. Startup PHY at the ethernet open. Use phy_startup() instead of keystone_get_link_status() when eth open, as it verifies PHY link inside and SGMII link is checked before. For K2HK evm PHY configuration at init was absent, so don't enable phy config at init for k2hk evm. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | net: keystone_net: register MDIO busKhoronzhuk, Ivan2014-10-23-38/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently MDIO framework is not used to configure Ethernet PHY. As result some of already implemented functions are duplicated. So register MDIO bus in order to use it. On that stage it's just registered, it'll be used as we start to use PHY framework. Use mdio bus read/write/reset functions in the driver. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | net: keystone_net: use mdio_reset functionKhoronzhuk, Ivan2014-10-23-14/+2
| | | | | | | | | | | | | | | | | | | | | | | | Don't use mdio_enable twice while eth open. Also rename it to keystone2_mdio_reset as more appropriate name. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | net: phy: print a number of phy that is not foundKhoronzhuk, Ivan2014-10-23-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | In case when several Ethernet ports are supported it's convenient to see the number of phy that is not found. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | soc: keystone_serdes: generalize configuration mechanismKhoronzhuk, Ivan2014-10-23-47/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The cmu, comlane, lane configuration mechanism are similar for sub systems as well such as PCI or sRIO, but they have different values based on input clock and output bus rate. According to this compact driver to simplify adding different configuration settings based on clock and rate. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | soc: keystone_serdes: generalize to be used by other sub systemsHao Zhang2014-10-23-35/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SerDes driver is used by other sub systems like PCI, sRIO etc. So modify it to be more general. The SerDes driver provides common API's that can also be extended for other peripherals SerDes configurations. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | soc: keystone_serdes: enhance to use cmu/comlane/lane specific configurationsHao Zhang2014-10-23-82/+84
| | | | | | | | | | | | | | | | | | | | | | | | Enhance the driver to use cmu/comlane/lane specific configurations instead of 1 big array of configuration. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | soc: keystone_serdes: create a separate SGMII SerDes driverKhoronzhuk, Ivan2014-10-23-138/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch split the Keystone II SGMII SerDes related code from Ethernet driver and create a separate SGMII SerDes driver. The SerDes driver can be used by others keystone subsystems like PCI, sRIO, so move it to driver/soc/keystone directory. Add soc specific drivers directory like in the Linux kernel. It is going to be used by keysotone soc specific drivers. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | net: keystone_net: remove redundant code from keystone_net.cKhoronzhuk, Ivan2014-10-23-17/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove unused tx_send_loop variable. Removes duplicated get_link_status() call from the keystone2_eth_send_packet(). The emac_gigabit_enable() is called at opening Ethernet and there is no need to enable it on sending each packet. So remove that call from keystone2_eth_send_packet() as well. The calling of power/clock up functions are mostly the responsibility of SoC/board code, so move these functions to appropriate place. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | net: keystone_net: move header file from arch to ti-commonKhoronzhuk, Ivan2014-10-23-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The header file for the driver should be in correct place. So move it to "arch/arm/include/asm/ti-common/keystone_net.h" and correct driver's external dependencies. At the same time align and correct some definitions. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | net: keystone_net: remove SoC specific emac_regs structureHao Zhang2014-10-23-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes K2HK SOC specifc emac_regs structure, it uses soc specific register offset to keep the network driver common across all the Keystone II EVMs. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | keystone: usb: add support of usb xhciWingMan Kwok2014-10-23-0/+330
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support of usb xhci. xHCI controls all USB speeds of the Host mode, that is, the SS through the SS PHY, as well as the HS, FS, and LS through the USB2 PHY. xHCI replaces and supersedes all previous host HCIs (HS-only EHCI, FS/LS OHCI and UHCI), and is therefore not backwards compatible with any of them. The USB3SS’s USB Controller is fully compliant with xHC. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: WingMan Kwok <w-kwok2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | dma: keystone_nav: generalize driver usageKhoronzhuk, Ivan2014-10-23-84/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The keystone_nav driver is general driver intended to be used for working with queue manager and pktdma for different IPs like NETCP, AIF, FFTC, etc. So the it's API shouldn't be named like it works only with one of them, it should be general names. The names with prefix like netcp_* rather do for drivers/net/keystone_net.c driver. So it's good to generalize this driver to be used for different IP's and delete confusion with real NETCP driver. The current netcp_* functions of keystone navigator can be used for other settings of pktdma, not only for NETCP. The API of this driver is used by the keystone_net driver to work with NETCP, so net driver also should be corrected. For convenience collect pkdma configurations in drivers/dma/keystone_nav_cfg.c. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
generated by cgit v1.1 at 2024-11-14 11:09:18 +0000