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* mpc8xx: remove RRvision board supportMasahiro Yamada2015-01-05-17/+0
| | | | | | | | | | | This board is still a non-generic board. Unused code in arch/powerpc/cpu/mpc8xx/video.c should be also deleted because CONFIG_VIDEO_ENCODER_AD7176, CONFIG_VIDEO_ENCODER_AD7177, CONFIG_VIDEO_ENCODER_AD7179 are not defined any more. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de>
* powerpc: manroland: remove uc100, uc101, mucmc52, hmi1001 supportMasahiro Yamada2015-01-05-8/+0
| | | | | | | | These boards are still non-generic boards. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Heiko Schocher <hs@denx.de> Cc: Stefan Roese <sr@denx.de>
* mpc8xx: remove FPS{850, 860}L, NSCU, SM850, TK885D, virtlab2 supportMasahiro Yamada2015-01-05-51/+2
| | | | | | | These boards are still non-generic boards. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-01-02-446/+99
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| * imx:qspi add 4K erase supportPeng Fan2014-12-31-5/+19
| | | | | | | | | | | | | | | | | | Add 4k erase command support for qspi driver. reuse the 64k erase function, but change the function name from qspi_op_se to qspi_op_erase, since it supports 64k and 4k erase. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * arm:mx6sx add QSPI supportPeng Fan2014-12-31-0/+19
| | | | | | | | | | | | | | Add QSPI support for mx6solox. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * QuadSPI: use correct amba_basePeng Fan2014-12-31-5/+25
| | | | | | | | | | | | | | | | | | According cs, use different amba_base to choose the corresponding flash devices. If not, `sf probe 1:0` and `sf probe 1:1` will choose the same flash device, but not different flash devices. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * QuadSPI: use QSPI_CMD_xx instead of flash opcodesPeng Fan2014-12-31-31/+33
| | | | | | | | | | | | | | Use QSPI_CMD_xx instead of flash opcodes Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * sf: sf_params: Add S25FL164K flash identifier infoAdnan Ali2014-12-18-0/+1
| | | | | | | | | | | | | | | | Add the necessary flash entry for the Spansion S25FL164K flash. Tested on Marvell 88F6218 based design. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * sf: sf_params: Add S25FL116K flash supportAdnan Ali2014-12-18-0/+1
| | | | | | | | | | | | | | Added S25FL116K flash and tested on Marvell 88F6281 based system. Signed-off-by: Adnan Ali <adnan.ali@codethink.co.uk> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * mtd/spi: Add support for SST25WF040BShengzhou Liu2014-12-18-0/+1
| | | | | | | | | | | | | | | | Add support for SST25WF040B-40I-SN flash. Tested on T1024QDS board. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * mtd: sf: Zap ramtron driverJagannadha Sutradharudu Teki2014-12-18-405/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | Removed ramtron driver since the EMK boards are no longer been active, and these are the only boards used this flash driver. Commit details for EMK zap: "ppc/arm: zap EMK boards" (sha1: d58a9451e7339ed4cf2b2627e534611f427fb791) Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Cc: Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-01-01-34/+1502
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| * | net: rtl8169: Add support for RTL-8168/8111gThierry Reding2014-12-18-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This network interface card is found on the NVIDIA Jetson TK1. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | net: rtl8169: Use non-cached memory if availableThierry Reding2014-12-18-11/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To work around potential issues with explicit cache maintenance of the RX and TX descriptor rings, allocate them from a pool of uncached memory if the architecture supports it. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | net: rtl8169: Properly align buffersThierry Reding2014-12-18-29/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RX and TX descriptor rings should be aligned to 256 byte boundaries. Use the DEFINE_ALIGN_BUFFER() macro to define the buffers so that they don't have to be manually aligned later on. Also make sure that the buffers do align to cache-line boundaries in case the cache-line is higher than the 256 byte alignment requirements of the NIC. Also add a warning if the cache-line size is larger than the descriptor size, because the driver may discard changes to descriptors made by the hardware when requeuing RX buffers. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | net: rtl8169: Honor CONFIG_SYS_RX_ETH_BUFFERThierry Reding2014-12-18-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the top-level README file, this configuration setting can be used to override the number of receive buffers that an ethernet NIC uses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | pci: tegra: Add Tegra PCIe driverThierry Reding2014-12-18-0/+1144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the PCIe controller found on some generations of Tegra. Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has 3 root ports with a total of 6 lanes and Tegra124 has 2 root ports with a total of 5 lanes. This is based on the Linux kernel driver, originally submitted upstream by Mike Rapoport. Signed-off-by: Mike Rapoport <mike@compulab.co.il> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | power: Add AMS AS3722 PMIC supportThierry Reding2014-12-18-0/+265
| |/ | | | | | | | | | | | | | | | | The AS3722 provides a number of DC/DC converters and LDOs as well as 8 GPIOs. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | usb: eth: add ASIX AX88179 DRIVERRene Griessl2014-12-31-0/+708
| | | | | | | | | | | | | | | | | | | | This patch adds driver support for the ASIX AX88179 USB3.0 to GbE network adapter. Driver has been tested on the RECS5250 COM module (similar to ARDALE5250). Testcase was DHCP and PXE boot. Signed-off-by: Rene Griessl <rgriessl@cit-ec.uni-bielefeld.de>
* | Merge git://git.denx.de/u-boot-x86Tom Rini2014-12-19-15/+19
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| * | x86: Rename coreboot-serial to x86-serialBin Meng2014-12-18-7/+7
| | | | | | | | | | | | | | | Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | x86: ich6-gpio: Add Intel Tunnel Creek GPIO supportBin Meng2014-12-18-8/+12
| |/ | | | | | | | | | | | | | | | | | | | | | | Intel Tunnel Creek GPIO register block is compatible with current ich6-gpio driver, except the offset and content of GPIO block base address register in the LPC PCI configuration space are different. Use u16 instead of u32 to store the 16-bit I/O address of the GPIO registers so that it could support both Ivybridge and Tunnel Creek. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2014-12-18-23/+59
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| * dfu: dfu_get_buf: check the value of env dfu_bufsiz before usePrzemyslaw Marczak2014-12-18-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In function dfu_get_buf(), the size of allocated buffer could be defined by the env variable. The size from this variable was passed for memalign() without checking its value. And the the memalign will return non null pointer for size 0. This could possibly cause data abort, so now the value of var is checked before use. And if this variable is set to 0 then the default size will be used. This commit also changes the base passed to simple_strtoul() to 0. Now decimal and hex values can be used for the variable dfu_bufsiz. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [TestHW: Exynos4412-Trats2]
| * gadget: f_thor: check pointers before use in download_tail()Przemyslaw Marczak2014-12-18-2/+14
| | | | | | | | | | | | | | | | | | | | Some pointers in function download_tail() were not checked before the use. This could possibly cause the data abort. To avoid this, check if the pointers are not null is added. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [TestHW: Exynos4412-Trats2]
| * dfu: mmc: check if mmc device exists in mmc_block_op()Przemyslaw Marczak2014-12-18-1/+7
| | | | | | | | | | | | | | | | | | | | | | The function mmc_block_op() is the last function before the physicall data write, but the mmc device pointer is not checked. If mmc device not exists, then data abort will occur. To avoid this, first the mmc device pointer is checked. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [TestHW: Exynos4412-Trats2]
| * fastboot: add support for continue commandRob Herring2014-12-18-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | The fastboot continue command is defined to exit fastboot and continue autoboot. This commit implements the continue command and the exiting of fastboot only. Subsequent u-boot commands can be processed after exiting fastboot. Autoboot should implement a boot script such as "fastboot; mmc read <...>; bootm" to fully implement the fastboot continue function. Signed-off-by: Rob Herring <robh@kernel.org> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [TestHW: Exynos4412-Trats2]
| * usb, g_dnl: generalize DFU detach functionsRob Herring2014-12-18-17/+18
| | | | | | | | | | | | | | | | | | In order to add detach functions for fastboot, make the DFU detach related functions common so they can be shared. Signed-off-by: Rob Herring <robh@kernel.org> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [TestHW: Exynos4412-Trats2]
| * USB: gadget: atmel_usba_udc: fix transfer hang issueBo Shen2014-12-16-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | When receive data, the RXRDY in status register set by hardware after a new packet has been stored in the endpoint FIFO. After, we copy from FIFO, we clear it, make the FIFO can be accessed again. In the receive_data() function, this bit RXRDY has been cleared. So, after the receive_data() function return, this bit should not be cleared again, or else it will cause the accessing FIFO corrupt, which will make the data loss. Signed-off-by: Bo Shen <voice.shen@atmel.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-12-16-7/+48
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| * | qe/deep-sleep: modify qe deep-sleep for generic boardZhao Qiang2014-12-15-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | Deep sleep for generic board is supported now, modify qe deep-sleep code to adapt it. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | crypto/fsl: Fix RNG instantiation failure.gaurav rana2014-12-15-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Corrected the order of arguments in memset in run_descriptor function. Wrong order of argumnets led to improper initialization of members of struct type result. This resulted in RNG instantiation error. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | net/fm: update ft_fixup_port to differentiate dual-role macShengzhou Liu2014-12-15-5/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | we need to differentiate dual-role MACs into two types: MACs with 10GEC enumeration consistent with DTSEC enumeration(defined by CONFIG_FSL_FM_10GEC_REGULAR_NOTATION) and other MACs without CONFIG_FSL_FM_10GEC_REGULAR_NOTATION defined. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | driver/ddr/fsl: Fix MRC_CYC calculation for DDR3York Sun2014-12-15-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For DDR controller version 4.7 or newer, MRC_CYC (mode register set cycle time) is max(tMRD, tMOD). tMRD is 4nCK, or 8nCK (RDIMM). tMOD is max(12nCK, 15ns) according to JEDEC spec. DDR4 is not affected by this change. Signed-off-by: York Sun <yorksun@freescale.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2014-12-16-0/+1747
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| * | spi: designware_spi: Some fixes / changesStefan Roese2014-12-06-19/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As suggested by Pavel, here some fixes to the designware SPI driver: - Spelling fixes - Comment for timeout added - Removed n_bytes completely (bits_per_word is enough for this) - Unput clock now not defined via macro. The function to get the clock value is now called directly from within the driver Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | spi: Add designware master SPI DM driver used on SoCFPGAStefan Roese2014-12-06-0/+426
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the driver for the Designware master SPI controller. This IP core is integrated on the Altera SoCFPGA. This implementation is a driver model (DM) implementation. So multiple SPI drivers can be used. Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller used to connect the SPI NOR flashes. Without DM, using multiple SPI drivers is not possible. This driver is very loosely based on the Linux driver. Most of the Linux driver is removed. Only the polling loop for the transfer is really used from this driver, as we don't support interrupts and DMA right now. This is tested on the SoCrates SoCFPGA board using the SPI pins on the P14 header. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | spi: Add Cadence QSPI DM driver used by SoCFPGAStefan Roese2014-12-06-0/+1320
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver is cloned from the Altera Rockerboard.org U-Boot repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some modification to support the U-Boot driver model (DM). As mentioned above, in this new version I ported this driver to the new driver model (DM). One big advantage of this move is that now multiple SPI drivers can be enabled on one platform. And since the SoCFPGA also has the Designware SPI master controller integrated, this feature is really needed to support both controllers. Because of this, this series needs the DT support for SoCFPGA to be applied. For DT based probing in the SPI DM. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | | Merge git://git.denx.de/u-boot-x86Tom Rini2014-12-15-129/+157
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| * | | x86: ich-spi: Add Intel Tunnel Creek SPI controller supportBin Meng2014-12-13-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Intel Tunnel Creek SPI controller support which is an ICH7 compatible device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | x86: Add a simple superio driver for SMSC LPC47MBin Meng2014-12-13-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8) are provided by a superio chip connected to the LPC bus. We must program the superio chip so that serial ports are available for us. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | x86: ich6-gpio: Move setup_pch_gpios() to board support codesBin Meng2014-12-13-51/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Movie setup_pch_gpios() in the ich6-gpio driver to the board support codes, so that the driver does not need to know any platform specific stuff (ie: include the platform specifc chipset header file). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | x86: ich-spi: Set the tx operation mode for ich 7Bin Meng2014-12-13-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ICH 7 SPI controller only supports byte program (02h) for SST flash. Word program (ADh) is not supported. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | | x86: ich-spi: Set the rx operation mode for ich 7Bin Meng2014-12-13-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ICH 7 SPI controller only supports array read command (03h). Fast array read command (0Bh) is not supported. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | | sf: Enable byte program supportJagannadha Sutradharudu Teki2014-12-13-12/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enabled byte program support for sst flashes in sf. Few controllers will only support BP, so this patch gives a tx transfer flag to set the BP so-that sf will operate on byte program transfer. A new TX operation mode SPI_OPM_TX_BP is introduced for such SPI controller to use byte program op for SST flash. Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * | | spi: sf: Support byte program for sst spi flashBin Meng2014-12-13-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently if SST flash advertises SST_WP flag in the params table the word program command (ADh) with auto address increment will be used for the flash write op. However some SPI controllers do not support the word program command (like the Intel ICH 7), the byte programm command (02h) has to be used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | | spi: Fix flag collision for SST_WPSimon Glass2014-12-13-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present SECT_4K is the same as SST_WP so we cannot tell these apart. Fix this so that the table in sf_params.c can be used correctly. Reported-by: Jens Rottmann <Jens.Rottmann@adlinktech.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | | sf: Fix look for the fastest read commandJagannadha Sutradharudu Teki2014-12-13-56/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Few of the spi controllers are only supports array slow read which is quite different behaviour compared to others. So this fix on sf will correctly handle the slow read supported controllers. Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * | | bios_emulator: Correct ordering of includesSimon Glass2014-12-13-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We should include common.h before other includes. This actually causes a build error on chromebook_link. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-10 15:35:02 +0000