| Commit message (Collapse) | Author | Age | Lines |
|---|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The DMA was outputting the palette on the screen because the base
for the DMA was not after the palette. In addition to that, the ceiling was
also too high, this led that the output on the screen was shifted.
NOTE: According to the TRM, even in 16/24bit mode a palette is required
in the first 32 bytes of the framebuffer.
See also:
https://e2e.ti.com/support/arm/sitara_arm/f/791/p/234967/834483#834483
"In this mode, the LCDC will assume all information is data and thus you
need to ensure that the DMA points to the first pixel of data and not the
first entry in the frame buffer which is the beginning of the 512 byte
palette."
Signed-off-by: Martin Pietryka <martin.pietryka@chello.at>
Reviewed-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
To support 16bpp we just need to change the raster_ctrl register
accordingly. Also 32bpp mode should work as well, but was not tested.
According to the TRM the uppermost byte will be ignored when
LCD_TFT_24BPP_UNPACK is set.
The switch logic is based on the Linux kernel tilcdc driver:
drivers/gpu/drm/tilcdc/tilcdc_crtc.c: lines 407 through 419
(kernel was checked out at commit: bcc981e9ed8)
Signed-off-by: Martin Pietryka <martin.pietryka@chello.at>
Reviewed-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at>
|
| |
|
|
|
|
|
| |
According to the TRM you have to set bits [21:20] to 0b10 for RAW mode, so
(0x10 << 20) is obviously wrong here.
Signed-off-by: Martin Pietryka <martin.pietryka@chello.at>
|
| |
|
|
|
|
|
|
|
|
|
| |
Since i've been married, i also have a new surname.
Mr. Petermaier moved to Mr. Schmelzer.
In this patch i update all files in which my (old) name is present.
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
| |
Often on boards exists a circuit which switches power on/off to LCD display.
Due to the need of limiting the in-rush current the output voltage from this
circuit rises "slowly", so it is necessary to wait a bit (VCC ramp up time)
before starting output on LCD-pins.
This time is specified in <n> ms within the panel-settings, called "pup_delay"
Further some LCDs need a couple of frames to stabilize the image on it.
We have now the possibility to wait some time after starting output on LCD.
This time is also specified in <n> ms within panel-settings, called "pon_delay"
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
|
|
|
- Adds support for a minimal framebuffer driver of TI's AM335x SoC
to be compatible with Wolfgang Denk's LCD-Framework (CONFIG_LCD,
common/lcd.c)
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
|
