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* usb: use __weakJeroen Hofstee2014-10-25-12/+3
| | | | Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* arm: marvell: Move arch/kirkwood.h to arch/soc.hStefan Roese2014-10-23-1/+1
| | | | | | | | | This move makes is possible to use this header not only from kirkwood platforms but from all Marvell mvebu platforms. Signed-off-by: Stefan Roese <sr@denx.de> Tested-by: Luka Perkov <luka@openwrt.org> Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
* Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2014-10-11-23/+47
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| * usb: tegra: ULPI regression on tegra20Marcel Ziswiler2014-10-06-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Trying to enumerate USB devices connected via ULPI to T20 failed as follows: USB2: ULPI integrity check failed Git bisecting revealed the following commit being at odds: commit 2d34151f7501ddaa599897f0d89ad576126b03eb usb: tegra: refactor PHY type selection Looking at above commit one quickly identifies a copy paste error which this patch fixes. Happy ULPIing again (;-p). Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
| * usb: ehci: Make periodic_schedules a per controller variableHans de Goede2014-10-06-5/+5
| | | | | | | | | | | | | | | | Periodic schedules tracks how many int_queue-s are active, and decides whether or not to en/disable the periodic schedule based on this. This is clearly a per controller thing. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * usb: ehci: poll_int_queue check real qtd, not the overlayHans de Goede2014-10-06-8/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we first start an int queue, the qh's overlay area is all zeros. This gets filled by the hc with the actual qtd values as soon as it advances the queue, but we may call poll_int_queue before then, in which case we would think the transfer has completed as the hc has not yet copied the qt_token to the overlay, so the active flag is not set. This fixes this by checking the actual qtd token, rather then the overlay. This also fixes a (theoretical) race where we see the completion in the overlay and free and re-use the qtd before the hc has completed writing back the overlay to the actual qtd. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * usb: ehci: Add missing cache flush to destroy_int_queueHans de Goede2014-10-06-0/+2
| | | | | | | | Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * usb: ehci: Properly set hub devnum and portnr with usb-1 hubs in the chainHans de Goede2014-10-06-8/+28
| | | | | | | | | | | | | | | | For full / low speed devices we need to get the devnum and portnr of the tt, so of the first upstream usb-2 hub, not of the parent device (which may be a usb-1 hub). Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | usb: ehci-mx6: Rename the USB register base addressYe.Li2014-09-29-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | The mx6sl/mx6sx has 2 OTG and 1 host. So they have name "USBO2H_USB_BASE_ADDR" in imx-regs.h. The driver hard codes the USB base address name to "USBOH3", which causes the driver failed to build for mx6sl/mx6sx. This patch uniform the address name to "USB_BASE_ADDR" for all mx6 series. Signed-off-by: Ye.Li <B37916@freescale.com>
* | usb: ehci: mxs: Add board-specific callbacksMarek Vasut2014-09-29-0/+16
|/ | | | | | | | | Add board-specific callbacks for enabling/disabling port power into the MXS EHCI controller driver. This is in-line with the names of callbacks on other systems. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* USB: ehci-atmel: use pcr to enable or disable clockBo Shen2014-09-19-0/+8
| | | | | | | | If the SoC has pcr, we use pcr (peripheral control register) to enable or disable clock. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* USB: ohci-at91: use pcr to enable or disable clockBo Shen2014-09-19-4/+4
| | | | | | | | If the SoC has pcr, we use pcr (peripheral control register) to enable or disable clock. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-08-28-0/+202
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| * sunxi: add USB EHCI driverRoman Byshko2014-07-31-0/+202
| | | | | | | | | | | | | | | | | | The Allwinner aka sunxi SoCs have one or more USB host controllers. This adds a driver for their EHCI. Signed-off-by: Roman Byshko <rbyshko@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | usb: ehci: rmobile: Remove xHCI addressNobuhiro Iwamatsu2014-08-09-3/+0
| | | | | | | | | | | | | | | | echi-rmobile does not support xHCI. This removes xHCI address from address table. And this revise a value of CONFIG_USB_MAX_CONTROLLER_COUNT for lager board and koelsh board. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* | usb: ehci: rmobile: Add support R8A7794Nobuhiro Iwamatsu2014-08-09-0/+6
|/ | | | | | | R8A7794 has same IP of USB controller as R8A7790 and R8A7791. This addes support for R8A7794. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* driver/usb: include upper/lower_32_bits() from linux/compat.hLijun Pan2014-07-22-4/+2
| | | | | | | upper_32_bits() and lower_32_bits() have been ported into linux/compat.h. Start use them now in drivers/usb/host/xhci.h. Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com>
* usb: host: xhci: make sure to power up PHYFelipe Balbi2014-07-09-0/+1
| | | | | | | some boards won't work if the PHY isn't explicitly powered up. Signed-off-by: Felipe Balbi <balbi@ti.com>
* arm: ep9315: Return back Cirrus Logic EDB9315A board supportSergey Kostanbaev2014-07-04-0/+39
| | | | | | | This patch returns back support for old ep93xx processors family Signed-off-by: Sergey Kostanbaev <sergey.kostanbaev@gmail.com> Cc: albert.u.boot@aribaud.net
* usb: xhci: (likely) fix bracket in if conditionJeroen Hofstee2014-06-25-2/+2
| | | | | | | | | Because of the brackets the & and && is evaluated before the comparison. This is likely not the intention. Change it to test the first and second condition to both be true. cc: Marek Vasut <marex@denx.de> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* usb: r8a66597: Fix initilization size of r8a66597 info structureYasuhisa Umano2014-06-25-1/+1
| | | | | | | | Initialization of r8a66597 info structure is not enough. Because initilization was used size of pointer. This fixes that use size of r8a6659 info structure. Signed-off-by: Yasuhisa Umano <yasuhisa.umano.zc@renesas.com>
* usb: r8a66597: Fix initialization hub that using R8A66597_MAX_ROOT_HUByasuhisa umano2014-06-25-2/+2
| | | | | | | | | This driver is processed as two USB hub despite one. The number of root hub is defined in R8A66597_MAX_ROOT_HUB. This fixes that register is accessed by using the definition of R8A66597_MAX_ROOT_HUB. Signed-off-by: Yasuhisa Umano <yasuhisa.umano.zc@renesas.com>
* Merge branch 'u-boot-microblaze/zynq' into 'u-boot-arm/master'Albert ARIBAUD2014-05-23-0/+105
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| * ARM: zynq: ehci: Added USB host driver supportMichal Simek2014-05-14-0/+105
| | | | | | | | | | | | | | Added USB host driver for zynq. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge branch 'pr-15052014' of git://git.denx.de/u-boot-usbTom Rini2014-05-22-59/+106
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| * | usb: tegra: support device modeStephen Warren2014-05-15-30/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few changes are made to the Tegra EHCI driver so that it can set everything up for device-mode operation on the first USB controller. This can be used in conjunction with ci_udc.c to operate as a USB device. Detailed changes are: * Rename set_host_mode() to set_up_vbus() since that's really what it does. * Modify set_up_vbus() to know whether it's initializing in host or device mode, and: - Skip the external VBUS check in device mode, since external VBUS is expected in this case. - Disable VBUS output in device mode. * Modify init_phy_mux() to know whether it's initializing in host or device mode, and hence skip setting USBMODE_CM_HC (which enables host mode) in device mode. See the comments in that function for why this is safe w.r.t. the ordering requirements of PHY selection. * Modify init_utmi_usb_controller() to force "b session valid" in device mode, since the HW requires this. This is done in UTMI-specific code, since we only support device mode on the first USB controller, and that controller can only talk to a UTMI PHY. * Enhance ehci_hcd_init() to error-check the requested host-/device-mode vs. the dr_mode (dual-role mode) value present in device tree, and the HW configurations which support device mode. * Enhance ehci_hcd_init() not to skip HW initialization when switching between host and device mode on a controller. This requires remembering which mode the last initialization used. Cc: Jim Lin <jilin@nvidia.com> Cc: Stefan Agner <stefan@agner.ch> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | usb: tegra: refactor PHY type selectionStephen Warren2014-05-15-30/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Both init_{utmi,ulpi}_usb_controller() have nearly identical code for PHY type selection. Pull this out into a common function to remove the duplication. Cc: Jim Lin <jilin@nvidia.com> Cc: Stefan Agner <stefan@agner.ch> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | usb: tegra: fix PHY selection codeStephen Warren2014-05-15-13/+8
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TRM for Tegra30 and later all state that USBMODE_CM_HC must be set before writing to hostpc1_devlc to select which PHY to use for a USB controller. However, neither init_{utmi,ulpi}_usb_controller() do this today, so the register writes they perform for PHY selection do not work. For the UTMI case, this was hacked around in commit 7e44d9320ed4 "ARM: Tegra: USB: EHCI: Add support for Tegra30/Tegra114" by adding code to ehci_hcd_init() which sets USBMODE_CM_HC and duplicates the PHY selection register write. This code doesn't cover the ULPI case, so I wouldn't be surprised if ULPI doesn't work with the current code, unless the ordering requirement only ends up being an issue in HW for UTMI not ULPI. This patch fixes init_{utmi,ulpi}_usb_controller() to correctly set USBMODE_CM_HC before selecting the PHY. Now that this works, we can remove the duplicate UTMI-specific code in ehci_hcd_init(), thus simplifying that function. Cc: Jim Lin <jilin@nvidia.com> Cc: Stefan Agner <stefan@agner.ch> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | drivers/usb : Define usb control register mask for w1c bitsNikhil Badola2014-05-16-5/+10
|/ | | | | | | | | | Define and use CONTROL_REGISTER_W1C_MASK to make sure that w1c bits of usb control register do not get reset while writing any other bit Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Merge branch 'u-boot/master'Albert ARIBAUD2014-05-09-29/+202
|\ | | | | | | | | | | | | Conflicts: drivers/net/Makefile (trivial merge)
| * exynos: usb: Fix data abort on boards w/o vbus-gpio node in the DTandrey.konovalov@linaro.org2014-04-30-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 4a271cb1b4ff doesn't take into account that fdtdec_setup_gpio() returns success when the gpio passed to it is FDT_GPIO_NONE (no gpio node found in the fdtdec_decode_gpio() call). This results in calling gpio_direction_output() on invalid gpio. For this reason executing "usb start" command on Arndale causes data abort in the ehci-exynos driver. Add the fdt_gpio_isvalid() check to fix that problem. Signed-off-by: Andrey Konovalov <andrey.konovalov@linaro.org> Cc: Julius Werner <jwerner@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de>
| * usb: Add endian support macros to interrupt transfers in the EHCI driver.Adrian Cox2014-04-30-25/+31
| | | | | | | | | | | | Update the EHCI driver to support interrupt transfers on PowerPC. Signed-off-by: Adrian Cox <adrian@humboldt.co.uk>
| * usb: ehci: rmobile: Add support ehci host driver of rmobile SoCsNobuhiro Iwamatsu2014-04-30-0/+131
| | | | | | | | | | | | | | | | The rmobile SoC has usb host controller. This supports USB controllers listed in the R8A7790, R8A7791 and R8A7740. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Reviewed-by: Marek Vasut <marex@denx.de>
| * fsl/usb: Increase TXFIFOTHRESH value for usb write in T4 Rev 2.0Nikhil Badola2014-04-22-0/+20
| | | | | | | | | | | | | | | | | | | | | | Increase TXFIFOTHRES field value in TXFILLTUNING register of usb for T4 Rev 2.0. This decreases data burst rate with which data packets are posted from the TX latency FIFO to compensate for latencies in DDR pipeline during DMA. This avoids Tx buffer underruns and leads to successful usb writes Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * fsl/usb: Workaround for USB erratum-A007075Nikhil Badola2014-04-22-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | Put a delay of 5 millisecond after reset so that ULPI phy gets enough time to come out of reset. Erratum A007075 applies to following SOCs and their variants, if any P1010 rev 1.0 B4860 rev 1.0, 2.0 P4080 rev 2.0, 3.0 Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * fsl/usb: Fix phy type for Second USB controllerNikhil Badola2014-04-22-2/+6
| | | | | | | | | | | | | | | | | | Set correct phy_type value for second USB controller. This is required for supporting SOCs having 2 USB controllers working simultaneously, one with UTMI phy and other with ULPI phy Signed-off-by: Nikhil Badola <B46172@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | usb: tegra: combine header fileStefan Agner2014-04-17-1/+0
| | | | | | | | | | | | | | | | | | | | | | Combine the Tegra USB header file into one header file for all SoCs. Use ifdef to account for the difference, especially Tegra20 is quite different from newer SoCs. This avoids duplication, mainly for Tegra30 and newer devices. Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | usb: tegra: fix PHY configurationStefan Agner2014-04-17-3/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Tegra30 and later, the PTS (parallel transceiver select) and STS (serial transceiver select) are part of the HOSTPC1_DEVLC_0 register rather than PORTSC1_0 register. Since the reset configuration usually matches the intended configuration, this error did not show up on Tegra30 devices. Also use the slightly different bit fields of first USB, (USBD) on Tegra20 and move those definitions to the Tegra20 specific header file. Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | usb: tegra: fix USB2 powerdown for Tegra30 and laterStefan Agner2014-04-17-0/+3
|/ | | | | | | | | | | | Clear the forced powerdown bit in the UTMIP_PLL_CFG2_0 register which brings USB2 in UTMI mode to work. This was clearly missing since the forced powerdown bit is set in reset by default for all USB ports. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* usb: create common header virtual root hub descriptorsStephen Warren2014-03-10-393/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many USB host controller drivers contain almost identical copies of the same virtual root hub descriptors. Put these into a common file to avoid duplication. Note that there were some very minor differences between the descriptors in the various files, such as: - USB 1.0 vs. USB 1.1 - Manufacturer/Device ID - Max packet size - String content I assume these aren't relevant. Cc: Thomas Lange <thomas@corelatus.se> Cc: Shinya Kuribayashi <skuribay@pobox.com> Cc: Gary Jennejohn <garyj@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Eric Millbrandt <emillbrandt@coldhaus.com> Cc: Pierre Aubert <p.aubert@staubli.com> Cc: Stefan Roese <sr@denx.de> Cc: Daniel Hellstrom <daniel@gaisler.com> Cc: Denis Peter <d.peter@mpl.ch> Cc: Rodolfo Giometti <giometti@linux.it> Cc: Zhang Wei <wei.zhang@freescale.com> Cc: Mateusz Zalega <m.zalega@samsung.com> Cc: Remy Bohmer <linux@bohmer.net> Cc: Markus Klotzbuecher <mk@denx.de> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Gary Jennejohn <garyj@denx.de> Cc: C Nauman <cnauman@diagraph.com> Cc: David Müller <d.mueller@elsoft.ch> Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Thomas Abraham <t-abraham@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Andrew Murray <amurray@embedded-bits.co.uk> Cc: Matej Frančeškin <matej.franceskin@comtrade.com> Cc: Cliff Cai <cliff.cai@analog.com> Cc: Bryan Wu <cooloney@gmail.com> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* usb: ehci: fully align interrupt QHs/QTDsStephen Warren2014-03-10-2/+4
| | | | | | | | | These data structures are passed to cache-flushing routines, and hence must be conform to both the USB the cache-flusing alignment requirements. That means aligning to USB_DMA_MINALIGN. This is important on systems where cache lines are >32 bytes. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ush: ehci: initialize altnext pointers in QHStephen Warren2014-03-10-0/+2
| | | | | | | | | | | | | | | | | | | | | Section 4.10.2 "Advance Queue" of ehci-specification-for-usb.pdf specifies how an EHCI controller loads a new QTD for processing if the QH is not already marked as active. It states: ===== If the field Bytes to Transfer is not zero and the T-bit in the Alternate Next qTD Pointer is set to zero, then the host controller uses the Alternate Next qTD Pointer. Otherwise, the host controller uses the Next qTD Pointer. If Next qTD Pointer’s T-bit is set to a one, then the host controller exits this state and uses the horizontal pointer to the next schedule data structure. ===== Hence, we must ensure that the alternate next QTD pointer's T-bit (TERMINATE) is set, so the EHCI controller knows to use the next QTD pointer. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-02-25-1/+1
|\ | | | | | | | | | | | | With this, fixup a trivial build error of get_effective_memsize needing to be updated in the new board/freescale/p1010rdb/spl.c Signed-off-by: Tom Rini <trini@ti.com>
| * fsl/usb: Limit phy_type comparison to first four charactersNikhil Badola2014-02-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Use first four characters for phy_type comparison. Strcmp() should not be used to check the phy_type string which maybe parsed by hwconfig_subarg(). Hwconfig_subarg() returns part of hwconfig string starting from phy_type value till the end of the string. Since phy_type could be either "utmi" or "ulpi", strncmp() should be used so that a comparison of "utmi;fsl_ddr:bank_intlv=auto" with "utmi" will succeed. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | ARM: USB: Remove the IXP EHCI driverMarek Vasut2014-02-06-38/+0
|/ | | | | | | | | The driver is no longer used, remove it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Michael Schwingen <michael@schwingen.org> Cc: Tom Rini <trini@ti.com>
* usb: exynos5: arndale: Add network supportInderpal Singh2014-01-13-0/+2
| | | | | | | | | | | | Arndale board has AX88760, which is USB 2.0 Hub & USB 2.0 Ethernet Combo controller, connected to HSIC Phy of USB host controller via USB3503 hub. This patch uses board specific board_usb_init function to perform reset sequence for USB3503 hub and enables the relevant config options for network to work. Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org> Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
* usb: ehci: exynos: set/reset hsic physInderpal Singh2014-01-13-0/+39
| | | | | | | | The controller has 3 ports. The port0 is for USB 2.0 Phy, port1 and port2 are for HSIC phys. The usb 2.0 phy is already being setup. This patch sets up the hsic phys. Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
* usb: ehci: Fix register accessMarek Vasut2013-12-18-1/+1
| | | | | | | | Fix the register access in EHCI HCD. We need to use address of the register as an ehci_writel() argument. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org>
* usb: ehci: Do not de-init uninited controllersMarek Vasut2013-12-18-0/+3
| | | | | | | | | In case the controller is not initialized, we shall not de-initialize it. As the control structure will not be filled, we will produce a null ptr dereference if the controller is not inited. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org>
* usb: ehci-pci: Clarify and cleanup the EHCI controller detectionMarek Vasut2013-12-18-3/+25
| | | | | | | | | The detection function of the EHCI PCI controller was really cryptic, add a beefy comment and clean the portion of the code up a bit. No change in the logic of the code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org>
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