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* bitops: introduce BIT() definitionHeiko Schocher2015-09-11-4/+0
| | | | | | | | | | | introduce BIT() definition, used in at91_udc gadget driver. Signed-off-by: Heiko Schocher <hs@denx.de> [remove all other occurrences of BIT(x) definition] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
* Move ALLOC_CACHE_ALIGN_BUFFER() to the new memalign.h headerSimon Glass2015-09-11-0/+1
| | | | | | | Now that we have a new header file for cache-aligned allocation, we should move the stack-based allocation macro there also. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Add SPI driverSimon Glass2015-09-02-0/+507
| | | | | | | Add a SPI driver for the Rockchip RK3288, using driver model. It should work for other Rockchip SoCs also. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Use dev_get_addr() where possibleSimon Glass2015-08-31-7/+7
| | | | | | | | | | This is a convenient way for a driver to get the hardware address of a device, when regmap or syscon are not being used. Change existing callers to use it as an example to others. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-08-18-1/+26
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| * spi: ti_qspi: Use DMA to read from qspi flashVignesh R2015-08-17-0/+25
| | | | | | | | | | | | | | | | ti_qspi uses memory map mode for faster read. Enabling DMA will increase read speed by 3x @48MHz on DRA74 EVM. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * ti: qspi: set flash quad bit based on quad support flagvishalm@ti.com2015-08-17-1/+1
| | | | | | | | | | | | | | | | Update op_mode_rx flag based on CONFIG_QSPI_QUAD_SUPPORT flag, instead of platform. Signed-off-by: Vishal Mahaveer <vishalm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* | ARM: exynos: move SoC sources to mach-exynosThomas Abraham2015-08-17-1/+1
|/ | | | | | | | | | | | | | Move arch/arm/cpu/armv7/exynos/* to arch/arm/mach-exynos/* to allow reuse of existing code for ARMv8 based Exynos platforms. Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* spi: omap3_spi: add am43xx support to omap3_spiNikita Kiryanov2015-08-12-1/+1
| | | | | | | | | Add support for AM43XX to the omap3_spi driver. Cc: Jagan Teki <jteki@openedev.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Reviewed-by: Jagan Teki <jteki@openedev.com>
* lib/fdtdec: Fix compiling warning caused by changing fdt_addr_t typeYork Sun2015-08-06-2/+2
| | | | | | | | fdt_addr_t is changed to phys_addr_t. The format in debug should be updated to %pa to match the type. Signed-off-by: York Sun <yorksun@freescale.com> CC: Simon Glass <sjg@chromium.org>
* exynos: spi: Convert the timeout to debug()Simon Glass2015-08-05-3/+3
| | | | | | | | | | | Since the timeout is reported through normal channels, and is sometimes expected (e.g. if the bus is being probed for a non-existent device), don't display the message in the driver. In general, drivers should not write to the console as this limits their usefulness in error conditions. Signed-off-by: Simon Glass <sjg@chromium.org>
* spi: zynq_spi: Simplify debug macroMichal Simek2015-07-28-1/+1
| | | | | | Trivial fix. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* spi: Fix zynq SPI bindingMichal Simek2015-07-28-1/+1
| | | | | | | | Zynq is using Cadence IP where binding is documented in the Linux kernel and there is no reason to use different binding. Synchronize it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* dm: spi: Make local functions staticSimon Glass2015-07-21-4/+4
| | | | | | Several functions in this file should be marked as static. Update them. Signed-off-by: Simon Glass <sjg@chromium.org>
* fdt: armv8: Fix build warnings on armv8Haikun Wang2015-07-20-2/+2
| | | | | | | | | | | | | | | | | | | Fix below build warnings on armv8, drivers/spi/fsl_dspi.c: In function ‘fsl_dspi_ofdata_to_platdata’: drivers/spi/fsl_dspi.c:667:2: warning: format ‘%x’ expects argument of type ‘unsigned int’, but argument 2 has type ‘fdt_addr_t’ [-Wformat=] debug("DSPI: regs=0x%x, max-frequency=%d, endianess=%s, num-cs=%d\n", ^ lib/fdtdec.c: In function ‘fdtdec_get_addr_size’: lib/fdtdec.c:105:4: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 3 has type ‘fdt_size_t’ [-Wformat=] debug("addr=%08lx, size=%08lx\n", ^ Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Acked-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-x86Tom Rini2015-07-15-9/+11
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| * dm: spi: Correct BIOS protection logic for ICH9Simon Glass2015-07-14-5/+4
| | | | | | | | | | | | | | | | | | The logic is incorrect and currently has no effect. Fix it so that we can write to SPI flash, since by default it is write-protected. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
| * dm: spi: Correct status register access widthSimon Glass2015-07-14-1/+5
| | | | | | | | | | | | | | | | | | The status register on ICH9 is a single byte, so use byte access when writing to it, to avoid updating the control register also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * dm: spi: Correct minor nits in ICH driverSimon Glass2015-07-14-3/+2
| | | | | | | | | | | | | | | | Tidy up three minor problems in this file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* | spi: cadence_qspi: support FIFO width other than 4 bytesVikas Manocha2015-07-03-23/+23
| | | | | | | | | | | | | | | | | | This patch makes the code compatible with FIFO depths other than 4 bytes. It also simplify read/write FIFO loops. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
* | spi: cadence_qspi: get sram size from device treeVikas Manocha2015-07-03-5/+3
| | | | | | | | | | | | | | | | | | sram size could be different on different socs, e.g. on stv0991 it is 256 while on altera platform it is 128. It is better to receive it from device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
* | spi: cadence_qspi: move the sram partition in initVikas Manocha2015-07-03-11/+5
|/ | | | | | | | | | There is no need to re-configure sram partition for every read/write for better full use of sram for read or write. This patch divides the half sram for read & half for write once at initialization. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
* spi: cf_qspi: fix clamp macro type check compilation warningsAngelo Dureghello2015-07-01-2/+1
| | | | | | | | Fix compilation warnings for redefined 'clamp' macro and non-uniform clamp macro types. Signed-off-by: Angelo Dureghello <angelo@sysam.it> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
* spi: Kconfig: Add TEGRA20_SLINK entryJagan Teki2015-07-01-0/+7
| | | | | | | | | Added TEGRA20_SLINK entry on Kconfig with help description. Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Tom Warren <twarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com>
* spi: Kconfig: Add TEGRA20_SFLASH entryJagan Teki2015-07-01-0/+7
| | | | | | | | | Added TEGRA20_SFLASH entry on Kconfig with help description. Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Tom Warren <twarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com>
* spi: Kconfig: Add TEGRA114_SPI entryJagan Teki2015-07-01-0/+10
| | | | | | | | | Added TEGRA114_SPI entry on Kconfig with help description. Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Tom Warren <twarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com>
* spi: Kconfig: Add ICH_SPI entryJagan Teki2015-07-01-0/+7
| | | | | | | | Added ICH_SPI entry on Kconfig with help description. Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* spi: Kconfig: Add EXYNOS_SPI entryJagan Teki2015-07-01-0/+7
| | | | | | | Added EXYNOS_SPI entry on Kconfig with help description. Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* spi: Kconfig: Add FSL_QSPI entryJagan Teki2015-07-01-0/+7
| | | | | | | | Added FSL_QSPI entry on Kconfig with help description. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Peng Fan <Peng.Fan@freescale.com> Cc: Haikun Wang <haikun.wang@freescale.com>
* spi: Kconfig: Add FSL_ESPI entryJagan Teki2015-07-01-0/+7
| | | | | | | Added FSL_ESPI entry on Kconfig with help description. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Haikun Wang <haikun.wang@freescale.com>
* spi: Kconfig: Add FSL_DSPI entryJagan Teki2015-07-01-0/+8
| | | | | | | Added FSL_DSPI entry on Kconfig with help description. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Haikun Wang <haikun.wang@freescale.com>
* spi: Kconfig: Show dm-spi drivers if DM_SPI setJagan Teki2015-07-01-25/+26
| | | | | | | | | | DM supported spi drivers are enbled only when DM_SPI enabled, so added DM_SPI if condition in Kconfig to show thoese only when it enabled. Also re-order the config items as incresing alphabetic order. Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: Makefile: Use object file alphabetic orderJagan Teki2015-07-01-5/+5
| | | | | | | Use object files as incresing alphabetic order, so-that it's easy for readability. Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: Kconfig: Add TI_QSPI entryJagan Teki2015-07-01-0/+6
| | | | | | | Added TI_QSPI entry on Kconfig with help description. Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* spi: Kconfig: Add XILINX_SPI entryJagan Teki2015-07-01-0/+9
| | | | | | | Added XILINX_SPI entry on Kconfig with help description. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Michal Simek <michal.simek@xilinx.com>
* spi: Add Kconfig menu entryJagan Teki2015-07-01-0/+4
| | | | | | Added Kconfig menu ... endmenu enties for spi support. Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: Kconfig: Add Zynq SPI controller entryJagan Teki2015-07-01-0/+8
| | | | | | | | | | Add Zynq SPI controller Kconfig entry. Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Marek Vasut <marex@denx.de> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
* spi: xilinx_spi: Add asm/io.h include fileJagan Teki2015-07-01-0/+1
| | | | | | | | | | | | | This patch includes asm/io.h for readl and writel calls. build errors: drivers/spi/xilinx_spi.c: In function 'xilinx_spi_probe': drivers/spi/xilinx_spi.c:119:2: warning: implicit declaration of function 'writel' [-Wimplicit-function-declaration] drivers/spi/xilinx_spi.c: In function 'xilinx_spi_xfer': drivers/spi/xilinx_spi.c:193:2: warning: implicit declaration of function 'readl' [-Wimplicit-function-declaration] Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Michal Simek <michal.simek@xilinx.com>
* dm: spi: xilinx_spi: Convert to driver modelJagan Teki2015-07-01-88/+112
| | | | | | | | This converts the xilinx spi driver to use the driver model. Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com>
* spi: zynq_spi: Add fdt support in driverJagan Teki2015-07-01-10/+13
| | | | | | | | | | | | | | | | | Now zynq spi driver platform data is controlled by devicetree, enable the status by saying "okay" on respective board dts to use the devicetree generated platdata. Ex: &spi1 { status = "okay"; }; Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
* dm: spi: zynq_spi: Convert to driver modelJagan Teki2015-07-01-124/+169
| | | | | | | | | | | | | | | | This converts the zynq spi driver to use the driver model. Minimal functional changes like using meaningful name on structure members wrt mainlined dm spi drivers. - input_hz -> frequency - req_hz -> freq - base -> regs Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
* spi: davinci_spi: Driver cleanupJagan Teki2015-07-01-170/+173
| | | | | | | | | | Arrange driver code in more readable format[1] for easy accessing and readable. [1] http://patchwork.ozlabs.org/patch/265683/ Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Rex Chang <rchang@ti.com> Cc: Murali Karicheri <m-karicheri2@ti.com>
* spi: davinci_spi: Move header code to driverJagan Teki2015-07-01-122/+109
| | | | | | | | | Move the header code into driver for more readable and easy to access it. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Rex Chang <rchang@ti.com> Cc: Murali Karicheri <m-karicheri2@ti.com>
* spi: xilinx_spi: Driver clean-upJagan Teki2015-07-01-107/+57
| | | | | | | | | | | | | | - Zap unneeded macros - Re-arrange the code - Removed __attribute__((weak)) - Replace __func__ macro with func names to save macro transition. - Re-arranged comment lines. - Arrange driver code in more readable format[1] [1] http://patchwork.ozlabs.org/patch/265683/ Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
* spi: xilinx_spi: Move header code to driverJagan Teki2015-07-01-139/+112
| | | | | | | | Move the header code into driver for more readable and easy to access it. Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
* spi: Zap oc_tiny_spi driverJagan Teki2015-07-01-246/+0
| | | | | | | | Zap oc_tiny_spi driver since the boards used this driver is no longer been active. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Thomas Chou <thomas@wytron.com.tw>
* spi: Zap ftssp010_spi driverJagan Teki2015-07-01-499/+0
| | | | | | | | | Zap ftssp010_spi driver since the boards used this driver is no longer been active. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Kuo-Jung Su <dantesu@faraday-tech.com> Cc: Axel Lin <axel.lin@ingics.com>
* spi: Zap andes_spi driverJagan Teki2015-07-01-400/+0
| | | | | | | | Zap andes_spi driver since the boards used this driver is no longer been active. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Macpaul Lin <macpaul@andestech.com>
* tegra: spi: Support slow SPI ratesSimon Glass2015-06-09-3/+15
| | | | | | | | | Use the oscillator as the source clock when we cannot achieve a low-enough speed with the peripheral clock. This happens when we request 3MHz on a SPI clock, for example. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: spi: Drop the claim_bus() method to correct delaysSimon Glass2015-06-09-17/+9
| | | | | | | | | | | | | | | | At present the driver does not properly honour the requested SPI CS deactivation delay since the SPI bus is changed in the claim_bus() method. Everything the claim_bus() method does can be done when the device is probed (setting the speed and mode) and at the start of a new transfer (where the fifo_status is already cleared). So drop this method. Also, until the delay is complete, we should not touch the bus, so make sure that spi_cs_activate() is called before other things are done in the xfer() method. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
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