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* | | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2013-06-13-24/+62
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| * | spi: tegra20_sflash: Remove redundant code to set bus and cs of struct spi_slaveAxel Lin2013-06-13-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | It's done in spi_alloc_slave(), thus remove the redundant code. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | spi: tegra114_spi: Convert to use spi_alloc_slave()Axel Lin2013-06-13-3/+1
| | | | | | | | | | | | | | | | | | Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | spi: armada100_spi: Remove unnecessary NULL test for dout and dinAxel Lin2013-06-13-9/+2
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Ajay Bhargav <ajay.bhargav@einfochips.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | spi: exynos: Support SPI_PREAMBLE modeRajeshwari Shinde2013-06-03-10/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support interfaces with a preamble before each received message. We handle this when the client has requested a SPI_XFER_END, meaning that we must close of the transaction. In this case we read until we see the preamble (or a timeout occurs), skipping all data before and including the preamble. The client will receive only data bytes after the preamble. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | | Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-05-30-102/+3
|\ \ \ | |/ / | | | | | | | | | | | | Conflicts: common/cmd_fpga.c drivers/usb/host/ohci-at91.c
| * | bfin: discard invalid data and clear RXS in bf5xx spi driverScott Jiang2013-05-13-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | There may be dirty data in RDBR, so we should discard invalid data. This operation also clears RXS bit in STAT register. Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
| * | bfin: Remove spi dma function in bf5xx.Scott Jiang2013-05-13-102/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | BF5xx rx dma causes spi flash random read error. Accually spi controller has problems both on tx and rx dma. So remove spi dma support in u-boot. Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
* | | spi: atmel_spi: using ip version to check whether has wdrbtBo Shen2013-05-12-4/+13
| |/ |/| | | | | | | | | | | | | | | | | | | Using IP version to check whether it has wdrbt bit in mode register Tested in at91sam9x5ek and at91sam9n12ek. Signed-off-by: Bo Shen <voice.shen@atmel.com> [fix warning about incompatible parameter] Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | imx: Move some header files from arch-mxs to imx-commonStefan Roese2013-04-22-1/+1
|/ | | | | | | | | | | | | | | | | | | The following headers are moved to a i.MX common location: - regs-common.h - regs-apbh.h - regs-bch.h - regs-gpmi.h - dma.h This way this header can be re-used also by other i.MX platforms. For example the i.MX6 which will need it for the upcoming NAND support. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
* Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-04-14-8/+9
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| * spi: mxc_spi: Set master mode for all channelsFabio Estevam2013-04-13-8/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The glitch in the SPI clock line, which commit 3cea335c34 (spi: mxc_spi: Fix spi clock glitch durant reset) solved, is back now and itwas re-introduced by commit d36b39bf0d (spi: mxc_spi: Fix ECSPI reset handling). Actually the glitch is happening due to always toggling between slave mode and master mode by configuring the CHANNEL_MODE bits in this reset function. Since the spi driver only supports master mode, set the mode for all channels always to master mode in order to have a stable, "glitch-free" SPI clock line. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-04-12-1/+1
|\ \ | | | | | | | | | | | | Conflicts: drivers/video/exynos_fb.c
| * | Consolidate bool typeYork Sun2013-04-01-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'bool' is defined in random places. This patch consolidates them into a single header file include/linux/types.h, using stdbool.h introduced in C99. All other #define, typedef and enum are removed. They are all consistent with true = 1, false = 0. Replace FALSE, False with false. Replace TRUE, True with true. Skip *.py, *.php, lib/* files. Signed-off-by: York Sun <yorksun@freescale.com>
* | | Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2013-04-04-0/+2
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| * | | spi: exynos: Fix compiler warnings for non-dt systemsVivek Gautam2013-03-29-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enclosing process_nodes() and spi_get_config() inside CONFIG_OF_CONTROL, since they are compiled only for DT systems. This fixes following warning: exynos_spi.c:391:12: warning: 'process_nodes' defined but not used [-Wunused-function] Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-04-04-4/+4
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| * | spi: mxc_spi: Fix ECSPI reset handlingDirk Behme2013-04-04-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reviewing the ECSPI reset handling shows two issues: 1. For the enable/reset bit (MXC_CSPICTRL_EN) in the control reg (ECSPIx_CONGREG) the i.MX6 technical reference manual states: -- cut -- ECSPIx_CONREG[0]: EN: Writing zero to this bit disables the block and resets the internal logic with the exception of the ECSPI_CONREG. -- cut -- Note the exception mentioned: The CONREG itself isn't reset. Fix this by manually writing the reset value 0 to the whole register. This sets the EN bit to zero, too (i.e. includes the old ~MXC_CSPICTRL_EN). 2. We want to reset the whole SPI block here. So it makes no sense to first read the old value of the CONREG and write it back, later. This will give us the old (historic/random) value of the CONREG back. And doesn't reset the CONREG. To get a clean CONREG after the reset of the block, too, don't use the old (historic/random) value of the CONREG while doing the reset. And read the clean CONREG after the reset. This was found while working on a SPI boot device where the i.MX6 boot ROM has already initialized the SPI block. The initialization by the boot ROM might be different to what the U-Boot driver wants to configure. I.e. we need a clean reset of SPI block, including the CONREG. Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com>
* | | Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-03-28-150/+792
|\ \ \ | | |/ | |/| | | | | | | | | | | | | Conflicts: drivers/spi/tegra20_sflash.c include/fdtdec.h lib/fdtdec.c
| * | tegra114: add SPI driverAllen Martin2013-03-25-0/+421
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add driver for tegra114 SPI controller. This controller is not compatible with either the tegra20 or tegra30 controllers, so it requires a new driver. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * | spi: add common fdt SPI driver interfaceAllen Martin2013-03-25-45/+197
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a common interface to fdt based SPI drivers. Each driver is represented by a table entry in fdt_spi_drivers[]. If there are multiple SPI drivers in the table, the first driver to return success from spi_init() will be registered as the SPI driver. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * | tegra20: spi: move fdt probe to spi_initAllen Martin2013-03-25-43/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the tegra20 SPI driver similar to the tegra30 (and soon to be tegra114) SPI drivers in preparation of common fdt SPI driver front end. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * | tegra: spi: pull register structs out of headersAllen Martin2013-03-25-11/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move register structs from headers into .c files and use common name. This is in preparation of making common fdt front end for SPI drivers. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * | tegra: spi: remove non fdt supportAllen Martin2013-03-25-37/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove non fdt support from tegra20 and tegra30 SPI drivers in preparation of new common fdt based SPI driver front end. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * | tegra: spi: rename tegra SPI driversAllen Martin2013-03-25-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Rename tegra SPI drivers to tegra20_flash and tegra20_slink in preparation for commonization and addition of tegra114_spi. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * | tegra: remove support for UART SPI switchAllen Martin2013-03-25-24/+1
| |/ | | | | | | | | | | | | | | | | | | This feature was only used for tegra20 seaboard that had a pinmux conflict on the SPI pins. These boards were never manufactured, so remove this support to clean up SPI driver. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* | x86: spi: Set maximum write size for ICHSimon Glass2013-03-19-0/+5
| | | | | | | | | | | | | | This SPI controller can only write 64 bytes at a time. Add this restriction in so that 'sf write' works correct for blocks larger than 64 bytes. Signed-off-by: Simon Glass <sjg@chromium.org>
* | x86: spi: Add Intel ICH driverSimon Glass2013-03-19-0/+893
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This supports Intel ICH7/9. The Intel controller is a little unusual in that it is mostly intended for use with SPI flash, and has some optimisations and features specifically for that application. In particular it is not possible to support ongoing transactions that continue over many calls with SPI_XFER_BEGIN and SPI_XFER_END. This driver supports writes of up to 64 bytes at a time, the limit for the controller. Future work will improve this. Signed-off-by: Bernie Thompson <bhthompson@chromium.org> Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* | spi: Use spi_alloc_slave() in each SPI driverSimon Glass2013-03-19-83/+36
| | | | | | | | | | | | | | | | Rather than each driver having its own way to allocate a SPI slave, use the new allocation function everywhere. This will make it easier to extend the interface without breaking drivers. Signed-off-by: Simon Glass <sjg@chromium.org>
* | spi: Add function to allocate a new SPI slaveSimon Glass2013-03-19-0/+42
|/ | | | | | | | | | At present it is difficult to extend the SPI structure since all drivers allocate it themselves, and few of them zero all fields. Add a new function spi_alloc_slave() which can be used by SPI drivers to perform this allocation, and thus ensure that all drivers can better cope with SPI structure changes. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-03-15-20/+19
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| * mxs: spi: Remove CONFIG_MXS_SPI_DMA_ENABLEMarek Vasut2013-03-07-16/+0
| | | | | | | | | | | | | | | | | | | | The CONFIG_MXS_SPI_DMA_ENABLE is no longer relevant as the SPI DMA has proven to work correctly. Remove this configuration option. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| * mxs: spi: Fix the MXS SPI for mx23Marek Vasut2013-03-07-2/+17
| | | | | | | | | | | | | | | | | | | | The MX23 has slightly different register layout. Adjust the SPI driver to match the layout, both the PIO and DMA part. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| * mxs: mmc: spi: dma: Better wrap the MXS differencesMarek Vasut2013-03-07-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch streamlines the differences between the MX23 and MX28 by implementing a few helper functions to handle different DMA channel mapping, different clock domain for SSP block and fixes a few minor bugs. First of all, the DMA channel mapping is now fixed in dma.h by defining the actual channel map for both MX23 and MX28. Thus, MX23 now does no longer use MX28 channel map which was wrong. Also, there is a fix for MX28 DMA channel map, where the last four channels were incorrect. Next, because correct DMA channel map is in place, the mxs_dma_init_channel() call now bases the channel ID starting from SSP port #0. This removes the need for DMA channel offset being added and cleans up the code. For the same reason, the SSP0 offset can now be used in mxs_dma_desc_append(), thus no need to adjust dma channel number in the driver either. Lastly, the SSP clock ID is now retrieved by calling mxs_ssp_clock_by_bus() which handles the fact that MX23 has shared SSP clock for both ports, while MX28 has per-port SSP clock. Finally, the mxs_ssp_bus_id_valid() pulls out two implementations of the same functionality from MMC and SPI driver into common code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
* | blackfin: add bf6xx spi driverScott Jiang2013-03-04-0/+309
|/ | | | | | | | | | Spi driver for bf60x is different from old one, so implement a new driver for it. Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bob Liu <lliubbo@gmail.com> Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-02-12-7/+389
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| * tegra: add SPI SLINK driverAllen Martin2013-02-11-0/+344
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add driver for tegra SPI "SLINK" style driver. This controller is similar to the tegra20 SPI "SFLASH" controller. The difference is that the SLINK controller is a genernal purpose SPI controller and the SFLASH controller is special purpose and can only talk to FLASH devices. In addition there are potentially many instances of an SLINK controller on tegra and only a single instance of SFLASH. Tegra20 is currently ths only version of tegra that instantiates an SFLASH controller. This driver supports basic PIO mode of operation and is configurable (CONFIG_OF_CONTROL) to be driven off devicetree bindings. Up to 4 devices per controller may be attached, although typically only a single chip select line is exposed from tegra per controller so in reality this is usually limited to 1. To enable this driver, use CONFIG_TEGRA_SLINK Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: spi: add fdt support to tegra SPI SFLASH driverAllen Martin2013-02-11-2/+43
| | | | | | | | | | | | | | | | | | Add support for configuring tegra SPI driver from devicetree. Support is keyed off CONFIG_OF_CONTROL. Add entry in seaboard dts file for spi controller to describe seaboard spi. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * mxs: clock: Use 'mxs' prefix for methodsOtavio Salvador2013-01-21-1/+1
| | | | | | | | | | | | | | Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * mxs: ssp: Pull out the SSP bus to regs conversionMarek Vasut2013-01-21-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Create function which converts SSP bus number to SSP register pointer. This functionality is reimplemented multiple times in the code, thus make one common implementation. Moreover, make it a switch(), since the SSP ports are not mapped in such nice linear fashion on MX23, therefore having it a switch will simplify things there. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andy Fleming <afleming@freescale.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* | spi: xilinx_spi: Perform software reset during slave setupJason Wu2013-02-04-0/+5
|/ | | | | | to make sure it is in the clear state. Signed-off-by: Jason Wu <huanyu@xilinx.com>
* Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2013-01-14-6/+90
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| * SPI: EXYNOS: Add FDT support to driver.Rajeshwari Shinde2013-01-08-6/+90
| | | | | | | | | | | | | | | | | | This patch adds FDT support to the SPI driver. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | Merge 'u-boot-atmel/master' into 'u-boot-arm/master'Albert ARIBAUD2013-01-09-1/+1
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| * | spi: atmel: sam9m10g45 also support WDRBT bitBo Shen2012-12-09-1/+1
| |/ | | | | | | | | | | | | The at91sam9m10g45 also support WDRBT bit, add support for it Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | kirkwood: make MPP arrays static constAlbert ARIBAUD2013-01-09-7/+5
| | | | | | | | | | | | | | | | | | | | This saves stack and code memory for local copy, and consumes initialized data memory. For 22 of the 29 kirkwood-based boards, this results in a global saving of about 30 bytes. For 7 of them, it results in an increase of 6 to 14 bytes. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | OMAP3 SPI : Fixed bugs related to SPI transferajoy2012-12-10-32/+45
|/ | | | | | | | | | | | | | | | | | | | | | Added posted writes (read after writes) to effect the change immediately for channel confiuration and channel enable register Disable the channel to purge receieve data in TX_ONLY mode transfer otherwise rx data will get affected by the next immediate RX_ONLY mode transfer Wait for the EOT bit to be set after last byte has been loaded to TX shift register in the the TX_ONLY mode.This ensures TX data has been completely shifted out Disable the channel in RX_ONLY mode before reading the last data from RXX register to prevent the SPI slave to transmit next word Signed-off-by: Ajoy Kumar Das <akdas75@yahoo.in> Cc: Tom Rini <trini@ti.com> Cc: jacopo mondi <j.mondi@voltaelectronics.com>
* Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2012-11-25-4/+5
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| * spi: mxc_spi: Fix spi clock glitch durant resetFabio Estevam2012-11-19-2/+2
| | | | | | | | | | | | | | | | | | | | | | Measuring the spi clock line on a scope shows a 'glitch' during the reset of the spi. Fix this by toggling only the MXC_CSPICTRL_EN bit, so that the clock line becomes always stable. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * spi: mxc_spi: Fix handling of chip selectFabio Estevam2012-11-19-2/+3
| | | | | | | | | | | | | | | | | | In decode_cs() function the polarity of the chip select must be taken into account. Also, for the case of low active chip select, the CS was activated too early. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
generated by cgit v1.1 at 2024-11-14 16:42:27 +0000