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* spi: kirkwood_spi: Add support for multiple chip-selects on MVEBUStefan Roese2016-04-06-0/+14
| | | | | | | | | | | | | Currently only chip-select 0 is supported by the kirkwood SPI driver. The Armada XP / 38x SoCs also use this driver and support multiple chip selects. This patch adds support for multiple CS on MVEBU. The register definitions are restructured a bit with this patch. Grouping them to the corresponding registers. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Jagan Teki <jteki@openedev.com>
* spi: kirkwood_spi.c: Add compatible match ID for Armada 375Stefan Roese2016-04-04-0/+1
| | | | | | | | This enables this driver for the Marvell Armada 375 SoC. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviwer-by: Jagan Teki <jteki@openedev.com>
* spi: omap3: Fix multiple definition of 'priv'Jagan Teki2016-03-15-19/+21
| | | | | | | | | | | | | Global definition of priv seems no-sense to use it for non-dm case and pass the pointer to functions which are common to both dm and non-dm. So, fix this by removing omap3_spi_slave from non-dm and make visible to omap3_spi_priv for both dm and non-dm. Cc: Christophe Ricard <christophe-h.ricard@st.com> Reported-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: omap3: Convert to driver modelJagan Teki2016-03-14-270/+416
| | | | | | | | | | | | | | | After this conversion the driver will able to support both dm and non-dm and code is more extensible like we can remove the non-dm part simply without touching anycode if all the boards which are using this driver become dm driven. Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Christophe Ricard <christophe-h.ricard@st.com> Tested-by: Christophe Ricard <christophe-h.ricard@st.com> Signed-off-by: Jagan Teki <jteki@openedev.com> [Set priv->wordlen, Add Kconfig entry and file credit for dm conversion] Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com>
* spi: omap3: Make local functions as staticJagan Teki2016-03-14-6/+6
| | | | | | | | | Attach static on local defined functions. Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com>
* spi: omap3: Move headers code inside the driverJagan Teki2016-03-14-111/+86
| | | | | | | | | | | | Header file have macro's and register definition and some unneeded function proto types which becomes tunned further in future patches and entire driver code resides in one file for more readability. Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com> [Fixes on code styles, Remove omap3_spi_txrx|write|read in header] Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com>
* dm: ti_qspi: Fix conversion of address to a pointerLokesh Vutla2016-03-12-3/+7
| | | | | | | | | | | | | | TI QSPI driver directly typecasts fdt_addr_t to a pointer. This is not strictly correct, as it gives a build warning when fdt_addr_t is u64. So, use map_physmem for a proper typecasts. This is inspired by commit 167efe01bc5a9 ("dm: ns16550: Use an address instead of a pointer for the uart base") Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* spi: spi-uclass: Set slave wordlen with SPI_DEFAULT_WORDLENChristophe Ricard2016-02-23-0/+1
| | | | | | | | In some case wordlen may not be set. Use SPI_DEFAULT_WORDLEN as default. Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com>
* spi: omap3: Remove unused variable irqstatus in omap3_spi_txrxChristophe Ricard2016-02-23-2/+0
| | | | | | | | Remove unused variable irqstatus in omap3_spi_txrx Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com>
* spi: ti_qspi: compile out spi_flash_copy_mmap when CONFIG_DMA is definedMugunthan V N2016-02-23-1/+1
| | | | | | | | | | When CONFIG_DMA is defined the default spi_flash_copy_mmap() can handle dma memory copy, so compile out spi_flash_copy_mmap() from ti_qspi driver when CONFIG_DMA config is defined. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com>
* dm: pch: Rename get_sbase op to get_spi_baseBin Meng2016-02-05-1/+1
| | | | | | | | Spell out 'sbase' to 'spi_base' so that it looks clearer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* spi: ich: Change PCHV_ to ICHV_Bin Meng2016-02-05-8/+13
| | | | | | | | | | | The ICH SPI controller supports two variants, one of which is ICH7 compatible and the other is ICH9 compatible. Change 'pch_version' to 'ich_version' to better match its original name. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com> Tested-by: Simon Glass <sjg@chromium.org>
* spi: ich: Use compatible strings to distinguish controller versionBin Meng2016-02-05-4/+24
| | | | | | | | | | At present ich spi driver gets the controller version information via pch, but this can be simply retrieved via spi node's compatible string. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com> Tested-by: Simon Glass <sjg@chromium.org>
* spi: ich: Some clean upBin Meng2016-02-05-47/+47
| | | | | | | | | | | | This cleans up the ich spi driver a little bit: - Remove struct ich_spi_slave that is not referenced anywhere - Remove ending period in some comments - Move struct ich_spi_platdata and struct ich_spi_priv to ich.h - Add #ifndef _ICH_H_ .. in ich.h Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-01-27-10/+10
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| * spi: fsl_qspi: Fix qspi_op_rdsr memcpy issueGong Qianyu2016-01-27-3/+3
| | | | | | | | | | | | | | | | | | | | In current driver, we always copy 4 bytes to the dest memory. Actually the dest memory may be shorter than 4 bytes. Add an argument to indicate the dest memory length. Avoid writing memory outside of the bounds. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * spi: fsl_qspi: Fix qspi_op_rdid memcpy issueGong Qianyu2016-01-27-6/+6
| | | | | | | | | | | | | | | | | | | | | | In current driver everytime we memcpy 4 bytes to the dest memory regardless of the remaining length. This patch adds checking the remaining length before memcpy. If the length is shorter than 4 bytes, memcpy the actual length of data to the dest memory. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * spi: fsl_qspi: fix compile warning for 64-bit platformGong Qianyu2016-01-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the following compile warning: drivers/spi/fsl_qspi.c: In function 'fsl_qspi_probe': drivers/spi/fsl_qspi.c:937:15: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] priv->regs = (struct fsl_qspi_regs *)plat->reg_base; ^ Just make the cast explicit. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | dm: x86: spi: Convert ICH SPI driver to driver model PCI APISimon Glass2016-01-24-116/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present this SPI driver works by searching the PCI buses for its peripheral. It also uses the legacy PCI API. In addition the driver has code to determine the type of Intel PCH that is used (version 7 or version 9). Now that we have proper PCH drivers we can use those to obtain the information we need. While the device tree has a node for the SPI peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the LPC device. Update the device tree files to show the SPI controller within the PCH, so that PCI access works as expected. This patch includes Bin's fix-up patch from here: https://patchwork.ozlabs.org/patch/569478/ Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* | spi: ich: Separate out the read/write trace from normal debuggingSimon Glass2016-01-24-9/+15
|/ | | | | | | | | The trace is seldom useful for basic debugging. Allow it to be enabled separately so that it is easier to see the more important init and error debug messages. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* rockchip: spi: Remove the explicit pinctrl settingSimon Glass2016-01-21-26/+2
| | | | | | | | The correct pinctrl is handled automatically so we don't need to do it in the driver. The exception is when we want to use a different chip select (other than 0). But this isn't used at present. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: spi: Correct chip-enable codeSimon Glass2016-01-21-1/+6
| | | | | | | | At present there is an incorrect call to rkspi_enable_chip(). It should be disabling the chip, not enabling it. Correct this and ensure that the chip is disabled when releasing the bus. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: spi: Implement the delaysSimon Glass2016-01-21-4/+23
| | | | | | | | Some devices need delays before and after activiation. Implement these features in the SPI driver so that we will be able to enable the Chrome OS EC. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: spi: Correct the bus init codeSimon Glass2016-01-21-2/+2
| | | | | | | Two of the init values are created locally so cannot be out of range. The masking is unnecessary and in one case is incorrect. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: spi: Remember the last speed to avoid re-setting itSimon Glass2016-01-21-1/+4
| | | | | | | Rather than changing the clock to the same value on every transaction, remember the last value and don't adjust the clock unless it is necessary. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: spi: Avoid setting the pinctrl twiceSimon Glass2016-01-21-3/+6
| | | | | | | | If full pinctrl is enabled we don't need to manually set the pinctrl in the driver. It will happen automatically. Adjust the code to suit - we will still use manual mode in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: spi: Update the driver to use the new clock IDSimon Glass2016-01-21-15/+17
| | | | | | We can use the new clk_get_by_index() function to get the correct clock. Signed-off-by: Simon Glass <sjg@chromium.org>
* spi: ti_qspi: Use 4-byte opcode for mmap readVignesh R2016-01-20-3/+3
| | | | | | | | | | | | ti-qspi driver currently uses 3-byte addressing mode(and opcodes) for memory-mapped read. This restricts maximum addressable flash size to 16MB. Enable the 4-byte addressing(and use 4-byte opcode) for memory-mapped read to allow access to addresses above 16MB. Signed-off-by: Ravi Babu <ravibabu@ti.com> [vigneshr@ti.com: Re-word commit description] Signed-off-by: Vignesh R <vigneshr@ti.com>
* spi: rk_spi: Fix debug format warningTom Rini2016-01-19-1/+1
| | | | | | | We need to use %lx not %x to describe a fdt_addr_t Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* Add more SPDX-License-Identifier tagsTom Rini2016-01-19-58/+4
| | | | | | | | | In a number of places we had wordings of the GPL (or LGPL in a few cases) license text that were split in such a way that it wasn't caught previously. Convert all of these to the correct SPDX-License-Identifier tag. Signed-off-by: Tom Rini <trini@konsulko.com>
* spi: kirkwood_spi.c: Add driver model supportStefan Roese2016-01-14-63/+159
| | | | | | | | | | | | | This patch adds driver model support to the kirkwood SPI driver. Which is also used on the MVEBU SoC's, now being converted to DM. Non-DM support is still available for the "older" platforms using this driver, like kirkwood. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Valentin Longchamp <valentin.longchamp@keymile.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org>
* spi: kirkwood_spi.c: Prepare for driver model supportStefan Roese2016-01-14-13/+28
| | | | | | | | | | | This patch prepares the Kirkwood SPI driver, also used on the MVEBU board (Armada XP / 38x), for the conversion to driver model. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Valentin Longchamp <valentin.longchamp@keymile.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org>
* drivers: spi: ti_qspi: convert driver to adopt device driver modelMugunthan V N2016-01-13-0/+187
| | | | | | | | | adopt ti_qspi driver to device driver model Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* spi: Add support for dual and quad modeMugunthan V N2016-01-13-1/+37
| | | | | | | | | | spi bus can support dual and quad wire data transfers for tx and rx. So defining dual and quad modes for both tx and rx. Also add support to parse bus width used for spi tx and rx transfers. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* drivers: spi: ti_qspi: prepare driver for DM conversionMugunthan V N2016-01-13-126/+153
| | | | | | | Prepare driver for DM conversion. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* drivers: spi:ti_qspi: change ti_qspi_slave to ti_qspi_priv for driver model ↵Mugunthan V N2016-01-13-60/+60
| | | | | | | | | | | | conversion Changing the ti_qspi_priv structure and its instance names from to priv for driver mode conversion. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* drivers: spi: ti_qspi: do not hard code chip select for memory map configurationMugunthan V N2016-01-13-2/+2
| | | | | | | | | | | | To enable memory map in dra7xx, specific chip select must be written to control module register. But this hard coded to chip select 1, fixing it by writing the specific chip select value to control module register. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* spi: Rename op_mode_rx to mode_rxJagan Teki2016-01-13-2/+2
| | | | | | | | | | | | | | Since spi rx mode macro's are renamed to simple and meaninfull, this patch will rename the respective structure members. Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Tested-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: Rename SPI_OPM_RX_* to SPI_RX_*Jagan Teki2016-01-13-2/+2
| | | | | | | | | | | | | | | | SPI_OPM_RX_AS - SPI_RX_SLOW SPI_OPM_RX_AF - SPI_RX_FAST SPI_OPM_RX_DOUT - SPI_RX_DUAL SPI_OPM_RX_QOF - SPI_RX_QUAD Cc: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: Rename SPI_TX_BP|QPP to SPI_TX_BYTE|QUADJagan Teki2016-01-13-1/+1
| | | | | | | | | | | | | | Since SPI_TX_* are spi_slave{} members so use spi protocol notation instead spi flash programming, like SPI_TX_BP => SPI_TX_BYTE SPI_TX_QPP => SPI_TX_QUAD Cc: Simon Glass <sjg@chromium.org> Tested-by: Jagan Teki <jteki@openedev.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: Use mode instead of op_mode_txJagan Teki2016-01-13-1/+1
| | | | | | | | | | Used mode member from spi_slave{} instead of op_mode_tx. Cc: Simon Glass <sjg@chromium.org> Tested-by: Jagan Teki <jteki@openedev.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: fsl_qspi: fix an error of using GENMASKGong Qianyu2016-01-07-1/+1
| | | | | | | | | This commit fixes the change of below commit "spi: fsl_qspi: Use GENMASK" (sha1 :bad490a24212c068c5b718b9189f47ea4075d078) Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* spi: zynq_qspi: Add configuration to disable LQSPI featureNathan Rossi2015-12-18-0/+9
| | | | | | | | | | | | | | | | When the Zynq Boot ROM code loads the payload from QSPI it uses the LQSPI feature of the QSPI device, however it does not clean up its configuration before handing over to the payload which leaves the device confgured to by-pass the standard non-linear operating mode. This ensures the Linear QSPI mode is disabled before re-enabling the device. Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Cc: Jagan Teki <jteki@openedev.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* fsl_qspi: Pet the watchdog while reading/writingAlexander Stein2015-12-15-0/+5
| | | | | | | | | When reading a large blob. e.g. a linux kernel (several MiBs) a watchdog timeout might occur meanwhile. So pet the watchdog while operating on the flash. Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com> Reviewed-by: York Sun <yorksun@freescale.com>
* spi: xilinx: Add new compatible stringsMichal Simek2015-12-11-1/+2
| | | | | | | | | Add xlnx,xps-spi-2.00.a/b which is compatible string listed in the Linux kernel. Remove origin one which has no real background. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* spi: Kconfig: Fix correct target name for ZynqMPMichal Simek2015-12-11-1/+1
| | | | | | | | ZynqMP is using different symbol. Use correct one. Reviewed-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* spi: zynq_spi: Add cadence compatible stringMichal Simek2015-12-11-0/+1
| | | | | | | Extend compatible list table for cdns,spi-r1p6 compatible string. Reviewed-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* spi: ti_qspi: Fix SPI_3WIRE checking using modeJagan Teki2015-12-11-1/+1
| | | | | | | | | SPI_3WIRE is spi mode not spi flags, so this patch fixed the spi-3wire checking throgh mode instead of flags. Cc: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: Get spi-3wire from dtsJagan Teki2015-12-11-0/+2
| | | | | | | | | spi-3wire is used when SI/SO signals shared so get the same from dts node and assign to mode on slave plat->mode. Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
* Move console definitions into a new console.h fileSimon Glass2015-11-19-0/+4
| | | | | | | | The console includes a global variable and several functions that are only used by a small subset of U-Boot files. Before adding more functions, move the definitions into their own header file. Signed-off-by: Simon Glass <sjg@chromium.org>
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