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| * dm: spi: Correct handling of SPI chip selects in sandboxSimon Glass2014-11-22-10/+1
| | | | | | | | | | | | | | | | | | This code was not updated when the chip select handling was adjusted. Fix it to call the correct function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Acked-by: Heiko Schocher <hs@denx.de>
* | linux/kernel.h: sync min, max, min3, max3 macros with LinuxMasahiro Yamada2014-11-23-4/+4
|/ | | | | | | | | | | | | | | | | | | | U-Boot has never cared about the type when we get max/min of two values, but Linux Kernel does. This commit gets min, max, min3, max3 macros synced with the kernel introducing type checks. Many of references of those macros must be fixed to suppress warnings. We have two options: - Use min, max, min3, max3 only when the arguments have the same type (or add casts to the arguments) - Use min_t/max_t instead with the appropriate type for the first argument Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Pavel Machek <pavel@denx.de> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [trini: Fixup arch/blackfin/lib/string.c] Signed-off-by: Tom Rini <trini@ti.com>
* spi, atmel: move CONFIG_SYS_SPI_WRITE_TOUT into common headerHeiko Schocher2014-11-17-0/+4
| | | | | | | | | | | | move CONFIG_SYS_SPI_WRITE_TOUT into drivers/spi/atmel_spi.h and define a default value. Delete this define in the board config files, where it is possible (all boards use currently the same value). Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* SPI: mxc_spi: delay initialisation until claim busMarkus Niebel2014-10-27-16/+21
| | | | | | | | | it is not correct to init for a specific slave in spi_setup_slave. instead buffer the values and delay init until spi_claim_bus. Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com> Acked-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* SPI: mxc_spi: remove second reset from ECSPI config handlerMarkus Niebel2014-10-27-3/+0
| | | | | | | | | | | | the second reset prevents other registers to be written. This will prevent to have the correct signal levels for SCLK before writing to the config reg in spi_xchg_single. Tested with GPIO based chipselect and SPI_MODE_3 on i.MX6S Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com> Acked-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: altera: Move the config options to the topMarek Vasut2014-10-27-8/+8
| | | | | | | | | | | | | Just move the configuration options scattered all over the driver to the top of the source file. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: altera: Clean up the use of variable dMarek Vasut2014-10-27-10/+13
| | | | | | | | | | | | | | | | The variable d is used in rather questionable way. Rework the code a bit so it's clearer what it does. Also, rename the variable from d to data to make it's name less mysterious. Finally, change it's data type to uint32_t , since it's accessed as a 32bit number. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: altera: Zap endless loopMarek Vasut2014-10-27-2/+11
| | | | | | | | | | | | | | | The driver contained an endless loop when waiting for TX completion, this is a bad idea since if the hardware fails, the loop might spin forever. Add timeout and handle it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: altera: Clean up most checkpatch issuesMarek Vasut2014-10-27-10/+13
| | | | | | | | | | | | | | | | | This patch just zaps most of the checkpatch cries present in the driver. There is one more left, which will be addressed separately. There is no functional change. This patch also adds a bunch of newlines all around the place, this is to make the code much more readable. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: altera: Clean up bit definitionsMarek Vasut2014-10-27-13/+13
| | | | | | | | | | | | | | Clean up the definitions of bits in the Altera SPI driver, there is no need to put braces around numbers afterall. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: altera: Use struct-based register accessMarek Vasut2014-10-27-24/+25
| | | | | | | | | | | | | | | | Zap the offset-based register access and use the struct-based one as this is the preferred method. No functional change, but there are some line-over-80 problems in the driver, which will be addressed later. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-imxTom Rini2014-10-27-0/+1
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| * ARM: i.MX: provide declaration for board_spi_cs_gpioEric Nelson2014-10-21-0/+1
| | | | | | | | | | | | | | | | Provide a public declaration of the board_spi_cs_gpio() callback for i.MX SPI chip selects to prevent the warning "Should it be static?" when compiling with "make C=1". Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* | dm: add entries to KconfigMasahiro Yamada2014-10-23-0/+6
| | | | | | | | | | | | | | | | Create entries of CONFIG_DM, CONFIG_DM_SERIAL, CONFIG_DM_GPIO and CONFIG_DM_SPI. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* | spi: kirkwood_spi.c: Change KW_SPI_BASE to MVEBU_SPI_BASEStefan Roese2014-10-23-1/+2
| | | | | | | | | | | | | | | | | | | | This makes is possible to use this SPI driver from other MVEBU SoC's as well. As the upcoming Armada XP support will do. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Tested-by: Luka Perkov <luka@openwrt.org> Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
* | spi: kirkwood_spi.c: Compile MPP (pin-mux) only for kirkwood SoC'sStefan Roese2014-10-23-0/+10
| | | | | | | | | | | | | | | | | | | | Compile the pin multiplexing only on Kirkwood platforms. As the Armada XP doesn't need it. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Tested-by: Luka Perkov <luka@openwrt.org> Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
* | arm: marvell: Move arch-kirkwood/spi.h to arch-mvebu/spi.hStefan Roese2014-10-23-1/+1
| | | | | | | | | | | | | | | | | | | | | | This move makes it possible to use this kirkwood SPI driver from other MVEBU platforms as well. This will be used by the upcoming Armada XP support. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Tested-by: Luka Perkov <luka@openwrt.org> Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
* | arm: marvell: Move arch/kirkwood.h to arch/soc.hStefan Roese2014-10-23-1/+1
| | | | | | | | | | | | | | | | | | This move makes is possible to use this header not only from kirkwood platforms but from all Marvell mvebu platforms. Signed-off-by: Stefan Roese <sr@denx.de> Tested-by: Luka Perkov <luka@openwrt.org> Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
* | dm: tegra: spi: Convert to driver modelSimon Glass2014-10-22-534/+392
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This converts the Tegra SPI drivers to use driver model. This is tested on: - Tegra20 - trimslice - Tegra30 - beaver - Tegra124 - dalmore (not tested on Tegra124) Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: exynos: Convert SPI to driver modelSimon Glass2014-10-22-333/+180
| | | | | | | | | | | | | | | | | | | | Move the exynos SPI driver over to driver model. This removes quite a bit of boilerplate from the driver, although it adds some for driver model. A few device tree additions are needed to make the SPI flash available. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | dm: spi: Add soft_spi implementationSimon Glass2014-10-22-0/+253
| | | | | | | | | | | | | | | | Add a new implementation of soft_spi that uses device tree to specify the GPIOs. This will replace soft_spi_legacy for boards which use driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | dm: spi: Remove SPI_INIT featureSimon Glass2014-10-22-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | This feature provides for init of a single SPI port for the soft SPI feature. It is not really compatible with driver model since it assumes a single SPI port. Also, inserting SPI init into the driver by means of a #define is not very nice. This feature is not used by any active boards, so let's remove it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | dm: spi: Rename soft_spi.c to soft_spi_legacy.cSimon Glass2014-10-22-1/+1
| | | | | | | | | | | | | | | | Reserve the 'normal' name for use by driver model, and rename the old driver so that it is clear that it is for 'legacy' drivers only. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | dm: sandbox: spi: Move to driver modelSimon Glass2014-10-22-126/+74
| | | | | | | | | | | | | | | | Adjust the sandbox SPI driver to support driver model and move sandbox over to driver model for SPI. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | dm: sandbox: Add a SPI emulation uclassSimon Glass2014-10-22-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot includes a SPI emulation driver already but it is not explicit, and is hidden in the SPI flash code. Conceptually with sandbox's SPI implementation we have a layer which creates SPI bus transitions and a layer which interprets them, currently only for SPI flash. The latter is actually an emulation, and it should be possible to add more than one emulation - not just SPI flash. Add a SPI emulation uclass so that other emulations can be plugged in to support different types of emulated devices on difference buses/chip selects. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | dm: spi: Add a uclass for SPISimon Glass2014-10-22-0/+394
|/ | | | | | | | | | | | | | | | Add a uclass which provides access to SPI buses and includes operations required by SPI. For a time driver model will need to co-exist with the legacy SPI interface so some parts of the header file are changed depending on which is in use. The exports are adjusted also since some functions are not available with driver model. Boards must define CONFIG_DM_SPI to use driver model for SPI. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> (Discussed some follow-up comments which will address in future add-ons)
* kconfig: add blank Kconfig filesMasahiro Yamada2014-09-24-0/+0
| | | | | | | | This would be useful to start moving various config options. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* spi: kirkwood_spi.c: cosmetic: Fix minor coding style issuesStefan Roese2014-09-24-8/+6
| | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Cc: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Tested-by: Luka Perkov <luka@openwrt.org> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* spi: kirkwood_spi.c: Make global variable staticStefan Roese2014-09-24-1/+1
| | | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Tested-by: Luka Perkov <luka@openwrt.org> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* spi: kirkwood_spi.c: Some fixes and cleanupStefan Roese2014-09-24-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces the clrsetbits_le32() accessor functions in the kirkwood SPI driver. Note that it also includes a fix: - writel(~KWSPI_CSN_ACT | KWSPI_SMEMRDY, &spireg->ctrl); + writel(KWSPI_SMEMRDY, &spireg->ctrl); Here the bit KWSPI_CSN_ACT (0x1) should have been cleared. Instead 0xfffffffe is written into this control register. This is the main reason to use the clrsetbits() functions now. As they make clearing bits much less error prone. Additionally KWSPI_IRQUNMASK is not used in spi_cs_activate() and spi_cs_deactivate() any more. Its the wrong macro but has the same value as the correct one (KWSPI_CSN_ACT). This is in preparation for use of this driver on the Marvell Armada XP platform as well. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Tested-by: Luka Perkov <luka@openwrt.org> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* spi: mxc: fix sf probe when using mxc_spiNikita Kiryanov2014-09-24-23/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MXC SPI driver has a feature whereas a GPIO line can be used to force CS high across multiple transactions. This is set up by embedding the GPIO information in the CS value: cs = (cs | gpio << 8) This merge of cs and gpio data into one value breaks the sf probe command: if the use of gpio is required, invoking "sf probe <cs>" will not work, because the CS argument doesn't have the GPIO information in it. Instead, the user must use "sf probe <cs | gpio << 8>". For example, if bank 2 gpio 30 is used to force cs high on cs 0, bus 0, then instead of typing "sf probe 0" the user now must type "sf probe 15872". This is inconsistent with the description of the sf probe command, and forces the user to be aware of implementaiton details. Fix this by introducing a new board function: board_spi_cs_gpio(), which will accept a naked CS value, and provide the driver with the relevant GPIO, if one is necessary. Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Eric Benard <eric@eukrea.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* spi, spi_mxc: do not hang in spi_xchg_singleHeiko Schocher2014-08-06-2/+15
| | | | | | | | | if status register do never set MXC_CSPICTRL_TC, spi_xchg_single endless loops. Add a timeout here to prevent endless hang. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Dirk Behme <dirk.behme@gmail.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* spi: Support half-duplex mode in FDT decodeSimon Glass2014-08-06-0/+2
| | | | | | | | This parameter should also be supported. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* exynos: spi: Fix calculation of SPI transaction start timeSimon Glass2014-08-06-4/+5
| | | | | | | | | | The SPI transaction delay is supposed to be measured from the end of one transaction to the start of the next. The code does not work that way, so fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* arm: ep9315: Return back Cirrus Logic EDB9315A board supportSergey Kostanbaev2014-07-04-0/+275
| | | | | | | This patch returns back support for old ep93xx processors family Signed-off-by: Sergey Kostanbaev <sergey.kostanbaev@gmail.com> Cc: albert.u.boot@aribaud.net
* Merge remote-tracking branch 'u-boot-samsung/master'Albert ARIBAUD2014-07-01-1/+4
|\ | | | | | | | | | | | | | | Conflicts: boards.cfg Conflict was trivial between goni maintainer change and lager_nor removal.
| * Exynos: SPI: Fix reading data from SPI flashAkshay Saraswat2014-06-23-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPI recieve and transfer code in exynos_spi driver has a logical bug. We read data in a variable which can hold an integer. Then we assign this integer 32 bit value to another variable which has data type uchar. Latter represents a unit of our recieve buffer. Everytime when we write a value to our recieve buffer we step ahead by 4 units when actually we wrote to one unit. This results in the loss of 3 bytes out of every 4 bytes recieved. This patch intends to fix this bug. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2014-07-01-1/+1
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| * | spi: davinci: Fix register address for SPI1_BUSAxel Lin2014-06-19-1/+1
| |/ | | | | | | | | | | Fix a trivial copy-paste bug. Signed-off-by: Axel Lin <axel.lin@ingics.com>
* | Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2014-06-25-38/+118
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| * Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2014-06-11-6/+12
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| | * spi: soft_spi: Support NULL din/dout buffersAndrew Ruder2014-06-08-6/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This mirrors the conventions used in other SPI drivers (kirkwood, davinci, atmel, et al) where the din/dout buffer can be NULL when the received/transmitted data isn't important. This reduces the need for allocating additional buffers when write-only/read-only functionality is needed. In the din == NULL case, the received data is simply not stored. In the dout == NULL case, zeroes are transmitted. Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com> Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-06-08-0/+1
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| * | powerpc/espi: remove 80us delay to improve transfer performanceHou Zhiqiang2014-06-05-32/+106
| | | | | | | | | | | | | | | | | | | | | Replace 80 mircoseconds delay with polling flag ESPI_EV_TXE. Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | arm: vf610: Add QSPI driver supportAlison Wang2014-06-09-0/+610
| |/ |/| | | | | | | | | | | Add Freescale QSPI driver support for VF610. Signed-off-by: Alison Wang <Huan.Wang@freescale.com> Signed-off-by: Chao Fu <b44548@freescale.com>
* | ti: qspi: populate slave device to set flash quad bit.Sourav Poddar2014-06-06-0/+1
|/ | | | | | | The patch populates the slave data which will be used by flash driver to set the flash quad enable bit. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
* Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2014-04-21-3/+82
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| * spi: davinci: add support for multiple bus and chip selectKaricheri, Muralidharan2014-04-17-3/+79
| | | | | | | | | | | | | | | | | | | | | | | | Currently davinci spi driver supports only bus 0 cs 0. This patch allows driver to support bus 1 and bus 2 with configurable number of chip selects. Also defaults are selected in a way to avoid regression on other platforms that uses davinci spi driver and has only one spi bus. Signed-off-by: Rex Chang <rchang@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * spi: ti_qspi: Add delay for successful bulk erase.Poddar, Sourav2014-04-17-0/+3
| | | | | | | | | | | | | | | | Bulk erase is not happening properly on dra7 due to erase timing constraints, add a delay so that erase timing constraints are properly met. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Yebio Mesfin <ymesfin@ti.com>
* | ARM: tegra: Tegra20 pinmux cleanupStephen Warren2014-04-17-3/+3
|/ | | | | | | | | | | | | | This renames all the Tegra20 pinmux pins and functions so they have a prefix which matches the type name. The entries in tegra20_pingroups[] are all updated to remove the columns which are no longer used. All affected code is updated to match. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
generated by cgit v1.1 at 2024-12-21 12:29:58 +0000