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* OMAP3: SPI driverDirk Behme2010-12-11-0/+470
| | | | | | CC: Ruslan N. Araslanov <byaaka@yandex.ru> Signed-off-by: Ruslan Araslanov <ruslan.araslanov@vitecmm.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* Switch from archive libraries to partial linkingSebastien Carlier2010-11-17-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, weak symbols were not overridden by non-weak symbols found in archive libraries when linking with recent versions of binutils. As stated in the System V ABI, "the link editor does not extract archive members to resolve undefined weak symbols". This commit changes all Makefiles to use partial linking (ld -r) instead of creating library archives, which forces all symbols to participate in linking, allowing non-weak symbols to override weak symbols as intended. This approach is also used by Linux, from which the gmake function cmd_link_o_target (defined in config.mk and used in all Makefiles) is inspired. The name of each former library archive is preserved except for extensions which change from ".a" to ".o". This commit updates references accordingly where needed, in particular in some linker scripts. This commit reveals board configurations that exclude some features but include source files that depend these disabled features in the build, resulting in undefined symbols. Known such cases include: - disabling CMD_NET but not CMD_NFS; - enabling CONFIG_OF_LIBFDT but not CONFIG_QE. Signed-off-by: Sebastien Carlier <sebastien.carlier@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-imxWolfgang Denk2010-10-11-48/+120
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| * MXC: Fix byte-ordering in SPI driver for i.MX31/i.MX51Stefano Babic2010-09-30-38/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The actual SPI driver for i.MX31 and i.MX51 controller use a wrong byte ordering, because it is supposed to work only with Freescale's devices, as the Power Controllers (PMIC). The driver is not suitable for general purposes, because the buffers passed to spi_xfer must be 32-bit aligned, as it is used mainly to send integer to PMIC devices. The patch drops any kind of limitation and makes the driver useful with devices controlled sending commands composed by single bytes (or by a odd number of bytes), such as spi flash, sensor, etc. Because the byte ordering is changed, any current driver using this controller must be adapted, too. Signed-off-by: Stefano Babic <sbabic@denx.de>
| * MXC: Correct SPI_CPOL setting in SPI driverStefano Babic2010-09-30-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The handling of the SPI_CPOL bit inside the SPI driver was wrong. As reported by the manual, the meaning of the SSPOL inside the configuration register is the same as reported by SPI specification (0 if low in idle, 1 is high on idle). The driver inverts this logic. Because this patch sets the logic as specified, it is required to clear the CPOL bit in the configuration file to adapt to the correct logic. Signed-off-by: Stefano Babic <sbabic@denx.de> Signed-off-by: David Jander <david.jander@protonic.nl>
| * Use common function to set GPIOs for MX3 and MX5Stefano Babic2010-09-29-8/+7
| | | | | | | | | | | | | | | | | | The patch adds support for setting gpios to the MX51 processor and change name to the corresponding functions for MX31. In this way, it is possible to get rid of nasty #ifdef switches related to the processor type. Signed-off-by: Stefano Babic <sbabic@denx.de>
* | Blackfin: bfin_spi: add optional DMA supportMike Frysinger2010-10-02-27/+128
|/ | | | | | | | This moves the last piece from the old spi_flash driver to the new SPI framework -- optional DMA RX support. This typically cuts speeds by ~40% at the cost of additional ~300 bytes. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: bfin_spi: use same gpio cs define as LinuxMike Frysinger2010-09-21-2/+0
| | | | | | | | Linux uses an offset of 8 to switch from hardware cs to a gpio cs, so have u-boot use the same value. Also make sure it is public for boards to access. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* AT91/AVR32: atmel_spi.c: flush RDR before next SPI transactionReinhard Meyer2010-09-03-2/+11
| | | | Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
* Merge branch 'master' of ../masterWolfgang Denk2010-07-15-186/+106
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| * Blackfin: bfin_spi: support gpios as chip selectsMike Frysinger2010-07-13-28/+57
| | | | | | | | | | | | | | Rather than only support the pins dedicated as chip selects, utilize the gpio framework to support any gpio pin. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: bfin_spi: convert to portmux frameworkMike Frysinger2010-07-13-159/+50
| | | | | | | | | | | | | | Rather than bang MMRs directly, use the new portmux framework to handle the details. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Davinci: SPI: add the missing v2 patch changesNick Thompson2010-07-05-2/+6
|/ | | | | | | | | | Two Indentation fixes. Catch requests for full-duplex transfers when driver configured for half-duplex operation only. Signed-off-by: Nick Thompson <nick.thompson@ge.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* Davinci: SPI performance enhancementsNick Thompson2010-06-22-67/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | | The following restructuring and optimisations increase the SPI read performance from 1.3MiB/s (on da850) to 2.87MiB/s (on da830): Remove continual revaluation of driver state from the core of the copy loop. State can not change during the copy loop, so it is possible to move these evaluations to before the copy loop. Cost is more code space as loop variants are required for each set of possible configurations. The loops are simpler however, so the extra is only 128bytes on da830 with CONFIG_SPI_HALF_DUPLEX defined. Unrolling the first copy loop iteration allows the TX buffer to be pre-loaded reducing SPI clock starvation. Unrolling the last copy loop iteration removes testing for the final loop iteration every time round the loop. Using the RX buffer empty flag as a transfer throttle allows the assumption that it is always safe to write to the TX buffer, so polling of TX buffer full flag can be removed. Signed-off-by: Nick Thompson <nick.thompson@ge.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2010-06-17-34/+43
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| * DaVinci: Improve DaVinci SPI speed.Delio Brignoli2010-06-08-34/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I have updated this patch based on the comments [1] by Wolfgang Denk and removed unused variables. [1][http://lists.denx.de/pipermail/u-boot/2010-May/071728.html] Reduce the number of reads per byte transferred on the BUF register from 2 to 1 and take advantage of the TX buffer in the SPI module. On LogicPD OMAP-L138 EVM, SPI read throughput goes up from ~0.8Mbyte/s to ~1.3Mbyte/s. Tested with a 2Mbyte image file. Remove unused variables in the spi_xfer() function. Signed-off-by: Delio Brignoli <dbrignoli@audioscience.com> Tested-by: Ben Gardiner <bengardiner@nanometrics.ca> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | spi: add altera spi controller supportThomas Chou2010-05-28-0/+166
|/ | | | | | | | | | | | | This patch adds the driver of altera spi controller, which is used as epcs/spi flash controller. It also works with mmc_spi driver. This driver support more than one spi bus, with base list declared #define CONFIG_SYS_ALTERA_SPI_LIST { BASE_0,BASE_1,... } Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Tested-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
* SPI: added support for MX51 to mxc_spiStefano Babic2010-05-05-20/+211
| | | | | | This patch add SPI support for the MX51 processor. Signed-off-by: Stefano Babic <sbabic@denx.de>
* Move arch/ppc to arch/powerpcStefan Roese2010-04-21-1/+1
| | | | | | | | | | | | | | | | | As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de>
* ppc: Move cpu/$CPU to arch/ppc/cpu/$CPUPeter Tyser2010-04-13-1/+1
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* Prepare v2010.03-rc1v2010.03-rc1Wolfgang Denk2010-03-12-1/+0
| | | | | | Coding style cleanup, update CHANGELOG. Signed-off-by: Wolfgang Denk <wd@denx.de>
* convert common files to new SoC accessJens Scharsig2010-02-12-0/+4
| | | | | | | | * add's a warning to all files, which need update to new SoC access * convert common files in cpu/../at91 and a lot of drivers to use c stucture SoC access Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
* SPI: Fix 32 bit transfers in mxc_spi.cMagnus Lilja2010-02-12-0/+9
| | | | | | | | | | | | | | Commit f9b6a1575d9f1ca192e4cb60e547aa66f08baa3f, "i.MX31: fix SPI driver for shorter than 32 bit" broke 32 bit transfers. This patch makes single 32 bit transfer work again. Transfer lengths that are known not to work will abort and print an error message. Tested on i.MX31 Litekit and i.MX31 PDK using 32 bit transfers to the MC13783/ATLAS chip (using the 'date' command). Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
* TI DaVinci: Driver for the davinci SPI controllerSekhar Nori2010-02-12-0/+325
| | | | | | | | | This adds a driver for the SPI controller found on davinci based SoCs from Texas Instruments. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* Blackfin: bfin_spi: round up clock dividerCliff Cai2010-01-17-1/+6
| | | | | | | | If the requested clock cannot be exactly obtained, round it up so that we err on the side of slightly slower rather than slightly faster. Signed-off-by: Cliff Cai <cliff.cai@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: bfin_spi: let boards control idle valueCliff Cai2010-01-17-1/+5
| | | | | | | Some SPI devices like to see high idle values rather than low. Signed-off-by: Cliff Cai <cliff.cai@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Add support for CS2 dataflash for Atmel-SPI.Remy Bohmer2009-11-23-2/+16
| | | | | | | The only missing chipselect line support is CS2, and I need it on CS2... Signed-off-by: Remy Bohmer <linux@bohmer.net>
* Coldfire: Consolidate DSPI driverTsiChung Liew2009-07-14-0/+358
| | | | | | | Unify both MCF5227x and MCF5445x DSPI driver in CPU to driver/spi folder for common use. Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2009-07-07-0/+186
|\ | | | | | | | | | | | | Conflicts: drivers/spi/Makefile Signed-off-by: Wolfgang Denk <wd@denx.de>
| * spi: Add Marvell Kirkwood SPI driverPrafulla Wadaskar2009-06-26-0/+186
| | | | | | | | | | | | This patch adds a SPI driver for the Marvell Kirkwood SoC's. Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
* | mpc52xx: Add SPI driver.Grzegorz Bernacki2009-06-14-0/+110
|/ | | | Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
* Blackfin: spi: fix pin handling of SPI0 SSEL4Mike Frysinger2009-05-29-1/+1
| | | | | | | CS4 on SPI0 has a dedicated PH8 pin which needs to be enabled as a peripheral in order to work. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* at91sam9/at91cap: improve clock frameworkJean-Christophe PLAGNIOL-VILLARD2009-04-16-3/+4
| | | | | | calculate dynamically the clock rate and pllb setting for usb Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Blackfin: spi: make cs deassert function deterministicTodor I Mollov2009-04-06-1/+15
| | | | | | | | | | | | | | | | | | | | | | Blackfin SPI driver was not driving the SPI chip-select high before putting the chip-select signals into tri-state mode. This is probably something that slipped by unnoticed in most designs. If the signals are put directly into a tri-state mode, then the board is relying on the pull-up resistors to pull up the chip-select before the next transaction. Most of the time this is fine, except when you have two transactions that follow each other very closely, such as the flash erase and read status register commands. In this case I was seeing a 500ns separation between the transactions. In my setup, with a 10kOhm pull-up, it would meet timing spec about half the time and resulted in intermittent errors. (A stronger pull up would fix this, but our design is targeted for low power consumption and a 3.3kOhm @ 3.3v is 3.3mW of needless power consumption.) I modified the spi_cs_deactivate() function in bfin_spi.c to drive the chip-selects high before putting them into tri-state. For me, this resulted in a rise time of 5ns instead of the previous rise time of about 1us, and fully satisfied the timing spec of the chip. Signed-off-by: Todor I Mollov <tmollov@ucsd.edu> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* at91: move dataflash spi driver to drivers/spiJean-Christophe PLAGNIOL-VILLARD2009-04-04-0/+158
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Blackfin: add BF538/BF539 SPI portmux handlingMike Frysinger2009-04-02-0/+18
| | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: spi: there is no PORTJ_FER MMR on BF537Sonic Zhang2009-03-23-5/+3
| | | | | | | | Since the PORTJ on the BF537 is peripheral-only (no GPIO functionality), then there is no PORTJ_FER register for us to worry about. Signed-off-by: Sonic Zhang <Sonic.Zhang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* i.MX31: support GPIO as a chip-select in the mxc_spi driverGuennadi Liakhovetski2009-02-24-8/+56
| | | | | | | | | Some SPI devices have special requirements on chip-select handling. With this patch we can use a GPIO as a chip-select and strictly follow the SPI_XFER_BEGIN and SPI_XFER_END flags. Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* i.MX31: fix SPI driver for shorter than 32 bitGuennadi Liakhovetski2009-02-24-11/+20
| | | | | | | | Fix setting the SPI Control register, 8 and 16-bit transfers and a wrong pointer in the free routine in the mxc_spi driver. Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Blackfin: add driver for on-chip SPI controllerMike Frysinger2009-02-02-0/+344
| | | | | | This fills out the SPI backend for the Blackfin on-chip SPI peripheral. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-7/+7
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* soft_spi: move to drivers/spiJean-Christophe PLAGNIOL-VILLARD2008-08-29-1/+195
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Move conditional compilation of MPC8XXX SPI driver to MakefileBen Warren2008-07-01-3/+1
| | | | Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* atmel_spi: Driver for the Atmel SPI controllerHans-Christian Egtvedt2008-06-03-0/+306
| | | | | | | | | | | | | | | This adds a driver for the SPI controller found on most AT91 and AVR32 chips, implementing the new SPI API. Changed in v4: - Update to new API - Handle zero-length transfers appropriately. The user may send a zero-length SPI transfer with SPI_XFER_END set in order to deactivate the chip select after a series of transfers with chip select active. This is useful e.g. when polling the status register of DataFlash. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
* SPI API improvementsHaavard Skinnemoen2008-06-03-38/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch gets rid of the spi_chipsel table and adds a handful of new functions that makes the SPI layer cleaner and more flexible. Instead of the spi_chipsel table, each board that wants to use SPI gets to implement three hooks: * spi_cs_activate(): Activates the chipselect for a given slave * spi_cs_deactivate(): Deactivates the chipselect for a given slave * spi_cs_is_valid(): Determines if the given bus/chipselect combination can be activated. Not all drivers may need those extra functions however. If that's the case, the board code may just leave them out (assuming they know what the driver needs) or rely on the linker to strip them out (assuming --gc-sections is being used.) To set up communication parameters for a given slave, the driver needs to call spi_setup_slave(). This returns a pointer to an opaque spi_slave struct which must be passed as a parameter to subsequent SPI calls. This struct can be freed by calling spi_free_slave(), but most driver probably don't want to do this. Before starting one or more SPI transfers, the driver must call spi_claim_bus() to gain exclusive access to the SPI bus and initialize the hardware. When all transfers are done, the driver must call spi_release_bus() to make the bus available to others, and possibly shut down the SPI controller hardware. spi_xfer() behaves mostly the same as before, but it now takes a spi_slave parameter instead of a spi_chipsel function pointer. It also got a new parameter, flags, which is used to specify chip select behaviour. This may be extended with other flags in the future. This patch has been build-tested on all powerpc and arm boards involved. I have not tested NIOS since I don't have a toolchain for it installed, so I expect some breakage there even though I've tried fixing up everything I could find by visual inspection. I have run-time tested this on AVR32 ATNGW100 using the atmel_spi and DataFlash drivers posted as a follow-up. I'd like some help testing other boards that use the existing SPI API. But most of all, I'd like some comments on the new API. Is this stuff usable for everyone? If not, why? Changed in v4: - Build fixes for various boards, drivers and commands - Provide common struct spi_slave definition that can be extended by drivers - Pass a struct spi_slave * to spi_cs_activate and spi_cs_deactivate - Make default bus and mode build-time configurable - Override default SPI bus ID and mode on mx32ads and imx31_litekit. Changed in v3: - Add opaque struct spi_slave for controller-specific data associated with a slave. - Add spi_claim_bus() and spi_release_bus() - Add spi_free_slave() - spi_setup() is now called spi_setup_slave() and returns a struct spi_slave - soft_spi now supports four SPI modes (CPOL|CPHA) - Add bus parameter to spi_setup_slave() - Convert the new i.MX32 SPI driver - Convert the new MC13783 RTC driver Changed in v2: - Convert the mpc8xxx_spi driver and the mpc8349emds board to the new API. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Tested-by: Guennadi Liakhovetski <lg@denx.de>
* Big white-space cleanup.Wolfgang Denk2008-05-21-1/+1
| | | | | | | | | | | This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de>
* New i.MX31 SPI driverGuennadi Liakhovetski2008-04-18-0/+167
| | | | | | | | | This is an SPI driver for i.MX and MXC based SoCs from Freescale. So far only implemented and tested on i.MX31, can with a modified register layout and definitions be used for i.MX27, I think, MXC CPUs have similar SPI controllers too. Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
* Fix conditional compilation of mpx8xxx_spi driverBen Warren2008-01-29-2/+2
| | | | | | | This driver should only compile if CONFIG_MPC8XXX_SPI is set Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* codingstyle cleanup for spi driverKim Phillips2008-01-17-29/+34
| | | | | | ..and rm unused CONFIG_FSL_SPI define Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Add support for a Freescale non-CPM SPI controllerBen Warren2008-01-17-0/+184
This patch adds support for the SPI controller found on Freescale PowerPC processors such as the MCP834x family. Additionally, a new config option, CONFIG_HARD_SPI, is added for general purpose SPI controller use. Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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