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* spi: Makefile: Use object file alphabetic orderJagan Teki2015-07-01-5/+5
| | | | | | | Use object files as incresing alphabetic order, so-that it's easy for readability. Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: Kconfig: Add TI_QSPI entryJagan Teki2015-07-01-0/+6
| | | | | | | Added TI_QSPI entry on Kconfig with help description. Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* spi: Kconfig: Add XILINX_SPI entryJagan Teki2015-07-01-0/+9
| | | | | | | Added XILINX_SPI entry on Kconfig with help description. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Michal Simek <michal.simek@xilinx.com>
* spi: Add Kconfig menu entryJagan Teki2015-07-01-0/+4
| | | | | | Added Kconfig menu ... endmenu enties for spi support. Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: Kconfig: Add Zynq SPI controller entryJagan Teki2015-07-01-0/+8
| | | | | | | | | | Add Zynq SPI controller Kconfig entry. Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Marek Vasut <marex@denx.de> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
* spi: xilinx_spi: Add asm/io.h include fileJagan Teki2015-07-01-0/+1
| | | | | | | | | | | | | This patch includes asm/io.h for readl and writel calls. build errors: drivers/spi/xilinx_spi.c: In function 'xilinx_spi_probe': drivers/spi/xilinx_spi.c:119:2: warning: implicit declaration of function 'writel' [-Wimplicit-function-declaration] drivers/spi/xilinx_spi.c: In function 'xilinx_spi_xfer': drivers/spi/xilinx_spi.c:193:2: warning: implicit declaration of function 'readl' [-Wimplicit-function-declaration] Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Michal Simek <michal.simek@xilinx.com>
* dm: spi: xilinx_spi: Convert to driver modelJagan Teki2015-07-01-88/+112
| | | | | | | | This converts the xilinx spi driver to use the driver model. Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com>
* spi: zynq_spi: Add fdt support in driverJagan Teki2015-07-01-10/+13
| | | | | | | | | | | | | | | | | Now zynq spi driver platform data is controlled by devicetree, enable the status by saying "okay" on respective board dts to use the devicetree generated platdata. Ex: &spi1 { status = "okay"; }; Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
* dm: spi: zynq_spi: Convert to driver modelJagan Teki2015-07-01-124/+169
| | | | | | | | | | | | | | | | This converts the zynq spi driver to use the driver model. Minimal functional changes like using meaningful name on structure members wrt mainlined dm spi drivers. - input_hz -> frequency - req_hz -> freq - base -> regs Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
* spi: davinci_spi: Driver cleanupJagan Teki2015-07-01-170/+173
| | | | | | | | | | Arrange driver code in more readable format[1] for easy accessing and readable. [1] http://patchwork.ozlabs.org/patch/265683/ Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Rex Chang <rchang@ti.com> Cc: Murali Karicheri <m-karicheri2@ti.com>
* spi: davinci_spi: Move header code to driverJagan Teki2015-07-01-122/+109
| | | | | | | | | Move the header code into driver for more readable and easy to access it. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Rex Chang <rchang@ti.com> Cc: Murali Karicheri <m-karicheri2@ti.com>
* spi: xilinx_spi: Driver clean-upJagan Teki2015-07-01-107/+57
| | | | | | | | | | | | | | - Zap unneeded macros - Re-arrange the code - Removed __attribute__((weak)) - Replace __func__ macro with func names to save macro transition. - Re-arranged comment lines. - Arrange driver code in more readable format[1] [1] http://patchwork.ozlabs.org/patch/265683/ Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
* spi: xilinx_spi: Move header code to driverJagan Teki2015-07-01-139/+112
| | | | | | | | Move the header code into driver for more readable and easy to access it. Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
* spi: Zap oc_tiny_spi driverJagan Teki2015-07-01-246/+0
| | | | | | | | Zap oc_tiny_spi driver since the boards used this driver is no longer been active. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Thomas Chou <thomas@wytron.com.tw>
* spi: Zap ftssp010_spi driverJagan Teki2015-07-01-499/+0
| | | | | | | | | Zap ftssp010_spi driver since the boards used this driver is no longer been active. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Kuo-Jung Su <dantesu@faraday-tech.com> Cc: Axel Lin <axel.lin@ingics.com>
* spi: Zap andes_spi driverJagan Teki2015-07-01-400/+0
| | | | | | | | Zap andes_spi driver since the boards used this driver is no longer been active. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Macpaul Lin <macpaul@andestech.com>
* tegra: spi: Support slow SPI ratesSimon Glass2015-06-09-3/+15
| | | | | | | | | Use the oscillator as the source clock when we cannot achieve a low-enough speed with the peripheral clock. This happens when we request 3MHz on a SPI clock, for example. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: spi: Drop the claim_bus() method to correct delaysSimon Glass2015-06-09-17/+9
| | | | | | | | | | | | | | | | At present the driver does not properly honour the requested SPI CS deactivation delay since the SPI bus is changed in the claim_bus() method. Everything the claim_bus() method does can be done when the device is probed (setting the speed and mode) and at the start of a new transfer (where the fifo_status is already cleared). So drop this method. Also, until the delay is complete, we should not touch the bus, so make sure that spi_cs_activate() is called before other things are done in the xfer() method. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* dm: spi: Avoid setting the speed with every transferSimon Glass2015-05-05-3/+6
| | | | | | | | Only set the speed if it has changed from last time. Since the speed will be 0 when the device is probed it will always be changed on the first transfer after the device is probed. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://www.denx.de/git/u-boot-socfpgaTom Rini2015-04-28-0/+16
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| * spi: Add Cadence QSPI controller Kconfig entryMarek Vasut2015-04-21-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Cadence QSPI controller Kconfig entry. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Acked-by: Pavel Machek <pavel@denx.de> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Vince Bridgers <vbridger@opensource.altera.com>
| * spi: Add Designware SPI controller Kconfig entryMarek Vasut2015-04-21-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add DWC SPI controller Kconfig entry. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Acked-by: Pavel Machek <pavel@denx.de> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Vince Bridgers <vbridger@opensource.altera.com>
* | spi: omap3: Fix timeout handlingDavid Dueck2015-04-27-8/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The timeout value is never reset during the transfer. This means that when transferring more data we eventually trigger the timeout. This was reported on the mailing list: "Spansion SPI flash read timeout with AM335x" Signed-off-by: David Dueck <davidcdueck@googlemail.com> CC: Tom Rini <trini@konsulko.com> CC: Stefan Roese <sr@denx.de> CC: Andy Pont <andy.pont@sdcsystems.com> Tested-by: David Dueck <davidcdueck@googlemail.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | dm: spi: Correct SPI claim/release_bus() methodsSimon Glass2015-04-23-7/+12
| | | | | | | | | | | | | | | | | | | | | | These methods should be passed a slave device, not a bus. This matches the old SPI interface. It is important to know which device is claiming the bus so passing a bus is not that useful. Reported-by: Haikun Wang <haikun.wang@freescale.com> Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | zynq: spi: Remove unnecessary error conditionSiva Durga Prasad Paladugu2015-04-22-3/+0
|/ | | | | | | | | | Removed the unnecessary error check from spi_xfer as the bitlen zero is possible now to deassert the chip select for which no data is required to be transfered. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* sandbox: Move CONFIG_SANDBOX_SPI to KconfigSimon Glass2015-04-18-0/+25
| | | | | | Move this over to Kconfig and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: spi: Convert Freescale QSPI driver to driver modelHaikun.Wang@freescale.com2015-04-18-329/+656
| | | | | | | | | Move the Freescale QSPI driver over to driver model. Signed-off-by: Haikun Wang <Haikun.Wang@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Tested-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: spi: Convert Freescale DSPI driver to driver modelHaikun.Wang@freescale.com2015-04-18-0/+738
| | | | | | | Move the Freescale DSPI driver over to driver model. Signed-off-by: Haikun Wang <Haikun.Wang@freescale.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: x86: spi: Convert ICH SPI driver to driver modelSimon Glass2015-04-18-254/+265
| | | | | | | | | | | | Convert this driver over to use driver model. Since all x86 platforms use it, move x86 to use driver model for SPI and SPI flash. Adjust all dependent code and remove the old x86 spi_init() function. Note that this does not make full use of the new PCI uclass as yet. We still scan the bus looking for the device. It should move to finding its details in the device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: core: Add dev_get_uclass_priv() to access uclass private dataSimon Glass2015-04-16-2/+2
| | | | | | | | Add a convenience function to access the private data that a uclass stores for each of its devices. Convert over most existing uses for consistency and to provide an example for others. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: spi: Add support for lynxpointSimon Glass2015-04-16-1/+2
| | | | | | | Add Lynxpoint to the driver so that the Asus Chromebox can be supported. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* lpc32xx: add LPC32xx SSP support (SPI mode)Albert ARIBAUD \(3ADEV\)2015-04-10-0/+145
| | | | | Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* spi: designware_spi: revisit FIFO size detection againAxel Lin2015-03-30-2/+2
| | | | | | | | | | | | | | | | By specification the FIFO size would be in a range 2-256 bytes. From TX Level prospective it means we can set threshold in the range 0-(FIFO size - 1) bytes. Hence there are currently two issues: a) FIFO size 2 bytes is actually skipped since TX Level is 1 bit and could be either 0 or 1 byte; b) FIFO size is incorrectly decreased by 1 which already done by meaning of TX Level register. Fixes: 501943696ea4 (spi: designware_spi: Fix detecting FIFO depth) Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: cf_spi: Staticize local functionsAxel Lin2015-03-30-13/+7
| | | | | | | Make local functions static and remove unneeded forward declarations. Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: cf_spi: Use to_cf_spi_slave to resolve cfslave from slaveAxel Lin2015-03-30-2/+9
| | | | | | | | Don't assume slave is always the first member of struct cf_spi_slave. Use container_of instead of casting first structure member. Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* qspi: dra7x: enable quad mode read for ti-qspi driverRavi Babu2015-03-30-0/+7
| | | | | | | | This patch enables QUAD read mode for qspi to improve the read performace while loading the binaries from qspi. Signed-off-by: Ravi Babu <ravibabu@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: ftssp010_spi: Use to_ftssp010_spi() to ensure free correct addressAxel Lin2015-03-30-1/+3
| | | | | | | | Don't assume slave is always the first member of struct ftssp010_spi. Use to_ftssp010_spi() to ensure free correct address in spi_free_slave(). Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: davinci: Remove duplicate code to set bus and cs for slaveAxel Lin2015-03-30-3/+0
| | | | | | | It's done in spi_alloc_slave(). Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: cf_qspi: Fixup to_cf_qspi_slave macroAxel Lin2015-03-30-1/+1
| | | | | | | | | The third parameter of container_of is the name of the member within the struct. Current code only works if the parameter passed to to_cf_qspi_slave named slave. Fix it. Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* dm: Expand and complete Kconfig in drivers/Simon Glass2015-02-12-2/+8
| | | | | | | | Expand the help messages for each driver. Add missing Kconfig for I2C, SPI flash and thermal. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* x86: Add SPI support to quark/galileoBin Meng2015-02-06-1/+2
| | | | | | | | | | The Quark SoC contains a legacy SPI controller in the legacy bridge which is ICH7 compatible. Like Tunnel Creek and BayTrail, the BIOS control register offset in the ICH SPI driver is wrong for the Quark SoC too, unprotect_spi_flash() is added to enable the flash write. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: spi: Support ValleyView in ICH SPI driverSimon Glass2015-02-06-20/+47
| | | | | | | | The base address is found in a different way and the protection bit is also in a different place. Otherwise it is very similar. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: spi: Move slave details to child platdataSimon Glass2015-01-29-43/+49
| | | | | | | | | | | | | | | | At present we go through various contortions to store the SPI slave's chip select in its private data. This only exists when the slave is active so must be set up when it is probed. Until the device is probed we don't actually know what chip select it will appear on. However, now that we can support per-child platform data, we can use that instead. This allows us to set up the chip select when the child is bound, and avoid the messy contortions. Unfortunately this is a fairly large change and it seems to be difficult to break it down further. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: spi: Set up the spi_slave device pointer in child_pre_probe()Simon Glass2015-01-29-0/+10
| | | | | | | | | | | At present we use struct spi_slave as our device pointer in a lot of places to avoid changing the old SPI API. At some point this will go away. But for now, it is better if the SPI uclass sets up this pointer, rather than relying on passing it into the device when it is probed. We can use the new uclass child_pre_probe() method to do this. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: spi: Move the per-child data size to the uclassSimon Glass2015-01-29-8/+1
| | | | | | | | This is common to all SPI drivers and specifies a structure used by the uclass. It makes more sense to define it in the uclass. Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: core: Add a flag to control sequence numberingSimon Glass2015-01-29-0/+1
| | | | | | | | | | | | | | | | At present we try to use the 'reg' property and device tree aliases to give devices a sequence number. The 'reg' property is often actually a memory address, so the sequence numbers thus-obtained are not useful. It would be better if the devices were just sequentially numbered in that case. In fact neither I2C nor SPI use this feature, so drop it. Some devices need us to look up an alias to number them within the uclass. Add a flag to control this, so it is not done unless it is needed. Adjust the tests to test this new behaviour. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* dm: spi: Remove use of fdtdec GPIO supportSimon Glass2015-01-29-34/+28
| | | | | | These functions are going away, so use the new uclass support instead. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: spi: Add device tree supportSimon Glass2015-01-24-0/+7
| | | | | | | As a temporary measure before the ICH driver moves over to driver model, add device tree support to the driver. Signed-off-by: Simon Glass <sjg@chromium.org>
* qspi:fsl implement AHB readPeng Fan2015-01-09-10/+142
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The QSPI controller in i.MX 6SoloX and Vybrid supports reading data using IP register and AHB bus. The original driver only supports reading data from IP interface. The IC team suggests to use AHB read which is faster then IP read. Using AHB read, we can directly memcpy, a "missed" access to the buffer will cause the controller to clear the buffer and use the SEQID stored in bfgencr register to initiate a read from flash device. Since AHB bus is 64 bit width, we can not set MCR register using 32bit. In order to minimize code change, redefine QSPI_MCR_END_CFD_LE to 64bit Little endian but not 32bit Little endia. Introduce a new configuration option CONFIG_SYS_FSL_QSPI_AHB. If want to use AHB read, just define CONFIG_SYS_FSL_QSPI_AHB. If not, just ignore it. Actually if Vybrid is migrated to use AHB read, this option can be removed and IP read function can be discared. The reason to introduce this option is that only i.MX SOC is tested in my side, no Vybrid platform for me. In spi_setup_slave, the original piece code to set AHB is deleted, since Vybrid platform does not use this to intiate AHB read. Instead, add qspi_init_ahb_read function if defined CONFIG_SYS_FSL_QSPI_AHB. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: ftssp010_spi: Simplify code flow in ftssp010_[wait|wait_tx|wait_rx]Axel Lin2015-01-08-24/+12
| | | | | | | No functional change, just simplify the code a bit. Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
generated by cgit v1.1 at 2024-12-29 15:03:00 +0000