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* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-02-12-7/+389
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| * tegra: add SPI SLINK driverAllen Martin2013-02-11-0/+344
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add driver for tegra SPI "SLINK" style driver. This controller is similar to the tegra20 SPI "SFLASH" controller. The difference is that the SLINK controller is a genernal purpose SPI controller and the SFLASH controller is special purpose and can only talk to FLASH devices. In addition there are potentially many instances of an SLINK controller on tegra and only a single instance of SFLASH. Tegra20 is currently ths only version of tegra that instantiates an SFLASH controller. This driver supports basic PIO mode of operation and is configurable (CONFIG_OF_CONTROL) to be driven off devicetree bindings. Up to 4 devices per controller may be attached, although typically only a single chip select line is exposed from tegra per controller so in reality this is usually limited to 1. To enable this driver, use CONFIG_TEGRA_SLINK Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: spi: add fdt support to tegra SPI SFLASH driverAllen Martin2013-02-11-2/+43
| | | | | | | | | | | | | | | | | | Add support for configuring tegra SPI driver from devicetree. Support is keyed off CONFIG_OF_CONTROL. Add entry in seaboard dts file for spi controller to describe seaboard spi. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * mxs: clock: Use 'mxs' prefix for methodsOtavio Salvador2013-01-21-1/+1
| | | | | | | | | | | | | | Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * mxs: ssp: Pull out the SSP bus to regs conversionMarek Vasut2013-01-21-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Create function which converts SSP bus number to SSP register pointer. This functionality is reimplemented multiple times in the code, thus make one common implementation. Moreover, make it a switch(), since the SSP ports are not mapped in such nice linear fashion on MX23, therefore having it a switch will simplify things there. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andy Fleming <afleming@freescale.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* | spi: xilinx_spi: Perform software reset during slave setupJason Wu2013-02-04-0/+5
|/ | | | | | to make sure it is in the clear state. Signed-off-by: Jason Wu <huanyu@xilinx.com>
* Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2013-01-14-6/+90
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| * SPI: EXYNOS: Add FDT support to driver.Rajeshwari Shinde2013-01-08-6/+90
| | | | | | | | | | | | | | | | | | This patch adds FDT support to the SPI driver. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | Merge 'u-boot-atmel/master' into 'u-boot-arm/master'Albert ARIBAUD2013-01-09-1/+1
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| * | spi: atmel: sam9m10g45 also support WDRBT bitBo Shen2012-12-09-1/+1
| |/ | | | | | | | | | | | | The at91sam9m10g45 also support WDRBT bit, add support for it Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | kirkwood: make MPP arrays static constAlbert ARIBAUD2013-01-09-7/+5
| | | | | | | | | | | | | | | | | | | | This saves stack and code memory for local copy, and consumes initialized data memory. For 22 of the 29 kirkwood-based boards, this results in a global saving of about 30 bytes. For 7 of them, it results in an increase of 6 to 14 bytes. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | OMAP3 SPI : Fixed bugs related to SPI transferajoy2012-12-10-32/+45
|/ | | | | | | | | | | | | | | | | | | | | | Added posted writes (read after writes) to effect the change immediately for channel confiuration and channel enable register Disable the channel to purge receieve data in TX_ONLY mode transfer otherwise rx data will get affected by the next immediate RX_ONLY mode transfer Wait for the EOT bit to be set after last byte has been loaded to TX shift register in the the TX_ONLY mode.This ensures TX data has been completely shifted out Disable the channel in RX_ONLY mode before reading the last data from RXX register to prevent the SPI slave to transmit next word Signed-off-by: Ajoy Kumar Das <akdas75@yahoo.in> Cc: Tom Rini <trini@ti.com> Cc: jacopo mondi <j.mondi@voltaelectronics.com>
* Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2012-11-25-4/+5
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| * spi: mxc_spi: Fix spi clock glitch durant resetFabio Estevam2012-11-19-2/+2
| | | | | | | | | | | | | | | | | | | | | | Measuring the spi clock line on a scope shows a 'glitch' during the reset of the spi. Fix this by toggling only the MXC_CSPICTRL_EN bit, so that the clock line becomes always stable. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * spi: mxc_spi: Fix handling of chip selectFabio Estevam2012-11-19-2/+3
| | | | | | | | | | | | | | | | | | In decode_cs() function the polarity of the chip select must be taken into account. Also, for the case of low active chip select, the CS was activated too early. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | SPI: Add SPI Driver for EXYNOS.Rajeshwari Shinde2012-11-15-0/+368
|/ | | | | | | | | | | | | | This patch adds SPI driver for EXYNOS. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Acked-by: Mike Frysinger <vapier@gentoo.org> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: jy0922.shim@samsung.com Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Merge remote-tracking branch 'u-boot-ti/master'Albert ARIBAUD2012-10-26-6/+5
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| * omap3_spi: introduce CONFIG_OMAP3_SPI_D0_D1_SWAPPEDPeter Korsgaard2012-10-25-6/+5
| | | | | | | | | | | | | | | | | | | | D0/D1 Swapped or not is a board property, not anything specific to the am33xx SoC, so add a custom define for it. At the same time correct the bit handling for the swapped mode (DPE0 should be cleared and SI/DPE1 set). Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
* | powerpc/espi: remove write command length checkShaohui Xie2012-10-22-4/+2
|/ | | | | | | | | | | | Current espi controller driver assumes the command length of write command is not equal to '1', it was made based on SPANSION SPI flash, but some SPI flash driver such as SST does use write command length as '1', so write command on SST SPI flash will not work. And the length check for write command is not necessary for SPANSION, though it's harmless for SPANSION, it will stop write operation on flashes like SST, so we remove the check. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Tegra20: Move some include files to arch-tegra for sharing with Tegra30Tom Warren2012-10-15-4/+3
| | | | | | | | | | | The move is pretty straight-forward. ap20.h and tegra20.h were renamed to ap.h and tegra.h. Some files remain in arch-tegra20 but 'include' a file in 'arch-tegra' with #defines & structs that will be common between T20 and T30 HW. HW-specific #defines, etc. stay in the 'arch-tegra20' 'root' file. All boards build OK w/MAKEALL -s tegra20. Checkpatch.pl runs clean. Seaboard works OK. Signed-off-by: Tom Warren <twarren@nvidia.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2012-09-21-30/+39
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| * Merge remote-tracking branch 'u-boot-imx/master'Albert ARIBAUD2012-09-21-25/+33
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| | * MX28: SPI: Fix the DMA chainingMarek Vasut2012-09-06-18/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It turns out that in order for the SPI DMA to properly support continuous transfers longer than 65280 bytes, there are some very important parts that were left out from the documentation. Firstly, the XFER_SIZE register is not written with the whole length of a transfer, but is written by each and every chained descriptor with the length of the descriptors data buffer. Next, unlike the demo code supplied by FSL, which only writes one PIO word per descriptor, this does not apply if the descriptors are chained, since the XFER_SIZE register must be written. Therefore, it is essential to use four PIO words, CTRL0, CMD0, CMD1, XFER_SIZE. CMD0 and CMD1 are written with zero, since they don't apply. The DMA programs the PIO words in an incrementing order, so four PIO words. Finally, unlike the demo code supplied by FSL, the SSP_CTRL0_IGNORE_CRC must not be set during the whole transfer, but it must be set only on the last descriptor in the chain. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| | * MX28: SPI: Fix the DMA DCache race conditionMarek Vasut2012-09-06-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes dcache-related problem. The problem manifested when dcache was enabled and the following command issued twice: mw 0x42000000 0 0x4000 ; sf probe ; sf read 0x42000000 0x0 0x10000 ; sha1sum 0x42000000 0x10000 The SHA1 checksum was correct during the first call. Yet with every subsequent call of the above command, it differed and was wrong. It turns out this was because of a race condition. On the first time the command was called, no cacheline contained any data from the destination memory location. The DMA transfered data into the location and the cache above the location was invalidated. Then the checksum was computed, but that meant the data were loaded into data cache. On any subsequent call, the DMA again transfered data into the same destination. Yet during the transfer, some of the DCache lines were evicted and written back into the main memory. Once the DMA transfer completed, the data cache was invalidated over the memory location as usual. But the data that were to be loaded back into the data cache by subsequent SHA1 checksuming were corrupted. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| * | Tegra: Change Tegra20 to Tegra in common code, prep for T30Tom Warren2012-09-10-3/+3
| |/ | | | | | | | | | | | | | | | | | | Convert TEGRA20_ defines to either TEGRA_ or NV_PA_ where appropriate. Convert tegra20_ source file and function names to tegra_, also. Upcoming Tegra30 port will use common code/defines/names where possible. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
| * kw_spi: fix clock prescaler computationValentin Longchamp2012-09-03-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The computation was not correct with low clock values: setting a 1MHz clock would result in an overlap that would then configure a 25Mhz clock. This patch implements a correct computation method according to the kirkwood functionnal spec. table 600 (Serial Memory Interface Configuration Register). Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Holger Brunck <holger.brunck@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> Acked-by: Prafulla Wadaskar <Prafulla@marvell.com> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
* | ColdFire: Queued SPI driverRichard Retanubun2012-09-20-0/+374
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds a driver for Freescale Colfire Queued SPI bus. Coded to work with 8 bits per transfer to use with SPI flash. CPOL, CPHA, and CS_ACTIVE_HIGH can be configured. Tested with MCF5270 which have 4 chip selects. Activate by #define CONFIG_CF_QSPI in board config. Signed-off-by: Richard Retanubun <richardretanubun@ruggedcom.com>
* | mpc8xxx_spi: fix SPI support on MPC8308RDBIra W. Snyder2012-09-18-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | The MPC8308RDB Reference Manual states that no bits in the SPMODE register are allowed to change while the enable (EN) bit is set. This driver changes the character length bits (LEN) while the enable (EN) bit is set. Clearing the EN bit while changing the LEN bits makes the driver work correctly on MPC8308RDB. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | spi: xilinx: Remove unused variableStephan Linz2012-09-11-1/+0
|/ | | | | | | | | | Warning is: xilinx_spi.c: In function 'spi_setup_slave': xilinx_spi.c:81: warning: unused variable 'regs' Signed-off-by: Stephan Linz <linz@li-pro.net> CC: Michal Simek <monstr@monstr.eu>
* spi: atmel: add WDRBT bit to avoid receive overrunBo Shen2012-09-01-0/+4
| | | | | | | | | | The atmel at91sam9x5 series spi has feature to avoid receive overren Using the patch to enable it Signed-off-by: Bo Shen <voice.shen@atmel.com> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* MX28: SPI: Supercharge the SPI driverMarek Vasut2012-09-01-31/+65
| | | | | | | | | | This change implements DMA chaining into SPI driver. This allows the transfers to go much faster, while also fixing SF issues. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
* spi: fix mxs_spi_slave structure allocation to clear memoryMatt Sealey2012-09-01-1/+1
| | | | | | | | | | | | | | | Use calloc() instead of malloc() to allocate the mxs_spi_slave structure. Clearing the memory is necessary since most of the time this gets done super early in boot, but on warm reboots, and when SPI probing is done long after the init stages it could actually pick up previously used memory, and things like the chipselect polarity and other data end up being filled with trash data if not explicitly set by the board files. This solves a semi-random, almost unreproducable error whereby SPI devices act very, very strangly on boot. Signed-off-by: Matt Sealey <matt@genesi-usa.com> Acked-by: Stefano Babic <sbabic@denx.de>
* spi: fix mxc_spi_slave structure allocation to clear memoryMatt Sealey2012-09-01-1/+1
| | | | | | | | | | | | | | | Use calloc() instead of malloc() to allocate the mxc_spi_slave structure. Clearing the memory is necessary since most of the time this gets done super early in boot, but on warm reboots, and when SPI probing is done long after the init stages it could actually pick up previously used memory, and things like the chipselect polarity and other data end up being filled with trash data if not explicitly set by the board files. This solves a semi-random, almost unreproducable error whereby SPI devices act very, very strangly on boot. Tested on Efika MX over several years.. Signed-off-by: Matt Sealey <matt@genesi-usa.com> Acked-by: Stefano Babic <sbabic@denx.de>
* mxc_spi: Round up clock dividerBenoît Thébaudeau2012-09-01-2/+2
| | | | | | | | | | | Since the input frequency of the API is a maximum that should not be exceeded in order for the devices to operate properly, the SPI clock divider should be rounded up, not truncated. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* mxs: Convert sys_proto.h prefixes to 'mxs'Otavio Salvador2012-09-01-4/+4
| | | | | | | The sys_proto.h functions (except the boot modes) are compatible with i.MX233 and i.MX28 so we use 'mxs' prefix for its methods. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* tegra20: rename tegra2 -> tegra20Allen Martin2012-09-01-5/+5
| | | | | | | | | | This is make naming consistent with the kernel and devicetree and in preparation of pulling out the common tegra20 code. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* am335x evm: Enable support for spi0Tom Rini2012-09-01-0/+10
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Add support, update omap3 McSPI driverTom Rini2012-09-01-0/+11
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* mxs: prefix register structs with 'mxs' prefixOtavio Salvador2012-09-01-10/+9
| | | | Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* MX28: SPI: Add DMA transfer supportMarek Vasut2012-09-01-1/+116
| | | | | | | | | | | | | | | | | The DMA transfers happen only if the transfered data are larger than 512 bytes. Otherwise PIO is used. This is a small speed optimization. The DMA transfer doesn't work if unaligned transfer is requested due to the limitation of the DMA controller. This has to be fixed by introducing generic bounce buffer. Therefore the DMA feature is now disabled by default. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* MX28: SPI: Pull out the PIO transfer functionMarek Vasut2012-09-01-33/+41
| | | | | | | | | | | Pull out all the PIO transfer logic into separate function, so DMA can be added. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* MX28: SPI: Refactor spi_xfer a bitMarek Vasut2012-09-01-10/+22
| | | | | | | | | | This makes it easier to adapt for addition of DMA support. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* spi: Fix merge conflicts - MakefileMichal Simek2012-08-07-1/+0
| | | | | | | | | | | | | | | The patch "spi: tegra2: rename tegra2_spi.* to tegra_spi.*" (sha1: edffa63d3d6e76991998789f9fcbaa483731ca65) renamed tegra2_spi.c to tegra_spi.c and the patch "Merge branch 'master' of git://git.denx.de/u-boot-microblaze" (sha1: d978780b2e676c005460cd561f4f15b5220bdf49) has wrongly resolved confict. This patch fix it. Signed-off-by: Michal Simek <monstr@monstr.eu>
* Merge branch 'master' of git://git.denx.de/u-boot-microblazeWolfgang Denk2012-07-31-0/+351
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-microblaze: microblaze: Wire up SPI driver spi: microblaze: Adds driver for Xilinx SPI controller microblaze: intc: Clear interrupt code microblaze: Call serial multi initialization microblaze: Move __udelay implementation microblaze: Remove extern from board.c microblaze: Wire up dts configuration fdt: Add board specific dts inclusion microblaze: Move individual board linker scripts to common script in cpu tree. microblaze: Add gpio.h microblaze: Add missing undefs for UBI and UBIFS microblaze: Expand and correct configuration comments microblaze: Enable ubi support microblaze: Avoid compile error on systems without cfi flash microblaze: Remove wrong define CONFIG_SYS_FLASH_PROTECTION Conflicts: drivers/spi/Makefile Signed-off-by: Wolfgang Denk <wd@denx.de>
| * spi: microblaze: Adds driver for Xilinx SPI controllerStephan Linz2012-07-31-0/+350
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is an improved version of the driver patch original submitted by Graeme Smecher <graeme.smecher@mail.mcgill.ca> The changes are: - remove hard coded Xilinx BSP defines (XPAR_SPI_*) and use CONFIG_SYS_SPI_BASE from config.h instead - add extensive register struct definitions - remove offset calculation for register access and use the new register struct instead - move default SPI controller configuration from spi_setup_slave() to spi_claim_bus() - add spi_set_speed() - insert SPI controller deactivation in spi_release_bus() - protect while loops in spi_xfer() with counter / timeouts - support SPI mode flags: LSB_FIRST, CPHA, CPOL, LOOP Come from: http://patchwork.ozlabs.org/patch/71797/ Signed-off-by: Stephan Linz <linz@li-pro.net> Tested-by: Michal Simek <monstr@monstr.eu>
* | kw_spi: add weak functions board_spi_claim/release_busValentin Longchamp2012-07-07-1/+12
| | | | | | | | | | | | | | | | | | | | This allows a final, board specific, step in the claim/relase_bus function for the SPI controller, which may be needed for some hardware designs. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Holger Brunck <holger.brunck@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com>
* | kw_spi: support spi_claim/release_bus functionsValentin Longchamp2012-07-07-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | These two function nows ensure that the MPP is configured correctly for the SPI controller before any SPI access, and restore the initial configuration when the access is over. Since the used pins for the SPI controller can differ (2 possibilities for each signal), the used pins are configured with CONFIG_SYS_KW_SPI_MPP. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Holger Brunck <holger.brunck@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com>
* | kw_spi: backup and reset the MPP of the chosen CS pinValentin Longchamp2012-07-07-9/+6
| | | | | | | | | | | | | | | | | | This was not done before, and in the case of a shared pin (for MPP0 between NF_IO[2] and CSn) this could lead to problems. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Holger Brunck <holger.brunck@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com>
* | spi: tegra2: rename tegra2_spi.* to tegra_spi.*Tom Warren2012-07-07-3/+3
| | | | | | | | | | | | | | | | In anticipation of Tegra3 support, start removing/renaming Tegra2-specific files. No functional changes (yet). Also updated copyright to 2012. Signed-off-by: Tom Warren <twarren@nvidia.com>
* | spi: Tegra2: Seaboard: fix UART corruption during SPI transactionsTom Warren2012-07-07-1/+12
|/ | | | | | | | | | | Simon Glass's proposal to fix this on Seaboard was NAK'd, so I removed his NS16550 references and added a small delay before SPI/UART muxing. Tested on my Seaboard with large SPI reads/writes and saw no corruption (crc's matched) and no spurious comm chars. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
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