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* MLK-10774-4 fsl:qspi update qspi driverPeng Fan2015-04-29-596/+684
| | | | | | Use freescale vendor qspi driver but not upstream qspi driver Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* lpc32xx: add LPC32xx SSP support (SPI mode)Albert ARIBAUD \(3ADEV\)2015-04-10-0/+145
| | | | | Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* spi: designware_spi: revisit FIFO size detection againAxel Lin2015-03-30-2/+2
| | | | | | | | | | | | | | | | By specification the FIFO size would be in a range 2-256 bytes. From TX Level prospective it means we can set threshold in the range 0-(FIFO size - 1) bytes. Hence there are currently two issues: a) FIFO size 2 bytes is actually skipped since TX Level is 1 bit and could be either 0 or 1 byte; b) FIFO size is incorrectly decreased by 1 which already done by meaning of TX Level register. Fixes: 501943696ea4 (spi: designware_spi: Fix detecting FIFO depth) Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: cf_spi: Staticize local functionsAxel Lin2015-03-30-13/+7
| | | | | | | Make local functions static and remove unneeded forward declarations. Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: cf_spi: Use to_cf_spi_slave to resolve cfslave from slaveAxel Lin2015-03-30-2/+9
| | | | | | | | Don't assume slave is always the first member of struct cf_spi_slave. Use container_of instead of casting first structure member. Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* qspi: dra7x: enable quad mode read for ti-qspi driverRavi Babu2015-03-30-0/+7
| | | | | | | | This patch enables QUAD read mode for qspi to improve the read performace while loading the binaries from qspi. Signed-off-by: Ravi Babu <ravibabu@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: ftssp010_spi: Use to_ftssp010_spi() to ensure free correct addressAxel Lin2015-03-30-1/+3
| | | | | | | | Don't assume slave is always the first member of struct ftssp010_spi. Use to_ftssp010_spi() to ensure free correct address in spi_free_slave(). Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: davinci: Remove duplicate code to set bus and cs for slaveAxel Lin2015-03-30-3/+0
| | | | | | | It's done in spi_alloc_slave(). Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: cf_qspi: Fixup to_cf_qspi_slave macroAxel Lin2015-03-30-1/+1
| | | | | | | | | The third parameter of container_of is the name of the member within the struct. Current code only works if the parameter passed to to_cf_qspi_slave named slave. Fix it. Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* dm: Expand and complete Kconfig in drivers/Simon Glass2015-02-12-2/+8
| | | | | | | | Expand the help messages for each driver. Add missing Kconfig for I2C, SPI flash and thermal. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* x86: Add SPI support to quark/galileoBin Meng2015-02-06-1/+2
| | | | | | | | | | The Quark SoC contains a legacy SPI controller in the legacy bridge which is ICH7 compatible. Like Tunnel Creek and BayTrail, the BIOS control register offset in the ICH SPI driver is wrong for the Quark SoC too, unprotect_spi_flash() is added to enable the flash write. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: spi: Support ValleyView in ICH SPI driverSimon Glass2015-02-06-20/+47
| | | | | | | | The base address is found in a different way and the protection bit is also in a different place. Otherwise it is very similar. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: spi: Move slave details to child platdataSimon Glass2015-01-29-43/+49
| | | | | | | | | | | | | | | | At present we go through various contortions to store the SPI slave's chip select in its private data. This only exists when the slave is active so must be set up when it is probed. Until the device is probed we don't actually know what chip select it will appear on. However, now that we can support per-child platform data, we can use that instead. This allows us to set up the chip select when the child is bound, and avoid the messy contortions. Unfortunately this is a fairly large change and it seems to be difficult to break it down further. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: spi: Set up the spi_slave device pointer in child_pre_probe()Simon Glass2015-01-29-0/+10
| | | | | | | | | | | At present we use struct spi_slave as our device pointer in a lot of places to avoid changing the old SPI API. At some point this will go away. But for now, it is better if the SPI uclass sets up this pointer, rather than relying on passing it into the device when it is probed. We can use the new uclass child_pre_probe() method to do this. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: spi: Move the per-child data size to the uclassSimon Glass2015-01-29-8/+1
| | | | | | | | This is common to all SPI drivers and specifies a structure used by the uclass. It makes more sense to define it in the uclass. Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: core: Add a flag to control sequence numberingSimon Glass2015-01-29-0/+1
| | | | | | | | | | | | | | | | At present we try to use the 'reg' property and device tree aliases to give devices a sequence number. The 'reg' property is often actually a memory address, so the sequence numbers thus-obtained are not useful. It would be better if the devices were just sequentially numbered in that case. In fact neither I2C nor SPI use this feature, so drop it. Some devices need us to look up an alias to number them within the uclass. Add a flag to control this, so it is not done unless it is needed. Adjust the tests to test this new behaviour. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* dm: spi: Remove use of fdtdec GPIO supportSimon Glass2015-01-29-34/+28
| | | | | | These functions are going away, so use the new uclass support instead. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: spi: Add device tree supportSimon Glass2015-01-24-0/+7
| | | | | | | As a temporary measure before the ICH driver moves over to driver model, add device tree support to the driver. Signed-off-by: Simon Glass <sjg@chromium.org>
* qspi:fsl implement AHB readPeng Fan2015-01-09-10/+142
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The QSPI controller in i.MX 6SoloX and Vybrid supports reading data using IP register and AHB bus. The original driver only supports reading data from IP interface. The IC team suggests to use AHB read which is faster then IP read. Using AHB read, we can directly memcpy, a "missed" access to the buffer will cause the controller to clear the buffer and use the SEQID stored in bfgencr register to initiate a read from flash device. Since AHB bus is 64 bit width, we can not set MCR register using 32bit. In order to minimize code change, redefine QSPI_MCR_END_CFD_LE to 64bit Little endian but not 32bit Little endia. Introduce a new configuration option CONFIG_SYS_FSL_QSPI_AHB. If want to use AHB read, just define CONFIG_SYS_FSL_QSPI_AHB. If not, just ignore it. Actually if Vybrid is migrated to use AHB read, this option can be removed and IP read function can be discared. The reason to introduce this option is that only i.MX SOC is tested in my side, no Vybrid platform for me. In spi_setup_slave, the original piece code to set AHB is deleted, since Vybrid platform does not use this to intiate AHB read. Instead, add qspi_init_ahb_read function if defined CONFIG_SYS_FSL_QSPI_AHB. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: ftssp010_spi: Simplify code flow in ftssp010_[wait|wait_tx|wait_rx]Axel Lin2015-01-08-24/+12
| | | | | | | No functional change, just simplify the code a bit. Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: cadence_qspi: Fix checking return value of fdt_first_subnode()Axel Lin2015-01-07-1/+1
| | | | | | | | fdt_first_subnode() returns -FDT_ERR_NOTFOUND if no subnode found. 0 is supposed to be a valid offset returns from fdt_first_subnode(). Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi:fsl-quadspi support bank register read writePeng Fan2015-01-07-15/+145
| | | | | | | | | | | | | | | | | | | | To support bigger than 16MB size qspi flashes, spi framework uses bank switch to access higher bank or lower bank. In this patch, QSPI_CMD_BRRD, QSPI_CMD_BRWR, QSPI_CMD_WREAR, QSPI_CMD_RDEAR is initialized in LUT register with related pad and length configuration. qspi_op_pp is originally for page programming, this patch reuses this function for bank register switch and renamed it with qspi_op_write. Since bank or EAR register is only 1 byte length, however original qspi_op_pp or now renamed qspi_op_write only support 4 bytes lenght as the access unit, this will trigger data abort exception when access EAR or bank register. This is because upper framework passes a 1 bytes pointer to qspi_op_write, however qspi_op_write treat it as an int pointer. This patch fixes this for accessing EAR or bank register. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* dt: socfpga: Rename snps, dw-spi-mmio to snps, dw-apb-ssiMarek Vasut2015-01-06-1/+1
| | | | | | | | | | | | | | | Linux now also contains SPI driver, yet the name is 'snps,dw-apb-ssi'. Fix the naming before we have to support both names. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: designware_spi: Fix detecting FIFO depthAxel Lin2015-01-06-2/+2
| | | | | | | | | | | | | | | | Current code tries to find the highest valid fifo depth by checking the value it wrote to DW_SPI_TXFLTR. There are a few problems in current code: 1) There is an off-by-one in dws->fifo_len setting because it assumes the latest register write fails so the latest valid value should be fifo - 1. 2) We know the depth could be from 2 to 256 from HW spec, so it is not necessary to test fifo == 257. In the case fifo is 257, it means the latest valid setting is fifo = 256. So after the for loop iteration, we should check fifo == 2 case instead of fifo == 257 if detecting the FIFO depth fails. This patch fixes above issues. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* imx:qspi add 4K erase supportPeng Fan2014-12-31-5/+19
| | | | | | | | | Add 4k erase command support for qspi driver. reuse the 64k erase function, but change the function name from qspi_op_se to qspi_op_erase, since it supports 64k and 4k erase. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* arm:mx6sx add QSPI supportPeng Fan2014-12-31-0/+19
| | | | | | | Add QSPI support for mx6solox. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* QuadSPI: use correct amba_basePeng Fan2014-12-31-5/+25
| | | | | | | | | According cs, use different amba_base to choose the corresponding flash devices. If not, `sf probe 1:0` and `sf probe 1:1` will choose the same flash device, but not different flash devices. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* QuadSPI: use QSPI_CMD_xx instead of flash opcodesPeng Fan2014-12-31-31/+33
| | | | | | | Use QSPI_CMD_xx instead of flash opcodes Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2014-12-16-0/+1747
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| * spi: designware_spi: Some fixes / changesStefan Roese2014-12-06-19/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As suggested by Pavel, here some fixes to the designware SPI driver: - Spelling fixes - Comment for timeout added - Removed n_bytes completely (bits_per_word is enough for this) - Unput clock now not defined via macro. The function to get the clock value is now called directly from within the driver Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * spi: Add designware master SPI DM driver used on SoCFPGAStefan Roese2014-12-06-0/+426
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the driver for the Designware master SPI controller. This IP core is integrated on the Altera SoCFPGA. This implementation is a driver model (DM) implementation. So multiple SPI drivers can be used. Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller used to connect the SPI NOR flashes. Without DM, using multiple SPI drivers is not possible. This driver is very loosely based on the Linux driver. Most of the Linux driver is removed. Only the polling loop for the transfer is really used from this driver, as we don't support interrupts and DMA right now. This is tested on the SoCrates SoCFPGA board using the SPI pins on the P14 header. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * spi: Add Cadence QSPI DM driver used by SoCFPGAStefan Roese2014-12-06-0/+1320
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver is cloned from the Altera Rockerboard.org U-Boot repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some modification to support the U-Boot driver model (DM). As mentioned above, in this new version I ported this driver to the new driver model (DM). One big advantage of this move is that now multiple SPI drivers can be enabled on one platform. And since the SoCFPGA also has the Designware SPI master controller integrated, this feature is really needed to support both controllers. Because of this, this series needs the DT support for SoCFPGA to be applied. For DT based probing in the SPI DM. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | x86: ich-spi: Add Intel Tunnel Creek SPI controller supportBin Meng2014-12-13-1/+2
| | | | | | | | | | | | | | | | Add Intel Tunnel Creek SPI controller support which is an ICH7 compatible device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: ich-spi: Set the tx operation mode for ich 7Bin Meng2014-12-13-2/+7
| | | | | | | | | | | | | | | | ICH 7 SPI controller only supports byte program (02h) for SST flash. Word program (ADh) is not supported. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | x86: ich-spi: Set the rx operation mode for ich 7Bin Meng2014-12-13-0/+4
| | | | | | | | | | | | | | | | | | | | ICH 7 SPI controller only supports array read command (03h). Fast array read command (0Bh) is not supported. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | x86: ich-spi: Fix a bug of reading from a non-64 bytes aligned addressBin Meng2014-12-13-15/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | The ich spi controller driver spi_xfer() tries to align reading address to 64 bytes when doing spi data in, which causes a bug of either infinite loop or a huge size memcpy(). Actually the ich spi controller does not have such requirement of 64 bytes alignment when reading data from spi slave devices. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | arm: omap: add support for am57xx devicesFelipe Balbi2014-12-04-4/+4
|/ | | | | | | | just add a few ifdefs around because this device is very similar to dra7xxx. Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* Merge git://git.denx.de/u-boot-dmTom Rini2014-11-24-32/+2
|\ | | | | | | | | | | | | Conflicts: drivers/serial/serial-uclass.c Signed-off-by: Tom Rini <trini@ti.com>
| * dm: spi: Use device_bind_driver() instead of our own functionSimon Glass2014-11-22-22/+1
| | | | | | | | | | | | | | | | | | | | The SPI function does the same thing, so we may as well just use the new generic function. The 'cs' parameter was not actually used, so can be dropped. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Acked-by: Heiko Schocher <hs@denx.de>
| * dm: spi: Correct handling of SPI chip selects in sandboxSimon Glass2014-11-22-10/+1
| | | | | | | | | | | | | | | | | | This code was not updated when the chip select handling was adjusted. Fix it to call the correct function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Acked-by: Heiko Schocher <hs@denx.de>
* | linux/kernel.h: sync min, max, min3, max3 macros with LinuxMasahiro Yamada2014-11-23-4/+4
|/ | | | | | | | | | | | | | | | | | | | U-Boot has never cared about the type when we get max/min of two values, but Linux Kernel does. This commit gets min, max, min3, max3 macros synced with the kernel introducing type checks. Many of references of those macros must be fixed to suppress warnings. We have two options: - Use min, max, min3, max3 only when the arguments have the same type (or add casts to the arguments) - Use min_t/max_t instead with the appropriate type for the first argument Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Pavel Machek <pavel@denx.de> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [trini: Fixup arch/blackfin/lib/string.c] Signed-off-by: Tom Rini <trini@ti.com>
* spi, atmel: move CONFIG_SYS_SPI_WRITE_TOUT into common headerHeiko Schocher2014-11-17-0/+4
| | | | | | | | | | | | move CONFIG_SYS_SPI_WRITE_TOUT into drivers/spi/atmel_spi.h and define a default value. Delete this define in the board config files, where it is possible (all boards use currently the same value). Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* SPI: mxc_spi: delay initialisation until claim busMarkus Niebel2014-10-27-16/+21
| | | | | | | | | it is not correct to init for a specific slave in spi_setup_slave. instead buffer the values and delay init until spi_claim_bus. Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com> Acked-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* SPI: mxc_spi: remove second reset from ECSPI config handlerMarkus Niebel2014-10-27-3/+0
| | | | | | | | | | | | the second reset prevents other registers to be written. This will prevent to have the correct signal levels for SCLK before writing to the config reg in spi_xchg_single. Tested with GPIO based chipselect and SPI_MODE_3 on i.MX6S Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com> Acked-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: altera: Move the config options to the topMarek Vasut2014-10-27-8/+8
| | | | | | | | | | | | | Just move the configuration options scattered all over the driver to the top of the source file. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: altera: Clean up the use of variable dMarek Vasut2014-10-27-10/+13
| | | | | | | | | | | | | | | | The variable d is used in rather questionable way. Rework the code a bit so it's clearer what it does. Also, rename the variable from d to data to make it's name less mysterious. Finally, change it's data type to uint32_t , since it's accessed as a 32bit number. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: altera: Zap endless loopMarek Vasut2014-10-27-2/+11
| | | | | | | | | | | | | | | The driver contained an endless loop when waiting for TX completion, this is a bad idea since if the hardware fails, the loop might spin forever. Add timeout and handle it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: altera: Clean up most checkpatch issuesMarek Vasut2014-10-27-10/+13
| | | | | | | | | | | | | | | | | This patch just zaps most of the checkpatch cries present in the driver. There is one more left, which will be addressed separately. There is no functional change. This patch also adds a bunch of newlines all around the place, this is to make the code much more readable. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: altera: Clean up bit definitionsMarek Vasut2014-10-27-13/+13
| | | | | | | | | | | | | | Clean up the definitions of bits in the Altera SPI driver, there is no need to put braces around numbers afterall. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: altera: Use struct-based register accessMarek Vasut2014-10-27-24/+25
| | | | | | | | | | | | | | | | Zap the offset-based register access and use the struct-based one as this is the preferred method. No functional change, but there are some line-over-80 problems in the driver, which will be addressed later. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
generated by cgit v1.1 at 2024-11-08 20:38:12 +0000