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* Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2014-03-25-19/+25
|\ | | | | | | | | | | | | | | Trivial merge conflict, needed to manually remove local_info as per commit 41364f0f. Conflicts: board/samsung/common/board.c
| * sandbox: Add implementation of spi_setup_slave_fdt()Simon Glass2014-03-17-0/+13
| | | | | | | | | | | | This function is needed when CONFIG_OF_SPI is defined. Signed-off-by: Simon Glass <sjg@chromium.org>
| * spi: atmel_dataflash: Simplify AT91F_SpiEnable implementationAxel Lin2014-03-17-19/+12
| | | | | | | | | | | | | | | | Refactor the code a bit to make it better in readability. Remove the comments because now the intention of the code is pretty clear. Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* | drivers/spi/omap3: Bug fix of premature write transfer completionVasili Galka2014-03-12-2/+3
|/ | | | | | | | | | The logic determining SPI "write" transfer completion was faulty. At certain conditions (e.g. slow SPI clock freq) the transfers were interrupted before completion. Both EOT and TXS flags of channel status registeer shall be checked to ensure that all data was transferred. Tested on AM3359 chip. Signed-off-by: Vasili Galka <vasili@visionmap.com>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2014-02-21-8/+42
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| * spi: ti_qspi: Add delay before xfer for am43xxSourav Poddar2014-02-18-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without this delay, write/read is failing. Looks like, the WIP always remain set and hence a timeout occurs leading to the error. Without this patch, device does not get probed also. Here is the log. U-Boot# U-Boot# U-Boot# U-Boot# sf probe 0 SF: Unsupported flash IDs: manuf ff, jedec ffff, ext_jedec ffff Failed to initialize SPI flash at 0:0 U-Boot# sf probe 0 While with this patch, log is U-Boot# sf probe 0 SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB, mapped at 30000000 U-Boot# sf erase 0 0x80000 SF: 524288 bytes @ 0x0 Erased: OK U-Boot# mw 81000000 0xdededede 0x40000 U-Boot# sf write 81000000 0 0x40000 SF: 262144 bytes @ 0x0 Written: OK U-Boot# sf read 82000000 0 0x40000 SF: 262144 bytes @ 0x0 Read: OK U-Boot# md 0x82000000 Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * spi: ti_qspi: Add AM43xx specifics changesSourav Poddar2014-02-18-3/+23
| | | | | | | | | | | | | | Add AM43xx specific changes. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * spi: spi-mxc: implement clk control for ECSPI to fix SPI_MODE_3Markus Niebel2014-02-18-2/+7
| | | | | | | | | | | | | | | | | | | | SPI_MODE_3 requires clk high when inactive. The SCLK_CTL field of the config reg was not configured in case of CPOL. Fix configuration so that SPI_MODE_3 which uses CPOL configures the clk line to be high in inactive state. Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * spi: xilinx: Move timeout calculation out of the loopMichal Simek2014-02-18-3/+5
| | | | | | | | | | | | | | | | Timeout calculation should be out of the data loop. This patch increase spi bandwidth for 30%. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* | blackfin: add spi and i2c specific get clock functionsSonic Zhang2014-02-20-6/+8
|/ | | | Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-01-16-1/+2
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| * spi: sh_qspi: Add header file that defines the address of registersNobuhiro Iwamatsu2014-01-16-1/+2
| | | | | | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | spi: sh_spi: Use sh_spi_clear_bit() instead of open-codedAxel Lin2014-01-11-8/+2
| | | | | | | | | | | | | | | | We have a sh_spi_clear_bit() function, there's no reason not to use it. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* | spi: Add Faraday SPI controller supportKuo-Jung Su2014-01-11-0/+509
|/ | | | | | | | | | | | | | | | | The Faraday FTSSP010 is a multi-function controller which supports I2S/SPI/SSP/AC97/SPDIF. However This patch implements only the SPI mode. NOTE: The DMA and CS/Clock control logic has been altered since hardware revision 1.19.0. So this patch would first detects the revision id of the underlying chip, and then switch to the corresponding software control routines. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> CC: Tom Rini <trini@ti.com>
* spi: tegra: clear RDY bit prior to every transferYen Lin2013-12-19-13/+8
| | | | | | | | | | | | | | | | | | | | | | The RDY bit indicates that a transfer is complete. This needs to be cleared by SW before every single HW transaction, rather than only at the start of each SW transaction (those being made up of n HW transactions). It seems that earlier HW may have cleared this bit autonomously when starting a new transfer, and hence this code was not needed in practice. However, this is generally a good idea in all cases. In Tegra124, the HW behaviour appears to have changed, and SW must explicitly clear this bit. Otherwise, SW will believe that transfers have completed when they have not, and may e.g. read stale data from the RX FIFO. Signed-off-by: Yen Lin <yelin@nvidia.com> [swarren, rewrote commit description, unified duplicate RDY clearing code and moved it right before the start of the HW transaction, unconditionally exit loop after reading RX data, rather than checking if TX FIFO is empty, since it is guaranteed to be] Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* spi: Add support SH Quad SPI driverNobuhiro Iwamatsu2013-12-18-0/+278
| | | | | | | | | This patch adds a driver for Renesas SoC's Quad SPI bus. This supports with 8 bits per transfer to use with SPI flash. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* Merge branch 'spi' of git://git.denx.de/u-boot-x86Tom Rini2013-12-10-5/+229
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| * sandbox: spi: Add SPI emulation busMike Frysinger2013-12-09-0/+205
| | | | | | | | | | | | | | This adds a SPI framework for people to hook up simulated SPI clients. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * spi_flash: Add spi_flash_probe_fdt() to locate SPI by FDT nodeSimon Glass2013-12-09-5/+24
| | | | | | | | | | | | | | This allows us to put the SPI flash chip inside the SPI interface node, with U-Boot finding the correct bus and chip select automatically. Signed-off-by: Simon Glass <sjg@chromium.org>
* | spi: bfin_spi6xx: Remove unnecessary test for bus and pins[bus]Axel Lin2013-12-06-4/+1
| | | | | | | | | | | | | | | | | | | | | | For invalid bus number, current code returns NULL in the default case of switch-case statements. In additional, pins[bus] is always not NULL because it is the address of specific row of the two-dimensional array. Thus this patch removes these unnecessary test. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Scott Jiang <scott.jiang.linux@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
* | spi: bfin_spi: Remove unnecessary test for bus and pins[bus]Axel Lin2013-12-06-8/+9
|/ | | | | | | | | | | For invalid bus number, current code returns NULL in the default case of switch-case statements. In additional, pins[bus] is always not NULL because it is the address of specific row of the two-dimensional array. Thus this patch removes these unnecessary test. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Scott Jiang <scott.jiang.linux@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
* spi: omap3: add support for more word lengthsNikita Kiryanov2013-11-12-24/+66
| | | | | | | | | | | | | | | | | | Current implementation only supports 8 bit word lengths, even though omap3 can handle anything between 4 and 32. Update the spi interface to support changing the SPI word length, and implement it in omap3_spi driver to support the full range of possible word lengths. This implementation is backwards compatible by defaulting to the old behavior of 8 bit word lengths. Also, it required a change to the omap3_spi non static I/O functions, but since they are not used anywhere else, no collateral changes are required. Cc: Tom Rini <trini@ti.com> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* spi: omap3: remove semicolon from #defineNikita Kiryanov2013-11-12-1/+1
| | | | | | | | | | Remove unnecessary semicolon from #define SPI_WAIT_TIMEOUT Cc: Tom Rini <trini@ti.com> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Gerhard Sittig <gsi@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* drivers: convert makefiles to Kbuild styleMasahiro Yamada2013-10-31-53/+31
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* spi: mxc_spi: Fix double incrementing read pointer for unaligned buffersTimo Herbrecher2013-10-16-1/+1
| | | | | | | | If dout buffer is not 32 bit-aligned or data to transmit is not multiple of 32 bit the read data pointer is already incremented on single byte reads. Signed-off-by: Timo Herbrecher <t.herbrecher@gateware.de> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* spi: Add GPL-2.0+ SPDX-License-Identifier for missing filesJagannadha Sutradharudu Teki2013-10-16-5/+5
| | | | | | | Added GPL-2.0+ SPDX-License-Identifier for missed spi source files. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* Coding Style cleanup: replace leading SPACEs by TABsWolfgang Denk2013-10-14-7/+7
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Drop changes for PEP 4 following python tools] Signed-off-by: Tom Rini <trini@ti.com>
* Coding Style cleanup: remove trailing white spaceWolfgang Denk2013-10-14-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* spi: exynos: Support word transfersRajeshwari Shinde2013-10-08-15/+61
| | | | | | | | | | | | | | Since SPI register access is so expensive, it is worth transferring data a word at a time if we can. This complicates the driver unfortunately. Use the byte-swapping feature to avoid having to convert to/from big endian in software. This change increases speed from about 2MB/s to about 4.5MB/s. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: exynos: Minimise access to SPI FIFO levelRajeshwari Shinde2013-10-08-12/+15
| | | | | | | | | | | | | | | | | | | | | | Accessing SPI registers is slow, but access to the FIFO level register in particular seems to be extraordinarily expensive (I measure up to 600ns). Perhaps it is required to synchronise with the SPI byte output logic which might run at 1/8th of the 40MHz SPI speed (just a guess). Reduce access to this register by filling up and emptying FIFOs more completely, rather than just one word each time around the inner loop. Since the rxfifo value will now likely be much greater that what we read before we fill the txfifo, we only fill the txfifo halfway. This is because if the txfifo is empty, but the rxfifo has data in it, then writing too much data to the txfifo may overflow the rxfifo as data arrives. This speeds up SPI flash reading from about 1MB/s to about 2MB/s on snow. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: exynos: Support a delay after deactivateRajeshwari Shinde2013-10-08-0/+20
| | | | | | | | | | | | | For devices that need some time to react after a spi transaction finishes, add the ability to set a delay. Implement this as a delay on the first/next transaction to avoid any delay in the fairly common case where a SPI transaction is followed by other processing. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: add TI QSPI driverMatt Porter2013-10-07-0/+312
| | | | | | | | | | Adds a SPI master driver for the TI QSPI peripheral. - Added quad read support. - Added memory mapped support. Signed-off-by: Matt Porter <matt.porter@linaro.org> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* spi: mxs_spi: Configure chipselect after block resetMarek Vasut2013-08-27-9/+3
| | | | | | | | | | | | The chipselect must be written into the CTRL0 register after the SSP block is reset, otherwise the block will always use ChipSelect #0. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* powerpc: Fix CamelCase checkpatch warningsPrabhakar Kushwaha2013-08-20-1/+1
| | | | | | | | | | | 85xx, 86xx PowerPC folders have code variables with CamelCase naming conventions. because of this code checkpatch script generates "WARNING: Avoid CamelCase". Convert variables name to normal naming convention and modify board, driver files with updated the new structure. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* spi: Add zynq spi controller driverJagannadha Sutradharudu Teki2013-08-07-0/+281
| | | | | | | | | Zynq spi controller driver supports 2 buses and 3 chipselects on each bus. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* spi: mpc8xxx_spi: Use DIV_ROUND_UP instead of open-codedAxel Lin2013-08-06-1/+1
| | | | | | Use DIV_ROUND_UP to simplify the code. Signed-off-by: Axel Lin <axel.lin@ingics.com>
* spi: fsl_espi: Use DIV_ROUND_UP instead of open-codedAxel Lin2013-08-06-4/+2
| | | | | | Use DIV_ROUND_UP to simplify the code. Signed-off-by: Axel Lin <axel.lin@ingics.com>
* spi: bfin_spi: Use DIV_ROUND_UP instead of open-codedAxel Lin2013-07-31-3/+1
| | | | | | | | Use DIV_ROUND_UP to simplify the code. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-383/+24
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-07-12-17/+11
|\ | | | | | | | | | | | | | | | | | | Fix a trivial conflict in arch/arm/dts/exynos5250.dtsi about gpio and serial. Conflicts: arch/arm/dts/exynos5250.dtsi Signed-off-by: Tom Rini <trini@ti.com>
| * Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-06-28-17/+11
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| | * spi: mxc_spi: Update pre and post divider algorithmDirk Behme2013-06-26-18/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The spi clock divisor is of the form x * (2**y), or x << y, where x is 1 to 16, and y is 0 to 15. Note the similarity with floating point numbers. Convert the desired divisor to the smallest number which is >= desired divisor, and can be represented in this form. The previous algorithm chose a divisor which could be almost twice as large as needed. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
| | * spi: mxc_spi: Fix pre and post divider calculationDirk Behme2013-06-26-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix two issues with the calculation of pre_div and post_div: 1. pre_div: While the calculation of pre_div looks correct, to set the CONREG[15-12] bits pre_div needs to be decremented by 1: The i.MX 6Dual/6Quad Applications Processor Reference Manual (IMX6DQRM Rev. 0, 11/2012) states: CONREG[15-12]: PRE_DIVIDER 0000 Divide by 1 0001 Divide by 2 0010 Divide by 3 ... 1101 Divide by 14 1110 Divide by 15 1111 Divide by 16 I.e. if we want to divide by 2, we have to write 1 to CONREG[15-12]. 2. In case the post divider becomes necessary, pre_div will be divided by 16. So set pre_div to 16, too. And not 15. Both issues above are tested using the following examples: clk_src = 60000000 (60MHz, default i.MX6 ECSPI clock) a) max_hz == 23000000 (23MHz, max i.MX6 ECSPI read clock) -> pre_div = 3 (divide by 3 => CONREG[15-12] == 2) -> post_div = 0 (divide by 1 => CONREG[11- 8] == 0) => 60MHz / 3 = 20MHz SPI clock b) max_hz == 2000000 (2MHz) -> pre_div = 16 (divide by 16 => CONREG[15-12] == 15) -> post_div = 1 (divide by 2 => CONREG[11- 8] == 1) => 60MHz / 32 = 1.875MHz SPI clock c) max_hz == 1000000 (1MHz) -> pre_div = 16 (divide by 16 => CONREG[15-12] == 15) -> post_div = 2 (divide by 4 => CONREG[11- 8] == 2) => 60MHz / 64 = 937.5kHz SPI clock d) max_hz == 500000 (500kHz) -> pre_div = 16 (divide by 16 => CONREG[15-12] == 15) -> post_div = 3 (divide by 8 => CONREG[11- 8] == 3) => 60MHz / 128 = 468.75kHz SPI clock Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
* | | cros: exynos: add SPI support for cros_ecHung-ying Tyan2013-06-26-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds SPI support for carrying out the cros_ec protocol. Signed-off-by: Hung-ying Tyan <tyanh@chromium.org> Signed-off-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* | | spi: mxc_spi: Use DIV_ROUND_UP at appropriate placesAxel Lin2013-06-22-3/+3
| | | | | | | | | | | | | | | | | | | | | This change slightly improves readability. Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | | spi: cf_qspi: Use DIV_ROUND_UP at appropriate placeAxel Lin2013-06-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This change slightly improves readability. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Richard Retanubun <richardretanubun@ruggedcom.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2013-06-13-24/+62
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| * | spi: tegra20_sflash: Remove redundant code to set bus and cs of struct spi_slaveAxel Lin2013-06-13-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | It's done in spi_alloc_slave(), thus remove the redundant code. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | spi: tegra114_spi: Convert to use spi_alloc_slave()Axel Lin2013-06-13-3/+1
| | | | | | | | | | | | | | | | | | Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | spi: armada100_spi: Remove unnecessary NULL test for dout and dinAxel Lin2013-06-13-9/+2
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Ajay Bhargav <ajay.bhargav@einfochips.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
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