| Commit message (Collapse) | Author | Age | Lines |
|---|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The system PMIC registers may not be accessible in u-boot via SPI if
function pmic_reg() is called in the latter part of boot up process in u-boot.
It is because the imx_spi_slave structure is allocated from malloc() in
the spi_setup_slave() function. However, this structure is not completely
initialized, which may result in using a dirty control register value
at CSPI during transfer.
memset() the imx_spi_slave structure after malloc() can resolve this problem
Please refer to CT39243849.
Signed-off-by: Robby Cai <R63905@freescale.com>
|
| |
|
|
|
|
|
| |
CSPI: make spi_get_cfg platform specific
move the spi_get_cfg out of the cspi/ecspi driver
Signed-off-by:Jason Liu <r64343@freescale.com>
|
| |
|
|
|
|
| |
Speed is too slow on MX25, remove udelay in cspi driver
Signed-off-by: Sammy He <r62914@freescale.com>
|
| |
|
|
|
|
| |
Reset CPLD registers to fix reboot/reset failure issue.
Signed-off-by: Sammy He <r62914@freescale.com>
|
| |
|
|
|
|
|
| |
1. Add imx cspi support for cpld access.
2. Add smc911x ethernet support from cpld.
Signed-off-by: Sammy He <r62914@freescale.com>
|
| |
|
|
|
|
|
|
|
| |
This patch will fix three issues:
1. Add boot device detection.
2. Use right nand command in anroid for recovery mode.
3. Recovery mode code clean.
Signed-off-by: Terry Lv <r65388@freescale.com>
|
| |
|
|
|
|
| |
Support Atmel AT45DB321D SPI NOR flash.
Signed-off-by: Terry Lv <r65388@freescale.com>
|
| |
|
|
|
|
| |
Add FEC support for BBG2.
Signed-off-by: Terry Lv <r65388@freescale.com>
|
| |
|
|
|
|
| |
spi nor boot support for BBG2.
Signed-off-by: Terry Lv <r65388@freescale.com>
|
| |
|
|
|
|
|
| |
Unify both MCF5227x and MCF5445x DSPI driver in CPU to
driver/spi folder for common use.
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
|
| |\
| |
| |
| |
| |
| |
| | |
Conflicts:
drivers/spi/Makefile
Signed-off-by: Wolfgang Denk <wd@denx.de>
|
| | |
| |
| |
| |
| |
| | |
This patch adds a SPI driver for the Marvell Kirkwood SoC's.
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
|
| |/
|
|
| |
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
|
| |
|
|
|
|
|
| |
CS4 on SPI0 has a dedicated PH8 pin which needs to be enabled as a
peripheral in order to work.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
|
| |
|
|
|
|
| |
calculate dynamically the clock rate and pllb setting for usb
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Blackfin SPI driver was not driving the SPI chip-select high before
putting the chip-select signals into tri-state mode. This is probably
something that slipped by unnoticed in most designs. If the signals are
put directly into a tri-state mode, then the board is relying on the
pull-up resistors to pull up the chip-select before the next transaction.
Most of the time this is fine, except when you have two transactions that
follow each other very closely, such as the flash erase and read status
register commands. In this case I was seeing a 500ns separation between
the transactions. In my setup, with a 10kOhm pull-up, it would meet
timing spec about half the time and resulted in intermittent errors. (A
stronger pull up would fix this, but our design is targeted for low power
consumption and a 3.3kOhm @ 3.3v is 3.3mW of needless power consumption.)
I modified the spi_cs_deactivate() function in bfin_spi.c to drive the
chip-selects high before putting them into tri-state. For me, this
resulted in a rise time of 5ns instead of the previous rise time of about
1us, and fully satisfied the timing spec of the chip.
Signed-off-by: Todor I Mollov <tmollov@ucsd.edu>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
|
| |
|
|
| |
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
| |
|
|
| |
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
|
| |
|
|
|
|
|
|
| |
Since the PORTJ on the BF537 is peripheral-only (no GPIO functionality),
then there is no PORTJ_FER register for us to worry about.
Signed-off-by: Sonic Zhang <Sonic.Zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
|
| |
|
|
|
|
|
|
|
| |
Some SPI devices have special requirements on chip-select handling.
With this patch we can use a GPIO as a chip-select and strictly follow
the SPI_XFER_BEGIN and SPI_XFER_END flags.
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
| |
|
|
|
|
|
|
| |
Fix setting the SPI Control register, 8 and 16-bit transfers
and a wrong pointer in the free routine in the mxc_spi driver.
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
| |
|
|
|
|
| |
This fills out the SPI backend for the Blackfin on-chip SPI peripheral.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
|
| |
|
|
| |
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
| |
|
|
| |
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
| |
|
|
| |
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This adds a driver for the SPI controller found on most AT91 and AVR32
chips, implementing the new SPI API.
Changed in v4:
- Update to new API
- Handle zero-length transfers appropriately. The user may send a
zero-length SPI transfer with SPI_XFER_END set in order to
deactivate the chip select after a series of transfers with chip
select active. This is useful e.g. when polling the status
register of DataFlash.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This patch gets rid of the spi_chipsel table and adds a handful of new
functions that makes the SPI layer cleaner and more flexible.
Instead of the spi_chipsel table, each board that wants to use SPI
gets to implement three hooks:
* spi_cs_activate(): Activates the chipselect for a given slave
* spi_cs_deactivate(): Deactivates the chipselect for a given slave
* spi_cs_is_valid(): Determines if the given bus/chipselect
combination can be activated.
Not all drivers may need those extra functions however. If that's the
case, the board code may just leave them out (assuming they know what
the driver needs) or rely on the linker to strip them out (assuming
--gc-sections is being used.)
To set up communication parameters for a given slave, the driver needs
to call spi_setup_slave(). This returns a pointer to an opaque
spi_slave struct which must be passed as a parameter to subsequent SPI
calls. This struct can be freed by calling spi_free_slave(), but most
driver probably don't want to do this.
Before starting one or more SPI transfers, the driver must call
spi_claim_bus() to gain exclusive access to the SPI bus and initialize
the hardware. When all transfers are done, the driver must call
spi_release_bus() to make the bus available to others, and possibly
shut down the SPI controller hardware.
spi_xfer() behaves mostly the same as before, but it now takes a
spi_slave parameter instead of a spi_chipsel function pointer. It also
got a new parameter, flags, which is used to specify chip select
behaviour. This may be extended with other flags in the future.
This patch has been build-tested on all powerpc and arm boards
involved. I have not tested NIOS since I don't have a toolchain for it
installed, so I expect some breakage there even though I've tried
fixing up everything I could find by visual inspection.
I have run-time tested this on AVR32 ATNGW100 using the atmel_spi and
DataFlash drivers posted as a follow-up. I'd like some help testing
other boards that use the existing SPI API.
But most of all, I'd like some comments on the new API. Is this stuff
usable for everyone? If not, why?
Changed in v4:
- Build fixes for various boards, drivers and commands
- Provide common struct spi_slave definition that can be extended by
drivers
- Pass a struct spi_slave * to spi_cs_activate and spi_cs_deactivate
- Make default bus and mode build-time configurable
- Override default SPI bus ID and mode on mx32ads and imx31_litekit.
Changed in v3:
- Add opaque struct spi_slave for controller-specific data associated
with a slave.
- Add spi_claim_bus() and spi_release_bus()
- Add spi_free_slave()
- spi_setup() is now called spi_setup_slave() and returns a
struct spi_slave
- soft_spi now supports four SPI modes (CPOL|CPHA)
- Add bus parameter to spi_setup_slave()
- Convert the new i.MX32 SPI driver
- Convert the new MC13783 RTC driver
Changed in v2:
- Convert the mpc8xxx_spi driver and the mpc8349emds board to the
new API.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Tested-by: Guennadi Liakhovetski <lg@denx.de>
|
| |
|
|
|
|
|
|
|
|
|
| |
This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).
Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.
Signed-off-by: Wolfgang Denk <wd@denx.de>
|
| |
|
|
|
|
|
|
|
| |
This is an SPI driver for i.MX and MXC based SoCs from Freescale. So far
only implemented and tested on i.MX31, can with a modified register layout
and definitions be used for i.MX27, I think, MXC CPUs have similar SPI
controllers too.
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
|
| |
|
|
|
|
|
| |
This driver should only compile if CONFIG_MPC8XXX_SPI is set
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
|
| |
|
|
|
|
| |
..and rm unused CONFIG_FSL_SPI define
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
|
|
|
This patch adds support for the SPI controller found on Freescale PowerPC
processors such as the MCP834x family. Additionally, a new config option,
CONFIG_HARD_SPI, is added for general purpose SPI controller use.
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
|
