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* ENGR00124908 CSPI: make spi_get_cfg platform specificJason Liu2010-07-07-51/+6
| | | | | | | CSPI: make spi_get_cfg platform specific move the spi_get_cfg out of the cspi/ecspi driver Signed-off-by:Jason Liu <r64343@freescale.com>
* ENGR00119486 MX25: Improve Lan9217 ethernet transfer speedSammy He2009-12-18-3/+1
| | | | | | Speed is too slow on MX25, remove udelay in cspi driver Signed-off-by: Sammy He <r62914@freescale.com>
* ENGR00118816 Fix reboot/reset failure with image on nandSammy He2009-11-26-0/+28
| | | | | | Reset CPLD registers to fix reboot/reset failure issue. Signed-off-by: Sammy He <r62914@freescale.com>
* ENGR00118576 MX25: Support Smc911x ethernetSammy He2009-11-20-3/+370
| | | | | | | 1. Add imx cspi support for cpld access. 2. Add smc911x ethernet support from cpld. Signed-off-by: Sammy He <r62914@freescale.com>
* ENGR00118362: Correct recovery NAND cmdTerry Lv2009-11-12-1/+1
| | | | | | | | | This patch will fix three issues: 1. Add boot device detection. 2. Use right nand command in anroid for recovery mode. 3. Recovery mode code clean. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00114393: Support Atmel AT45DB321D SPI NOR flash.Terry Lv2009-09-10-1/+1
| | | | | | Support Atmel AT45DB321D SPI NOR flash. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00113611: Add FEC support for BBG2.Terry Lv2009-09-10-5/+9
| | | | | | Add FEC support for BBG2. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00112845 spi nor boot and pmic support for BBG2.Terry Lv2009-09-10-0/+458
| | | | | | spi nor boot support for BBG2. Signed-off-by: Terry Lv <r65388@freescale.com>
* Coldfire: Consolidate DSPI driverTsiChung Liew2009-07-14-0/+358
| | | | | | | Unify both MCF5227x and MCF5445x DSPI driver in CPU to driver/spi folder for common use. Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2009-07-07-0/+186
|\ | | | | | | | | | | | | Conflicts: drivers/spi/Makefile Signed-off-by: Wolfgang Denk <wd@denx.de>
| * spi: Add Marvell Kirkwood SPI driverPrafulla Wadaskar2009-06-26-0/+186
| | | | | | | | | | | | This patch adds a SPI driver for the Marvell Kirkwood SoC's. Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
* | mpc52xx: Add SPI driver.Grzegorz Bernacki2009-06-14-0/+110
|/ | | | Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
* Blackfin: spi: fix pin handling of SPI0 SSEL4Mike Frysinger2009-05-29-1/+1
| | | | | | | CS4 on SPI0 has a dedicated PH8 pin which needs to be enabled as a peripheral in order to work. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* at91sam9/at91cap: improve clock frameworkJean-Christophe PLAGNIOL-VILLARD2009-04-16-3/+4
| | | | | | calculate dynamically the clock rate and pllb setting for usb Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Blackfin: spi: make cs deassert function deterministicTodor I Mollov2009-04-06-1/+15
| | | | | | | | | | | | | | | | | | | | | | Blackfin SPI driver was not driving the SPI chip-select high before putting the chip-select signals into tri-state mode. This is probably something that slipped by unnoticed in most designs. If the signals are put directly into a tri-state mode, then the board is relying on the pull-up resistors to pull up the chip-select before the next transaction. Most of the time this is fine, except when you have two transactions that follow each other very closely, such as the flash erase and read status register commands. In this case I was seeing a 500ns separation between the transactions. In my setup, with a 10kOhm pull-up, it would meet timing spec about half the time and resulted in intermittent errors. (A stronger pull up would fix this, but our design is targeted for low power consumption and a 3.3kOhm @ 3.3v is 3.3mW of needless power consumption.) I modified the spi_cs_deactivate() function in bfin_spi.c to drive the chip-selects high before putting them into tri-state. For me, this resulted in a rise time of 5ns instead of the previous rise time of about 1us, and fully satisfied the timing spec of the chip. Signed-off-by: Todor I Mollov <tmollov@ucsd.edu> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* at91: move dataflash spi driver to drivers/spiJean-Christophe PLAGNIOL-VILLARD2009-04-04-0/+158
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Blackfin: add BF538/BF539 SPI portmux handlingMike Frysinger2009-04-02-0/+18
| | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: spi: there is no PORTJ_FER MMR on BF537Sonic Zhang2009-03-23-5/+3
| | | | | | | | Since the PORTJ on the BF537 is peripheral-only (no GPIO functionality), then there is no PORTJ_FER register for us to worry about. Signed-off-by: Sonic Zhang <Sonic.Zhang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* i.MX31: support GPIO as a chip-select in the mxc_spi driverGuennadi Liakhovetski2009-02-24-8/+56
| | | | | | | | | Some SPI devices have special requirements on chip-select handling. With this patch we can use a GPIO as a chip-select and strictly follow the SPI_XFER_BEGIN and SPI_XFER_END flags. Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* i.MX31: fix SPI driver for shorter than 32 bitGuennadi Liakhovetski2009-02-24-11/+20
| | | | | | | | Fix setting the SPI Control register, 8 and 16-bit transfers and a wrong pointer in the free routine in the mxc_spi driver. Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Blackfin: add driver for on-chip SPI controllerMike Frysinger2009-02-02-0/+344
| | | | | | This fills out the SPI backend for the Blackfin on-chip SPI peripheral. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-7/+7
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* soft_spi: move to drivers/spiJean-Christophe PLAGNIOL-VILLARD2008-08-29-1/+195
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Move conditional compilation of MPC8XXX SPI driver to MakefileBen Warren2008-07-01-3/+1
| | | | Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* atmel_spi: Driver for the Atmel SPI controllerHans-Christian Egtvedt2008-06-03-0/+306
| | | | | | | | | | | | | | | This adds a driver for the SPI controller found on most AT91 and AVR32 chips, implementing the new SPI API. Changed in v4: - Update to new API - Handle zero-length transfers appropriately. The user may send a zero-length SPI transfer with SPI_XFER_END set in order to deactivate the chip select after a series of transfers with chip select active. This is useful e.g. when polling the status register of DataFlash. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
* SPI API improvementsHaavard Skinnemoen2008-06-03-38/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch gets rid of the spi_chipsel table and adds a handful of new functions that makes the SPI layer cleaner and more flexible. Instead of the spi_chipsel table, each board that wants to use SPI gets to implement three hooks: * spi_cs_activate(): Activates the chipselect for a given slave * spi_cs_deactivate(): Deactivates the chipselect for a given slave * spi_cs_is_valid(): Determines if the given bus/chipselect combination can be activated. Not all drivers may need those extra functions however. If that's the case, the board code may just leave them out (assuming they know what the driver needs) or rely on the linker to strip them out (assuming --gc-sections is being used.) To set up communication parameters for a given slave, the driver needs to call spi_setup_slave(). This returns a pointer to an opaque spi_slave struct which must be passed as a parameter to subsequent SPI calls. This struct can be freed by calling spi_free_slave(), but most driver probably don't want to do this. Before starting one or more SPI transfers, the driver must call spi_claim_bus() to gain exclusive access to the SPI bus and initialize the hardware. When all transfers are done, the driver must call spi_release_bus() to make the bus available to others, and possibly shut down the SPI controller hardware. spi_xfer() behaves mostly the same as before, but it now takes a spi_slave parameter instead of a spi_chipsel function pointer. It also got a new parameter, flags, which is used to specify chip select behaviour. This may be extended with other flags in the future. This patch has been build-tested on all powerpc and arm boards involved. I have not tested NIOS since I don't have a toolchain for it installed, so I expect some breakage there even though I've tried fixing up everything I could find by visual inspection. I have run-time tested this on AVR32 ATNGW100 using the atmel_spi and DataFlash drivers posted as a follow-up. I'd like some help testing other boards that use the existing SPI API. But most of all, I'd like some comments on the new API. Is this stuff usable for everyone? If not, why? Changed in v4: - Build fixes for various boards, drivers and commands - Provide common struct spi_slave definition that can be extended by drivers - Pass a struct spi_slave * to spi_cs_activate and spi_cs_deactivate - Make default bus and mode build-time configurable - Override default SPI bus ID and mode on mx32ads and imx31_litekit. Changed in v3: - Add opaque struct spi_slave for controller-specific data associated with a slave. - Add spi_claim_bus() and spi_release_bus() - Add spi_free_slave() - spi_setup() is now called spi_setup_slave() and returns a struct spi_slave - soft_spi now supports four SPI modes (CPOL|CPHA) - Add bus parameter to spi_setup_slave() - Convert the new i.MX32 SPI driver - Convert the new MC13783 RTC driver Changed in v2: - Convert the mpc8xxx_spi driver and the mpc8349emds board to the new API. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Tested-by: Guennadi Liakhovetski <lg@denx.de>
* Big white-space cleanup.Wolfgang Denk2008-05-21-1/+1
| | | | | | | | | | | This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de>
* New i.MX31 SPI driverGuennadi Liakhovetski2008-04-18-0/+167
| | | | | | | | | This is an SPI driver for i.MX and MXC based SoCs from Freescale. So far only implemented and tested on i.MX31, can with a modified register layout and definitions be used for i.MX27, I think, MXC CPUs have similar SPI controllers too. Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
* Fix conditional compilation of mpx8xxx_spi driverBen Warren2008-01-29-2/+2
| | | | | | | This driver should only compile if CONFIG_MPC8XXX_SPI is set Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* codingstyle cleanup for spi driverKim Phillips2008-01-17-29/+34
| | | | | | ..and rm unused CONFIG_FSL_SPI define Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Add support for a Freescale non-CPM SPI controllerBen Warren2008-01-17-0/+184
This patch adds support for the SPI controller found on Freescale PowerPC processors such as the MCP834x family. Additionally, a new config option, CONFIG_HARD_SPI, is added for general purpose SPI controller use. Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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