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* lpc32xx: add LPC32xx SSP support (SPI mode)Albert ARIBAUD \(3ADEV\)2015-04-10-0/+1
| | | | | Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* spi: Add designware master SPI DM driver used on SoCFPGAStefan Roese2014-12-06-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the driver for the Designware master SPI controller. This IP core is integrated on the Altera SoCFPGA. This implementation is a driver model (DM) implementation. So multiple SPI drivers can be used. Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller used to connect the SPI NOR flashes. Without DM, using multiple SPI drivers is not possible. This driver is very loosely based on the Linux driver. Most of the Linux driver is removed. Only the polling loop for the transfer is really used from this driver, as we don't support interrupts and DMA right now. This is tested on the SoCrates SoCFPGA board using the SPI pins on the P14 header. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: Add Cadence QSPI DM driver used by SoCFPGAStefan Roese2014-12-06-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This driver is cloned from the Altera Rockerboard.org U-Boot repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some modification to support the U-Boot driver model (DM). As mentioned above, in this new version I ported this driver to the new driver model (DM). One big advantage of this move is that now multiple SPI drivers can be enabled on one platform. And since the SoCFPGA also has the Designware SPI master controller integrated, this feature is really needed to support both controllers. Because of this, this series needs the DT support for SoCFPGA to be applied. For DT based probing in the SPI DM. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* dm: tegra: spi: Convert to driver modelSimon Glass2014-10-22-1/+0
| | | | | | | | | | | | | | This converts the Tegra SPI drivers to use driver model. This is tested on: - Tegra20 - trimslice - Tegra30 - beaver - Tegra124 - dalmore (not tested on Tegra124) Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: spi: Add soft_spi implementationSimon Glass2014-10-22-0/+1
| | | | | | | | Add a new implementation of soft_spi that uses device tree to specify the GPIOs. This will replace soft_spi_legacy for boards which use driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* dm: spi: Rename soft_spi.c to soft_spi_legacy.cSimon Glass2014-10-22-1/+1
| | | | | | | | Reserve the 'normal' name for use by driver model, and rename the old driver so that it is clear that it is for 'legacy' drivers only. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* dm: sandbox: Add a SPI emulation uclassSimon Glass2014-10-22-0/+1
| | | | | | | | | | | | | | | | | U-Boot includes a SPI emulation driver already but it is not explicit, and is hidden in the SPI flash code. Conceptually with sandbox's SPI implementation we have a layer which creates SPI bus transitions and a layer which interprets them, currently only for SPI flash. The latter is actually an emulation, and it should be possible to add more than one emulation - not just SPI flash. Add a SPI emulation uclass so that other emulations can be plugged in to support different types of emulated devices on difference buses/chip selects. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* dm: spi: Add a uclass for SPISimon Glass2014-10-22-0/+4
| | | | | | | | | | | | | | | | Add a uclass which provides access to SPI buses and includes operations required by SPI. For a time driver model will need to co-exist with the legacy SPI interface so some parts of the header file are changed depending on which is in use. The exports are adjusted also since some functions are not available with driver model. Boards must define CONFIG_DM_SPI to use driver model for SPI. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> (Discussed some follow-up comments which will address in future add-ons)
* arm: ep9315: Return back Cirrus Logic EDB9315A board supportSergey Kostanbaev2014-07-04-0/+1
| | | | | | | This patch returns back support for old ep93xx processors family Signed-off-by: Sergey Kostanbaev <sergey.kostanbaev@gmail.com> Cc: albert.u.boot@aribaud.net
* arm: vf610: Add QSPI driver supportAlison Wang2014-06-09-0/+1
| | | | | | | Add Freescale QSPI driver support for VF610. Signed-off-by: Alison Wang <Huan.Wang@freescale.com> Signed-off-by: Chao Fu <b44548@freescale.com>
* spi: Add Faraday SPI controller supportKuo-Jung Su2014-01-11-0/+1
| | | | | | | | | | | | | | | | | The Faraday FTSSP010 is a multi-function controller which supports I2S/SPI/SSP/AC97/SPDIF. However This patch implements only the SPI mode. NOTE: The DMA and CS/Clock control logic has been altered since hardware revision 1.19.0. So this patch would first detects the revision id of the underlying chip, and then switch to the corresponding software control routines. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> CC: Tom Rini <trini@ti.com>
* spi: Add support SH Quad SPI driverNobuhiro Iwamatsu2013-12-18-0/+1
| | | | | | | | | This patch adds a driver for Renesas SoC's Quad SPI bus. This supports with 8 bits per transfer to use with SPI flash. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sandbox: spi: Add SPI emulation busMike Frysinger2013-12-09-0/+1
| | | | | | | This adds a SPI framework for people to hook up simulated SPI clients. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* drivers: convert makefiles to Kbuild styleMasahiro Yamada2013-10-31-53/+31
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* spi: add TI QSPI driverMatt Porter2013-10-07-0/+1
| | | | | | | | | | Adds a SPI master driver for the TI QSPI peripheral. - Added quad read support. - Added memory mapped support. Signed-off-by: Matt Porter <matt.porter@linaro.org> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* spi: Add zynq spi controller driverJagannadha Sutradharudu Teki2013-08-07-0/+1
| | | | | | | | | Zynq spi controller driver supports 2 buses and 3 chipselects on each bus. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-17/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-03-28-2/+4
|\ | | | | | | | | | | | | Conflicts: drivers/spi/tegra20_sflash.c include/fdtdec.h lib/fdtdec.c
| * tegra114: add SPI driverAllen Martin2013-03-25-0/+1
| | | | | | | | | | | | | | | | | | | | Add driver for tegra114 SPI controller. This controller is not compatible with either the tegra20 or tegra30 controllers, so it requires a new driver. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * spi: add common fdt SPI driver interfaceAllen Martin2013-03-25-0/+1
| | | | | | | | | | | | | | | | | | | | | | Add a common interface to fdt based SPI drivers. Each driver is represented by a table entry in fdt_spi_drivers[]. If there are multiple SPI drivers in the table, the first driver to return success from spi_init() will be registered as the SPI driver. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * tegra: spi: rename tegra SPI driversAllen Martin2013-03-25-2/+2
| | | | | | | | | | | | | | | | | | Rename tegra SPI drivers to tegra20_flash and tegra20_slink in preparation for commonization and addition of tegra114_spi. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* | x86: spi: Add Intel ICH driverSimon Glass2013-03-19-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This supports Intel ICH7/9. The Intel controller is a little unusual in that it is mostly intended for use with SPI flash, and has some optimisations and features specifically for that application. In particular it is not possible to support ongoing transactions that continue over many calls with SPI_XFER_BEGIN and SPI_XFER_END. This driver supports writes of up to 64 bytes at a time, the limit for the controller. Future work will improve this. Signed-off-by: Bernie Thompson <bhthompson@chromium.org> Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* | spi: Add function to allocate a new SPI slaveSimon Glass2013-03-19-0/+3
|/ | | | | | | | | | At present it is difficult to extend the SPI structure since all drivers allocate it themselves, and few of them zero all fields. Add a new function spi_alloc_slave() which can be used by SPI drivers to perform this allocation, and thus ensure that all drivers can better cope with SPI structure changes. Signed-off-by: Simon Glass <sjg@chromium.org>
* blackfin: add bf6xx spi driverScott Jiang2013-03-04-0/+1
| | | | | | | | | | Spi driver for bf60x is different from old one, so implement a new driver for it. Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bob Liu <lliubbo@gmail.com> Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
* tegra: add SPI SLINK driverAllen Martin2013-02-11-0/+1
| | | | | | | | | | | | | | | | | | | | | | Add driver for tegra SPI "SLINK" style driver. This controller is similar to the tegra20 SPI "SFLASH" controller. The difference is that the SLINK controller is a genernal purpose SPI controller and the SFLASH controller is special purpose and can only talk to FLASH devices. In addition there are potentially many instances of an SLINK controller on tegra and only a single instance of SFLASH. Tegra20 is currently ths only version of tegra that instantiates an SFLASH controller. This driver supports basic PIO mode of operation and is configurable (CONFIG_OF_CONTROL) to be driven off devicetree bindings. Up to 4 devices per controller may be attached, although typically only a single chip select line is exposed from tegra per controller so in reality this is usually limited to 1. To enable this driver, use CONFIG_TEGRA_SLINK Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* SPI: Add SPI Driver for EXYNOS.Rajeshwari Shinde2012-11-15-0/+1
| | | | | | | | | | | | | | This patch adds SPI driver for EXYNOS. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Acked-by: Mike Frysinger <vapier@gentoo.org> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: jy0922.shim@samsung.com Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* ColdFire: Queued SPI driverRichard Retanubun2012-09-20-0/+1
| | | | | | | | | | | | This patch adds a driver for Freescale Colfire Queued SPI bus. Coded to work with 8 bits per transfer to use with SPI flash. CPOL, CPHA, and CS_ACTIVE_HIGH can be configured. Tested with MCF5270 which have 4 chip selects. Activate by #define CONFIG_CF_QSPI in board config. Signed-off-by: Richard Retanubun <richardretanubun@ruggedcom.com>
* spi: Fix merge conflicts - MakefileMichal Simek2012-08-07-1/+0
| | | | | | | | | | | | | | | The patch "spi: tegra2: rename tegra2_spi.* to tegra_spi.*" (sha1: edffa63d3d6e76991998789f9fcbaa483731ca65) renamed tegra2_spi.c to tegra_spi.c and the patch "Merge branch 'master' of git://git.denx.de/u-boot-microblaze" (sha1: d978780b2e676c005460cd561f4f15b5220bdf49) has wrongly resolved confict. This patch fix it. Signed-off-by: Michal Simek <monstr@monstr.eu>
* Merge branch 'master' of git://git.denx.de/u-boot-microblazeWolfgang Denk2012-07-31-0/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-microblaze: microblaze: Wire up SPI driver spi: microblaze: Adds driver for Xilinx SPI controller microblaze: intc: Clear interrupt code microblaze: Call serial multi initialization microblaze: Move __udelay implementation microblaze: Remove extern from board.c microblaze: Wire up dts configuration fdt: Add board specific dts inclusion microblaze: Move individual board linker scripts to common script in cpu tree. microblaze: Add gpio.h microblaze: Add missing undefs for UBI and UBIFS microblaze: Expand and correct configuration comments microblaze: Enable ubi support microblaze: Avoid compile error on systems without cfi flash microblaze: Remove wrong define CONFIG_SYS_FLASH_PROTECTION Conflicts: drivers/spi/Makefile Signed-off-by: Wolfgang Denk <wd@denx.de>
| * spi: microblaze: Adds driver for Xilinx SPI controllerStephan Linz2012-07-31-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is an improved version of the driver patch original submitted by Graeme Smecher <graeme.smecher@mail.mcgill.ca> The changes are: - remove hard coded Xilinx BSP defines (XPAR_SPI_*) and use CONFIG_SYS_SPI_BASE from config.h instead - add extensive register struct definitions - remove offset calculation for register access and use the new register struct instead - move default SPI controller configuration from spi_setup_slave() to spi_claim_bus() - add spi_set_speed() - insert SPI controller deactivation in spi_release_bus() - protect while loops in spi_xfer() with counter / timeouts - support SPI mode flags: LSB_FIRST, CPHA, CPOL, LOOP Come from: http://patchwork.ozlabs.org/patch/71797/ Signed-off-by: Stephan Linz <linz@li-pro.net> Tested-by: Michal Simek <monstr@monstr.eu>
* | spi: tegra2: rename tegra2_spi.* to tegra_spi.*Tom Warren2012-07-07-1/+1
|/ | | | | | | | In anticipation of Tegra3 support, start removing/renaming Tegra2-specific files. No functional changes (yet). Also updated copyright to 2012. Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra2: spi: Add SPI driver for Tegra2 SOCTom Warren2011-12-24-0/+1
| | | | | | | This driver supports SPI on Tegra2, running at 48MHz. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
* iMX28: Add SPI driverMarek Vasut2011-11-11-0/+1
| | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
* SPI: Add SPI driver support for Marvell Armada100Ajay Bhargav2011-10-27-0/+1
| | | | | | | This patch provides support for SPI emulated over SSP for Marvell Armada100 SOC. Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
* andes_spi: add andes_spi interfaceMacpaul Lin2011-07-25-0/+1
| | | | | | | | | andes_spi is an spi interface developed by Andes Tech. Signed-off-by: Macpaul Lin <macpaul@andestech.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Mike Frysinger <vapier@gentoo.org> Acked-by: Mike Frysinger <vapier@gentoo.org>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2011-04-30-0/+1
|\
| * powerpc: eSPI and eSPI controller supportMingkai Hu2011-04-29-0/+1
| | | | | | | | | | | | | | | | Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Singed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Cc: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | spi: add new driver for OpenCores tiny_spiThomas Chou2011-04-30-0/+1
|/ | | | | | | | This patch adds support for OpenCores tiny_spi. http://opencores.org/project,tiny_spi Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
* spi: add support SuperH SPI moduleYoshihiro Shimoda2011-02-02-0/+1
| | | | | | | SH7757 has SPI module. This patch supports it. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* OMAP3: SPI driverDirk Behme2010-12-11-0/+1
| | | | | | CC: Ruslan N. Araslanov <byaaka@yandex.ru> Signed-off-by: Ruslan Araslanov <ruslan.araslanov@vitecmm.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* Switch from archive libraries to partial linkingSebastien Carlier2010-11-17-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, weak symbols were not overridden by non-weak symbols found in archive libraries when linking with recent versions of binutils. As stated in the System V ABI, "the link editor does not extract archive members to resolve undefined weak symbols". This commit changes all Makefiles to use partial linking (ld -r) instead of creating library archives, which forces all symbols to participate in linking, allowing non-weak symbols to override weak symbols as intended. This approach is also used by Linux, from which the gmake function cmd_link_o_target (defined in config.mk and used in all Makefiles) is inspired. The name of each former library archive is preserved except for extensions which change from ".a" to ".o". This commit updates references accordingly where needed, in particular in some linker scripts. This commit reveals board configurations that exclude some features but include source files that depend these disabled features in the build, resulting in undefined symbols. Known such cases include: - disabling CMD_NET but not CMD_NFS; - enabling CONFIG_OF_LIBFDT but not CONFIG_QE. Signed-off-by: Sebastien Carlier <sebastien.carlier@gmail.com>
* spi: add altera spi controller supportThomas Chou2010-05-28-0/+1
| | | | | | | | | | | | | This patch adds the driver of altera spi controller, which is used as epcs/spi flash controller. It also works with mmc_spi driver. This driver support more than one spi bus, with base list declared #define CONFIG_SYS_ALTERA_SPI_LIST { BASE_0,BASE_1,... } Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Tested-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
* TI DaVinci: Driver for the davinci SPI controllerSekhar Nori2010-02-12-0/+1
| | | | | | | | | This adds a driver for the SPI controller found on davinci based SoCs from Texas Instruments. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* Coldfire: Consolidate DSPI driverTsiChung Liew2009-07-14-0/+1
| | | | | | | Unify both MCF5227x and MCF5445x DSPI driver in CPU to driver/spi folder for common use. Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2009-07-07-0/+1
|\ | | | | | | | | | | | | Conflicts: drivers/spi/Makefile Signed-off-by: Wolfgang Denk <wd@denx.de>
| * spi: Add Marvell Kirkwood SPI driverPrafulla Wadaskar2009-06-26-0/+1
| | | | | | | | | | | | This patch adds a SPI driver for the Marvell Kirkwood SoC's. Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
* | mpc52xx: Add SPI driver.Grzegorz Bernacki2009-06-14-0/+1
|/ | | | Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
* at91: move dataflash spi driver to drivers/spiJean-Christophe PLAGNIOL-VILLARD2009-04-04-0/+1
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Blackfin: add driver for on-chip SPI controllerMike Frysinger2009-02-02-0/+1
| | | | | | This fills out the SPI backend for the Blackfin on-chip SPI peripheral. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* soft_spi: move to drivers/spiJean-Christophe PLAGNIOL-VILLARD2008-08-29-1/+2
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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